From mboxrd@z Thu Jan  1 00:00:00 1970
From: Prabhakar Kushwaha <prabhakar@freescale.com>
Date: Tue, 21 Aug 2012 15:07:05 +0530
Subject: [U-Boot] [PATCH v3] powerpc/85xx: clear out TLB on boot
In-Reply-To: <20120820231008.GA28444@tyr.buserror.net>
References: <20120820231008.GA28444@tyr.buserror.net>
Message-ID: <503356C1.8040706@freescale.com>
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To: u-boot@lists.denx.de

On 08/21/2012 04:40 AM, Scott Wood wrote:
> Instead of just shooting down the entry that covers CCSR, clear out
> every TLB entry that isn't the one that we're executing out of.
>
> Signed-off-by: Scott Wood<scottwood@freescale.com>
> ---
> v3: Don't skip the "last TLB entry" check when skipping a TLB entry
> in the invalidation loop.  Sorry about the rapid updates -- this should
> be the last one for this patch unless someone notices a problem.
>
> Prabhakar, can you test that this doesn't break debugging?
>
>   

Verified debugging on P1010RDB with NOR, NAND boot and SPI boot.

No debug is breaking


Thanks,
Prabhakar