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From: "Andreas Bießmann" <andreas.devel@googlemail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 4/5] at91: 9x5: change SMC config timing that both works for PMECC & non-PMECC.
Date: Tue, 21 Aug 2012 12:46:21 +0200	[thread overview]
Message-ID: <503366FD.4090904@gmail.com> (raw)
In-Reply-To: <1345093515-16761-5-git-send-email-josh.wu@atmel.com>

Dear Josh Wu,

On 16.08.2012 07:05, Josh Wu wrote:
> Signed-off-by: Josh Wu <josh.wu@atmel.com>
> ---
>  board/atmel/at91sam9x5ek/at91sam9x5ek.c |   12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
> index 17db0fd..8dc24ab 100644
> --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
> +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
> @@ -63,13 +63,13 @@ static void at91sam9x5ek_nand_hw_init(void)
>  	writel(csa, &matrix->ebicsa);
>  
>  	/* Configure SMC CS3 for NAND/SmartMedia */
> -	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
> -		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
> +	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
> +		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
>  		&smc->cs[3].setup);
> -	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
> -		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
> +	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
> +		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
>  		&smc->cs[3].pulse);
> -	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
> +	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
>  		&smc->cs[3].cycle);
>  	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
>  		AT91_SMC_MODE_EXNW_DISABLE |
> @@ -78,7 +78,7 @@ static void at91sam9x5ek_nand_hw_init(void)
>  #else /* CONFIG_SYS_NAND_DBW_8 */
>  		AT91_SMC_MODE_DBW_8 |
>  #endif
> -		AT91_SMC_MODE_TDF_CYCLE(3),
> +		AT91_SMC_MODE_TDF_CYCLE(1),
>  		&smc->cs[3].mode);
>  
>  	writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);
> 

are these changes required to get it working? As I understand your
changes make the timing harder, which will result in less different NAND
devices will be supported. The timing may be exactly the best for the
currently used one, but maybe some change the device in future to a
slightly slower one.
Maybe I'm wrong so tell me please. But if not then I would like to have
a Tested-by from one who owns this board (Bo?)

Best regards

Andreas Bie?mann

  reply	other threads:[~2012-08-21 10:46 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-08-16  5:05 [U-Boot] [PATCH v2 0/5] at91: 9x5: Enable PMECC(Programmable Multibit ECC controller) support Josh Wu
2012-08-16  5:05 ` [U-Boot] [PATCH v2 1/5] at91: atmel_nand: extract HWECC initialization code into one function: atmel_hw_nand_init_param() Josh Wu
2012-08-16  8:56   ` Andreas Bießmann
2012-08-20 10:13     ` Josh Wu
2012-08-21  1:21     ` Scott Wood
2012-08-16  5:05 ` [U-Boot] [PATCH v2 2/5] at91: atmel_nand: remove unused variables Josh Wu
2012-08-21  1:22   ` Scott Wood
2012-08-16  5:05 ` [U-Boot] [PATCH v2 3/5] at91: atmel_nand: Update driver to support Programmable Multibit ECC controller Josh Wu
2012-08-17  9:24   ` Andreas Bießmann
2012-08-21 10:37     ` Josh Wu
2012-08-21 20:39       ` Scott Wood
2012-08-22  3:26         ` Josh Wu
2012-08-21  1:37   ` Scott Wood
2012-08-16  5:05 ` [U-Boot] [PATCH v2 4/5] at91: 9x5: change SMC config timing that both works for PMECC & non-PMECC Josh Wu
2012-08-21 10:46   ` Andreas Bießmann [this message]
2012-08-22  7:11     ` Josh Wu
2012-08-16  5:05 ` [U-Boot] [PATCH v2 5/5] at91: 9x5: Enable PMECC for 5series ek board Josh Wu

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