From: Josh Wu <josh.wu@atmel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 3/5] at91: atmel_nand: Update driver to support Programmable Multibit ECC controller
Date: Wed, 22 Aug 2012 11:26:50 +0800 [thread overview]
Message-ID: <5034517A.5010009@atmel.com> (raw)
In-Reply-To: <5033F1F9.6050706@freescale.com>
Hi, Scott
On 8/22/2012 4:39 AM, Scott Wood wrote:
> On 08/21/2012 05:37 AM, Josh Wu wrote:
>> Hi, Andreas
>>
>> On 8/17/2012 5:24 PM, Andreas Bie?mann wrote:
>>> can you please add some README entry describing these new config
>>> parameters?
>>> Namely CONFIG_ATMEL_NAND_HW_PMECC, CONFIG_PMECC_CAP,
>>> CONFIG_PMECC_SECTOR_SIZE (can't this be derived from some already
>>> available NAND information?) and CONFIG_PMECC_INDEX_TABLE_OFFSET.
>> OK, I will add a README file to explain all the parameters.
>> this CONFIG_PMECC_SECTOR_SIZE means how many bytes to generate out PMECC
>> code. It only can be 512 and 1024.
>> So for a nand chip whose page size is 2048, if CONFIG_PMECC_SECTOR_SIZE
>> is set as 512, then PMECC will generate PMECC code for each 512 bytes.
>>
>> I think it cannot be derived from nand information.
I think I am not make me clear in previous email. let me try again :)
For the PMECC hardware, it support to read/write one data page of nand
in one step. The size of the data page should be multiple(max is 8) of
PMECC sector. The PMECC sector can only be 512 or 1024.
So the PMECC can read/write max 8192 bytes (max data page size: 8 x
1024) in one step. And generate the ecc bytes (8 x 4) for this page if
the error correct capability is 2 bits.
But the internal thing is those ecc bytes is split into 8 parts and each
part is for corresponding sector.
> So this is basically nand->ecc.size?
I don't think nand->ecc.size is the CONFIG_PMECC_SECTOR_SIZE. Since for
my understanding, the ecc.size is the data bytes per ecc step. In my
code, PMECC can read/write one page in one step.
So I set nand->ecc.size to the page size.
> While this can't be directly read
> from the chip, usually there's a convention for a given type of NAND
> chip on a given controller. Do you really need to support both 512 and
> 1024 for any single chip?
hmm. So maybe I can set default PMECC sector size to 512 if nand flash
page is smaller than 4096 (8x512) bytes. And set it to 1024 only when
nand flash page is larger than 4096.
But in other side, if CONFIG_PMECC_SECTOR_SIZE is defined, then driver
will use it.
>
> Why do you set nand->ecc.size to mtd->writesize if that isn't the actual
> ECC chunk size?
As mentioned in above, the ecc.size is the data bytes per ecc step. In
PMECC code, PMECC can read/write one page in one step.
So I set nand->ecc.size to the page size not the actual inside ECC chunk
size: CONFIG_PMECC_SECTOR_SIZE
> -Scott
>
>
Thanks.
Best Regards,
Josh Wu
next prev parent reply other threads:[~2012-08-22 3:26 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-16 5:05 [U-Boot] [PATCH v2 0/5] at91: 9x5: Enable PMECC(Programmable Multibit ECC controller) support Josh Wu
2012-08-16 5:05 ` [U-Boot] [PATCH v2 1/5] at91: atmel_nand: extract HWECC initialization code into one function: atmel_hw_nand_init_param() Josh Wu
2012-08-16 8:56 ` Andreas Bießmann
2012-08-20 10:13 ` Josh Wu
2012-08-21 1:21 ` Scott Wood
2012-08-16 5:05 ` [U-Boot] [PATCH v2 2/5] at91: atmel_nand: remove unused variables Josh Wu
2012-08-21 1:22 ` Scott Wood
2012-08-16 5:05 ` [U-Boot] [PATCH v2 3/5] at91: atmel_nand: Update driver to support Programmable Multibit ECC controller Josh Wu
2012-08-17 9:24 ` Andreas Bießmann
2012-08-21 10:37 ` Josh Wu
2012-08-21 20:39 ` Scott Wood
2012-08-22 3:26 ` Josh Wu [this message]
2012-08-21 1:37 ` Scott Wood
2012-08-16 5:05 ` [U-Boot] [PATCH v2 4/5] at91: 9x5: change SMC config timing that both works for PMECC & non-PMECC Josh Wu
2012-08-21 10:46 ` Andreas Bießmann
2012-08-22 7:11 ` Josh Wu
2012-08-16 5:05 ` [U-Boot] [PATCH v2 5/5] at91: 9x5: Enable PMECC for 5series ek board Josh Wu
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