[U-Boot] [PATCH v2 4/5] at91: 9x5: change SMC config timing that both works for PMECC & non-PMECC.

[Josh Wu <josh.wu@atmel.com>]

Hi, Andreas

On 8/21/2012 6:46 PM, Andreas Bie?mann wrote:
> Dear Josh Wu,
>
> On 16.08.2012 07:05, Josh Wu wrote:
>> Signed-off-by: Josh Wu <josh.wu@atmel.com>
>> ---
>>   board/atmel/at91sam9x5ek/at91sam9x5ek.c |   12 ++++++------
>>   1 file changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
>> index 17db0fd..8dc24ab 100644
>> --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
>> +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
>> @@ -63,13 +63,13 @@ static void at91sam9x5ek_nand_hw_init(void)
>>   	writel(csa, &matrix->ebicsa);
>>   
>>   	/* Configure SMC CS3 for NAND/SmartMedia */
>> -	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
>> -		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
>> +	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
>> +		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
>>   		&smc->cs[3].setup);
>> -	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
>> -		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
>> +	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
>> +		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
>>   		&smc->cs[3].pulse);
>> -	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
>> +	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
>>   		&smc->cs[3].cycle);
>>   	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
>>   		AT91_SMC_MODE_EXNW_DISABLE |
>> @@ -78,7 +78,7 @@ static void at91sam9x5ek_nand_hw_init(void)
>>   #else /* CONFIG_SYS_NAND_DBW_8 */
>>   		AT91_SMC_MODE_DBW_8 |
>>   #endif
>> -		AT91_SMC_MODE_TDF_CYCLE(3),
>> +		AT91_SMC_MODE_TDF_CYCLE(1),
>>   		&smc->cs[3].mode);
>>   
>>   	writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);
>>
> are these changes required to get it working?

yes. without those change PMECC will not work.

> As I understand your
> changes make the timing harder, which will result in less different NAND
> devices will be supported. The timing may be exactly the best for the
> currently used one, but maybe some change the device in future to a
> slightly slower one.
> Maybe I'm wrong so tell me please. But if not then I would like to have
> a Tested-by from one who owns this board (Bo?)

Currently this timing works for both PMECC & non-PMECC. But I'm not sure 
whether it works for other different chips in future.
So the Tested-by should be needed for this patch. I will cc Bo in the 
next version.

>
> Best regards
>
> Andreas Bie?mann

Best Regards,
Josh Wu