[U-Boot] [PATCH 0/6] SPL: Port SPL framework to powerpc

[U-Boot] [PATCH 0/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

This patchset ports the SPL framework to powerpc. Its based on the
SPL generalization lately done by Tom Rini. The patches can be applied
on top of his 3rd version located here:

http://github.com/trini/u-boot WIP/spl-improvements

Additionally, a new MPC5200 board port is included, the a3m071 board
port. This board port uses this SPL framework mainly to speed up
booting into the OS (Linux of course). Detection of Linux vs. U-Boot
booting is done here by checking the environment variable "boot_os".
If "boot_os" is set to "yes", then the OS (Linux) is booted. Otherwise
the "real" U-Boot is booted. For this env checking in the SPL, a small
restructuring of the env code has been done.

Comments welcome!

Thanks,
Stefan

[U-Boot] [PATCH 1/6] SPL: Add NOR flash booting support

[Stefan Roese]

SPL NOR flash booting support is quite simple. Only copying of the
images is needed.

On MPC5xxx we need to make sure to only use the standard memcpy()
implementation and not the MPC5xxx specific one. As the MPC5xxx
version has some complexity which is not needed for this SPL
booting.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 common/spl/Makefile  |  1 +
 common/spl/spl.c     |  5 ++++
 common/spl/spl_nor.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 include/spl.h        |  3 +++
 4 files changed, 77 insertions(+)
 create mode 100644 common/spl/spl_nor.c

diff --git a/common/spl/Makefile b/common/spl/Makefile
index b61b438..53a82c4 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -15,6 +15,7 @@ LIB	= $(obj)libspl.o
 
 ifdef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
+COBJS-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
 COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
 endif
 
diff --git a/common/spl/spl.c b/common/spl/spl.c
index dcf8556..4c0135e 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -170,6 +170,11 @@ void board_init_r(gd_t *id, ulong dummy)
 		spl_nand_load_image();
 		break;
 #endif
+#ifdef CONFIG_SPL_NOR_SUPPORT
+	case BOOT_DEVICE_NOR:
+		spl_nor_load_image();
+		break;
+#endif
 #ifdef CONFIG_SPL_YMODEM_SUPPORT
 	case BOOT_DEVICE_UART:
 		spl_ymodem_load_image();
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
new file mode 100644
index 0000000..bf0552f
--- /dev/null
+++ b/common/spl/spl_nor.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <spl.h>
+
+/*
+ * Don't use the special MPC5xxx memcpy implementation, only use
+ * the standard one.
+ */
+#if defined(CONFIG_MPC512X) || defined(CONFIG_MPC5200)
+extern void *__memcpy(void *, const void *, size_t);
+#define memcpy		__memcpy
+#endif
+
+void spl_nor_load_image(void)
+{
+	if (spl_start_uboot()) {
+		/*
+		 * Load real U-Boot from its location in NOR flash to its
+		 * defined location in SDRAM
+		 */
+		memcpy((void *)CONFIG_SYS_TEXT_BASE,
+		       (void *)CONFIG_SYS_UBOOT_BASE,
+		       CONFIG_SYS_MONITOR_LEN);
+
+		/*
+		 * This parsing is needed for the SPL framework to correctly
+		 * detect and boot the U-Boot image
+		 */
+		spl_parse_image_header(
+			(const struct image_header *)CONFIG_SYS_TEXT_BASE);
+	} else {
+		/*
+		 * Load Linux from its location in NOR flash to its defined
+		 * location in SDRAM
+		 */
+		spl_parse_image_header(
+			(const struct image_header *)CONFIG_SYS_OS_BASE);
+
+		memcpy((void *)spl_image.load_addr,
+		       (void *)(CONFIG_SYS_OS_BASE +
+				sizeof(struct image_header)),
+		       spl_image.size);
+
+		/*
+		 * Copy DT blob (fdt) to SDRAM. Passing pointer to flash
+		 * doesn't work (16 KiB should be enough for DT)
+		 */
+		memcpy((void *)CONFIG_SYS_SPL_ARGS_ADDR,
+		       (void *)(CONFIG_SYS_FDT_BASE),
+		       (16 << 10));
+	}
+}
diff --git a/include/spl.h b/include/spl.h
index 3b3051f..efa160e 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -55,6 +55,9 @@ void spl_display_print(void);
 /* NAND SPL functions */
 void spl_nand_load_image(void);
 
+/* NOR SPL functions */
+void spl_nor_load_image(void);
+
 /* MMC SPL functions */
 void spl_mmc_load_image(void);
 
-- 
1.7.12

[U-Boot] [PATCH 2/6] powerpc: Extract EPAPR_MAGIC constants into processor.h

[Stefan Roese]

By extracting these defines into a header, they can be re-used by other
C sources as well. This will be done by the SPL framework OS boot
support.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 arch/powerpc/include/asm/processor.h | 6 ++++++
 arch/powerpc/lib/bootm.c             | 6 ------
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index dc009d6..daa670b 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1329,4 +1329,10 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 #endif
 #endif /* CONFIG_MACH_SPECIFIC */
 
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
+ #define EPAPR_MAGIC	(0x45504150)
+#else
+ #define EPAPR_MAGIC	(0x65504150)
+#endif
+
 #endif /* __ASM_PPC_PROCESSOR_H */
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 0c54c72..09bb7e6 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -87,12 +87,6 @@ static void boot_jump_linux(bootm_headers_t *images)
 		 *   r8: 0
 		 *   r9: 0
 		 */
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
- #define EPAPR_MAGIC	(0x45504150)
-#else
- #define EPAPR_MAGIC	(0x65504150)
-#endif
-
 		debug ("   Booting using OF flat tree...\n");
 		WATCHDOG_RESET ();
 		(*kernel) ((bd_t *)of_flat_tree, 0, 0, EPAPR_MAGIC,
-- 
1.7.12

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

This patch enables the SPL framework to be used on powerpc platforms
and not only ARM.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 common/spl/spl.c | 45 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 42 insertions(+), 3 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 4c0135e..7a8f2a8 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -25,7 +25,6 @@
 #include <common.h>
 #include <spl.h>
 #include <asm/u-boot.h>
-#include <asm/utils.h>
 #include <nand.h>
 #include <fat.h>
 #include <version.h>
@@ -36,11 +35,17 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_SYS_UBOOT_START
+#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
+#endif
+
 u32 *boot_params_ptr = NULL;
 struct spl_image_info spl_image;
 
+#ifdef CONFIG_ARM
 /* Define global data structure pointer to it*/
 gd_t gdata __attribute__ ((section(".data")));
+#endif
 static bd_t bdata __attribute__ ((section(".data")));
 
 inline void hang(void)
@@ -50,6 +55,7 @@ inline void hang(void)
 		;
 }
 
+#ifdef CONFIG_ARM
 void __weak board_init_f(ulong dummy)
 {
 	/*
@@ -61,6 +67,17 @@ void __weak board_init_f(ulong dummy)
 	debug(">>board_init_f()\n");
 	relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
 }
+#endif
+
+/*
+ * Weak default function for board specific cleanup/preparation before
+ * Linux boot. Some boards/platforms might now need it, so just provide
+ * an empty stub here.
+ */
+__weak void spl_board_prepare_for_linux(void)
+{
+	/* Nothing to do! */
+}
 
 /*
  * Default function to determine if u-boot or the OS should
@@ -89,7 +106,11 @@ void spl_parse_image_header(const struct image_header *header)
 		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
 		spl_image.entry_point = __be32_to_cpu(header->ih_load);
 		/* Load including the header */
+#ifdef CONFIG_ARM
 		spl_image.load_addr = spl_image.entry_point - header_size;
+#else
+		spl_image.load_addr = __be32_to_cpu(header->ih_load);
+#endif
 		spl_image.os = header->ih_os;
 		spl_image.name = (const char *)&header->ih_name;
 		debug("spl: payload image: %s load addr: 0x%x size: %d\n",
@@ -101,7 +122,7 @@ void spl_parse_image_header(const struct image_header *header)
 			header->ih_magic);
 		/* Let's assume U-Boot will not be more than 200 KB */
 		spl_image.size = 200 * 1024;
-		spl_image.entry_point = CONFIG_SYS_TEXT_BASE;
+		spl_image.entry_point = CONFIG_SYS_UBOOT_START;
 		spl_image.load_addr = CONFIG_SYS_TEXT_BASE;
 		spl_image.os = IH_OS_U_BOOT;
 		spl_image.name = "U-Boot";
@@ -114,6 +135,7 @@ void spl_parse_image_header(const struct image_header *header)
  * arg: Pointer to paramter image in RAM
  */
 #ifdef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_ARM
 static void __noreturn jump_to_image_linux(void *arg)
 {
 	debug("Entering kernel arg pointer: 0x%p\n", arg);
@@ -124,7 +146,22 @@ static void __noreturn jump_to_image_linux(void *arg)
 	cleanup_before_linux();
 	image_entry(0, CONFIG_MACH_TYPE, arg);
 }
-#endif
+#endif /* CONFIG_ARM */
+
+#ifdef CONFIG_PPC
+static void __noreturn jump_to_image_linux(void *arg)
+{
+	debug("Entering kernel arg pointer: 0x%p\n", arg);
+	typedef void (*image_entry_arg_t)(void *, ulong r4, ulong r5, ulong r6,
+					  ulong r7, ulong r8, ulong r9)
+		__attribute__ ((noreturn));
+	image_entry_arg_t image_entry =
+		(image_entry_arg_t)spl_image.entry_point;
+
+	image_entry(arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, 0, 0);
+}
+#endif /* CONFIG_PPC */
+#endif /* CONFIG_SPL_OS_BOOT */
 
 static void __noreturn jump_to_image_no_args(void)
 {
@@ -213,7 +250,9 @@ void board_init_r(gd_t *id, ulong dummy)
 /* This requires UART clocks to be enabled */
 void preloader_console_init(void)
 {
+#ifdef CONFIG_ARM
 	gd = &gdata;
+#endif
 	gd->bd = &bdata;
 	gd->flags |= GD_FLG_RELOC;
 	gd->baudrate = CONFIG_BAUDRATE;
-- 
1.7.12

[U-Boot] [PATCH 4/6] env: Extract getenv_f() into separate source file

[Stefan Roese]

By extracting getenv_f and envmatch() from cmd_nvedit.c into a
separate file, getenv_f() can be included easily into the SPL
binary. With this, SPL boards can now use getenv_f() to read
environment variables (e.g. to detect if the OS or U-Boot shall
be executed).

In the approach this is done for env stored in NOR flash, as this
will be used by an upcoming MPC5200 board port.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 common/Makefile       |  4 +++
 common/cmd_nvedit.c   | 58 ------------------------------------
 common/env_getenv_f.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 86 insertions(+), 58 deletions(-)
 create mode 100644 common/env_getenv_f.c

diff --git a/common/Makefile b/common/Makefile
index 3d62775..2cd539a 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -50,6 +50,7 @@ XCOBJS-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o
 COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o
 XCOBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o
 COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o
+COBJS-y += env_getenv_f.o
 COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
 COBJS-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
@@ -187,6 +188,9 @@ COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
 endif
 
 ifdef CONFIG_SPL_BUILD
+COBJS-y += env_common.o
+COBJS-y += env_getenv_f.o
+COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
 endif
 COBJS-y += console.o
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index fd05e72..f766fd5 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -520,44 +520,6 @@ char *getenv(const char *name)
 	return NULL;
 }
 
-/*
- * Look up variable from environment for restricted C runtime env.
- */
-int getenv_f(const char *name, char *buf, unsigned len)
-{
-	int i, nxt;
-
-	for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
-		int val, n;
-
-		for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) {
-			if (nxt >= CONFIG_ENV_SIZE)
-				return -1;
-		}
-
-		val = envmatch((uchar *)name, i);
-		if (val < 0)
-			continue;
-
-		/* found; copy out */
-		for (n = 0; n < len; ++n, ++buf) {
-			*buf = env_get_char(val++);
-			if (*buf == '\0')
-				return n;
-		}
-
-		if (n)
-			*--buf = '\0';
-
-		printf("env_buf [%d bytes] too small for value of \"%s\"\n",
-			len, name);
-
-		return n;
-	}
-
-	return -1;
-}
-
 /**
  * Decode the integer value of an environment variable and return it.
  *
@@ -593,26 +555,6 @@ U_BOOT_CMD(
 );
 #endif
 
-
-/*
- * Match a name / name=value pair
- *
- * s1 is either a simple 'name', or a 'name=value' pair.
- * i2 is the environment index for a 'name2=value2' pair.
- * If the names match, return the index for the value2, else -1.
- */
-int envmatch(uchar *s1, int i2)
-{
-	while (*s1 == env_get_char(i2++))
-		if (*s1++ == '=')
-			return i2;
-
-	if (*s1 == '\0' && env_get_char(i2-1) == '=')
-		return i2;
-
-	return -1;
-}
-
 static int do_env_default(cmd_tbl_t *cmdtp, int flag,
 			  int argc, char * const argv[])
 {
diff --git a/common/env_getenv_f.c b/common/env_getenv_f.c
new file mode 100644
index 0000000..7dfbfe0
--- /dev/null
+++ b/common/env_getenv_f.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <environment.h>
+
+/*
+ * Match a name / name=value pair
+ *
+ * s1 is either a simple 'name', or a 'name=value' pair.
+ * i2 is the environment index for a 'name2=value2' pair.
+ * If the names match, return the index for the value2, else -1.
+ */
+int envmatch(uchar *s1, int i2)
+{
+	while (*s1 == env_get_char(i2++))
+		if (*s1++ == '=')
+			return i2;
+
+	if (*s1 == '\0' && env_get_char(i2-1) == '=')
+		return i2;
+
+	return -1;
+}
+
+/*
+ * Look up variable from environment for restricted C runtime env.
+ */
+int getenv_f(const char *name, char *buf, unsigned len)
+{
+	int i, nxt;
+
+	for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
+		int val, n;
+
+		for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) {
+			if (nxt >= CONFIG_ENV_SIZE)
+				return -1;
+		}
+
+		val = envmatch((uchar *)name, i);
+		if (val < 0)
+			continue;
+
+		/* found; copy out */
+		for (n = 0; n < len; ++n, ++buf) {
+			*buf = env_get_char(val++);
+			if (*buf == '\0')
+				return n;
+		}
+
+		if (n)
+			*--buf = '\0';
+
+		printf("env_buf [%d bytes] too small for value of \"%s\"\n",
+			len, name);
+
+		return n;
+	}
+
+	return -1;
+}
-- 
1.7.12

[U-Boot] [PATCH 5/6] mpc5200: Add SPL support

[Stefan Roese]

This patch adds SPL booting support (NOR flash) for the
MPC5200 platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 arch/powerpc/cpu/mpc5xxx/Makefile       |  4 +++
 arch/powerpc/cpu/mpc5xxx/spl_boot.c     | 62 +++++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc5xxx/start.S        | 22 ++++++++++++
 arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds | 53 ++++++++++++++++++++++++++++
 arch/powerpc/include/asm/spl.h          | 28 +++++++++++++++
 arch/powerpc/lib/Makefile               |  4 +++
 6 files changed, 173 insertions(+)
 create mode 100644 arch/powerpc/cpu/mpc5xxx/spl_boot.c
 create mode 100644 arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds
 create mode 100644 arch/powerpc/include/asm/spl.h

diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile
index 1a088b7..8de2c13 100644
--- a/arch/powerpc/cpu/mpc5xxx/Makefile
+++ b/arch/powerpc/cpu/mpc5xxx/Makefile
@@ -41,6 +41,10 @@ COBJS-y += speed.o
 COBJS-$(CONFIG_CMD_USB) += usb_ohci.o
 COBJS-$(CONFIG_CMD_USB) += usb.o
 
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl_boot.o
+endif
+
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
 START	:= $(addprefix $(obj),$(SSTART) $(CSTART))
diff --git a/arch/powerpc/cpu/mpc5xxx/spl_boot.c b/arch/powerpc/cpu/mpc5xxx/spl_boot.c
new file mode 100644
index 0000000..177b323
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/spl_boot.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <spl.h>
+
+extern char __bss_start[], __bss_end__[];
+
+/*
+ * Return selected boot device. On MPC5200 its only NOR flash right now.
+ */
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NOR;
+}
+
+/*
+ * SPL version of board_init_f()
+ */
+void board_init_f(ulong bootflag)
+{
+	/*
+	 * First we need to initialize the SDRAM, so that the real
+	 * U-Boot or the OS (Linux) can be loaded
+	 */
+	initdram(0);
+
+	/* Clear bss */
+	memset(__bss_start, '\0', __bss_end__ - __bss_start);
+
+	/*
+	 * get_clocks() needs to be called so that the serial driver
+	 * works correctly
+	 */
+	get_clocks();
+
+	/*
+	 * Do rudimental console / serial setup
+	 */
+	preloader_console_init();
+
+	/*
+	 * Call board_init_r() (SPL framework version) to load and boot
+	 * real U-Boot or OS
+	 */
+	board_init_r(NULL, 0);
+	/* Does not return!!! */
+}
diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
index 51cc4e2..ad5bc0a 100644
--- a/arch/powerpc/cpu/mpc5xxx/start.S
+++ b/arch/powerpc/cpu/mpc5xxx/start.S
@@ -50,6 +50,7 @@
 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Set up GOT: Global Offset Table
  *
@@ -68,6 +69,7 @@
 	GOT_ENTRY(__bss_end__)
 	GOT_ENTRY(__bss_start)
 	END_GOT
+#endif
 
 /*
  * Version string
@@ -84,6 +86,18 @@ version_string:
 	. = EXC_OFF_SYS_RESET
 	.globl	_start
 _start:
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	/*
+	 * This is the entry of the real U-Boot from a board port
+	 * that supports SPL booting on the MPC5200. We only need
+	 * to call board_init_f() here. Everything else has already
+	 * been done in the SPL u-boot version.
+	 */
+	GET_GOT			/* initialize GOT access		*/
+	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
+	/* NOTREACHED - board_init_f() does not return */
+#else
 	mfmsr	r5			/* save msr contents		*/
 
 	/* Move CSBoot and adjust instruction pointer                   */
@@ -152,7 +166,9 @@ lowboot_reentry:
 	/* Be careful to keep code relocatable !			*/
 	/*--------------------------------------------------------------*/
 
+#ifndef CONFIG_SPL_BUILD
 	GET_GOT			/* initialize GOT access		*/
+#endif
 
 	/* r3: IMMR */
 	bl	cpu_init_f	/* run low-level CPU init code (in Flash)*/
@@ -160,7 +176,9 @@ lowboot_reentry:
 	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
 
 	/* NOTREACHED - board_init_f() does not return */
+#endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Vector Table
  */
@@ -333,6 +351,7 @@ int_return:
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfi
+#endif /* CONFIG_SPL_BUILD */
 
 /*
  * This code initialises the MPC5xxx processor core
@@ -522,6 +541,7 @@ get_pvr:
 	mfspr	r3, PVR
 	blr
 
+#ifndef CONFIG_SPL_BUILD
 /*------------------------------------------------------------------------------*/
 
 /*
@@ -759,3 +779,5 @@ trap_init:
 
 	mtlr	r4			/* restore link register    */
 	blr
+
+#endif /* CONFIG_SPL_BUILD */
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds
new file mode 100644
index 0000000..2e50f02
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2012 Stefan Roese <sr@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY
+{
+	sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE
+	flash : ORIGIN = CONFIG_SPL_TEXT_BASE,
+		LENGTH = CONFIG_SYS_SPL_LEN
+}
+
+OUTPUT_ARCH(powerpc)
+ENTRY(_start)
+SECTIONS
+{
+	.text :
+	{
+		__start = .;
+		arch/powerpc/cpu/mpc5xxx/start.o	(.text)
+		*(.text*)
+	} > flash
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } > flash
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } > flash
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > sdram
+}
diff --git a/arch/powerpc/include/asm/spl.h b/arch/powerpc/include/asm/spl.h
new file mode 100644
index 0000000..fd69253
--- /dev/null
+++ b/arch/powerpc/include/asm/spl.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_NOR		1
+
+#endif
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index cdd62a2..6e6688d 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -44,7 +44,9 @@ SOBJS-y	+= ticks.o
 SOBJS-y	+= reloc.o
 
 COBJS-$(CONFIG_BAT_RW) += bat_rw.o
+ifndef CONFIG_SPL_BUILD
 COBJS-y	+= board.o
+endif
 COBJS-y	+= bootm.o
 COBJS-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount.o
 COBJS-y	+= cache.o
@@ -75,12 +77,14 @@ TARGETS += $(LIB)
 all: $(TARGETS)
 
 $(LIB):	$(obj).depend $(OBJS)
+ifndef CONFIG_SPL_BUILD
 	@if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\
 	then \
 		echo "ERROR: Your compiler doesn't generate .fixup sections!";\
 		echo "       Upgrade to a recent toolchain."; \
 		exit 1; \
 	fi;
+endif
 	$(call cmd_link_o_target, $(OBJS))
 
 $(LIBGCC): $(obj).depend $(LGOBJS)
-- 
1.7.12

[U-Boot] [PATCH 6/6] mpc5200: Add a3m071 board support

[Stefan Roese]

This patch adds support for the a3m071 board based on the
MPC5200.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 MAINTAINERS                  |   2 +
 board/a3m071/Makefile        |  36 ++++
 board/a3m071/a3m071.c        | 335 +++++++++++++++++++++++++++++++++++++
 board/a3m071/mt46v16m16-75.h |  32 ++++
 boards.cfg                   |   1 +
 include/configs/a3m071.h     | 384 +++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 790 insertions(+)
 create mode 100644 board/a3m071/Makefile
 create mode 100644 board/a3m071/a3m071.c
 create mode 100644 board/a3m071/mt46v16m16-75.h
 create mode 100644 include/configs/a3m071.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c5a6f2f..d848ffc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -390,6 +390,8 @@ Ricardo Ribalda <ricardo.ribalda@uam.es>
 
 Stefan Roese <sr@denx.de>
 
+	a3m071		MPC5200
+
 	P3M7448		MPC7448
 
 	uc100		MPC857
diff --git a/board/a3m071/Makefile b/board/a3m071/Makefile
new file mode 100644
index 0000000..6f961fb
--- /dev/null
+++ b/board/a3m071/Makefile
@@ -0,0 +1,36 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
new file mode 100644
index 0000000..89ced82
--- /dev/null
+++ b/board/a3m071/a3m071.c
@@ -0,0 +1,335 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
+ *
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * Copyright 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <miiphy.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#include "mt46v16m16-75.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_SYS_RAMBOOT) && \
+	(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+	long control = SDRAM_CONTROL | hi_addr_bit;
+
+	/* unlock mode register */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+
+#ifdef SDRAM_DDR
+	/* set mode register: extended mode */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+
+	/* set mode register: reset DLL */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+#endif
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+
+	/* auto refresh */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+
+	/* set mode register */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+phys_size_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+#if !defined(CONFIG_SYS_RAMBOOT) && \
+	(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);	/* 2GB at 0x0 */
+	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);	/* disabled */
+
+	/* setup config registers */
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+#ifdef SDRAM_DDR
+	/* set tap delay */
+	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+			 0x13 + __builtin_ffs(dramsize >> 20) - 1);
+	} else {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0);	/* disabled */
+	}
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
+	if (dramsize2 >= 0x13)
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	else
+		dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
+		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+
+	return dramsize + dramsize2;
+}
+
+static void get_revisions(int *failsavelevel, int *digiboardversion,
+	int *fpgaversion)
+{
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+	u8 val;
+
+	/*
+	 * Figure out failsavelevel
+	 * see ticket dsvk#59
+	 */
+	*failsavelevel = 0;	/* 0=failsave, 1=board ok, 2=fpga ok */
+
+	/* read digitalboard-version from TMR[2..4] */
+	val = 0;
+	val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
+	val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
+	val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
+	*digiboardversion = val;
+
+	if (*digiboardversion == 0) {
+		*failsavelevel = 1;	/* digiboard-version ok */
+
+		/* read fpga-version from TMR[5..7] */
+		val = 0;
+		val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
+		val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
+		val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
+		*fpgaversion = val;
+
+		if (*fpgaversion == 1)
+			*failsavelevel = 2;	/* fpga-version ok */
+	}
+}
+
+/*
+ * This function is called from the SPL U-Boot version for
+ * early init stuff, that needs to be done for OS (e.g. Linux)
+ * booting. Doing it later in the real U-Boot would not work
+ * in case that the SPL U-Boot boots Linux directly.
+ */
+void spl_board_init(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+	int digiboardversion;
+	int failsavelevel;
+	int fpgaversion;
+	u32 val;
+
+	get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
+
+	val = in_be32(&mm->ipbi_ws_ctrl);
+
+	/* first clear bits 19..21 (CS3...5) */
+	val &= ~((1 << 19) | (1 << 20) | (1 << 21));
+	if (failsavelevel == 2) {
+		/* FPGA ok */
+		val |= (1 << 19) | (1 << 21);
+	}
+
+	if (failsavelevel >= 1) {
+		/* at least digiboard-version ok */
+		val |= (1 << 20);
+	}
+
+	/* And write new value back to register */
+	out_be32(&mm->ipbi_ws_ctrl, val);
+
+	/*
+	 * No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG)
+	 * as all 3 config versions (failsave level) have the same setup.
+	 */
+
+	/*
+	 * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
+	 * ticket #60
+	 *
+	 * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
+	 * set bit 0(msb) to 1
+	 */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, 1 << (31 - 0));
+
+	/* setup GPIOs for status-leds if needed - see ticket #57 */
+	if (failsavelevel > 0) {
+		/* digiboard-version is OK */
+		/* LED is LOW ACTIVE - so deactivate by set output to 1 */
+		gpio->simple_dvo |= 1 << (31 - 12);
+		gpio->simple_dvo |= 1 << (31 - 13);
+		/* set GPIO direction to output */
+		gpio->simple_ddr |= 1 << (31 - 12);
+		gpio->simple_ddr |= 1 << (31 - 13);
+		/* open drain config is set to "normal output"@reset */
+		/* gpio->simple_ode &=~ ( 1 << (31-12) ); */
+		/* gpio->simple_ode &=~ ( 1 << (31-13) ); */
+		/* enable as GPIO */
+		gpio->simple_gpioe |= 1 << (31 - 12);
+		gpio->simple_gpioe |= 1 << (31 - 13);
+	}
+
+	/* setup fpga irq - see ticket #65 */
+	if (failsavelevel > 1) {
+		/*
+		 * The main irq initialisation is done in interrupts.c
+		 * mpc5xxx_init_irq
+		 */
+		struct mpc5xxx_intr *intr =
+		    (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
+
+		setbits_be32(&intr->ctrl, 0x08C01801);
+
+		/*
+		 * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
+		 * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
+		 */
+	}
+
+}
+
+int checkboard(void)
+{
+	int digiboardversion;
+	int failsavelevel;
+	int fpgaversion;
+
+	get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
+
+	puts("Board: A3M071\n");
+	printf("Rev:   failsave level       %u\n", failsavelevel);
+	printf("       digiboard IO version %u\n", digiboardversion);
+	if (failsavelevel > 0)	/* only if fpga-version red */
+		printf("       fpga IO version      %u\n", fpgaversion);
+
+	return 0;
+}
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+	/* adjust flash start and offset to detected values */
+	gd->bd->bi_flashstart = flash_info[0].start[0];
+	gd->bd->bi_flashoffset = 0;
+
+	/* adjust mapping */
+	out_be32((void *)MPC5XXX_BOOTCS_START,
+		 START_REG(gd->bd->bi_flashstart));
+	out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
+	out_be32((void *)MPC5XXX_BOOTCS_STOP,
+		 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
+	out_be32((void *)MPC5XXX_CS0_STOP,
+		 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t * bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * A3M071 specific implementation of spl_start_uboot()
+ *
+ * RETURN
+ * 0 if booting into OS is selected (default)
+ * 1 if booting into U-Boot is selected
+ */
+int spl_start_uboot(void)
+{
+	char s[8];
+
+	env_init();
+	getenv_f("boot_os", s, sizeof(s));
+	if ((s != NULL) && (strcmp(s, "yes") == 0))
+		return 0;
+
+	return 1;
+}
+#endif
diff --git a/board/a3m071/mt46v16m16-75.h b/board/a3m071/mt46v16m16-75.h
new file mode 100644
index 0000000..e49e996
--- /dev/null
+++ b/board/a3m071/mt46v16m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define SDRAM_DDR		/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x704f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..cbe9c27 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -431,6 +431,7 @@ mpc5121ads                   powerpc     mpc512x     mpc5121ads          freesca
 mpc5121ads_rev2              powerpc     mpc512x     mpc5121ads          freescale      -           mpc5121ads:MPC5121ADS_REV2
 cmi_mpc5xx                   powerpc     mpc5xx      cmi
 PATI                         powerpc     mpc5xx      pati                mpl
+a3m071                       powerpc     mpc5xxx     a3m071
 a4m072                       powerpc     mpc5xxx     a4m072
 BC3450                       powerpc     mpc5xxx     bc3450
 canmb                        powerpc     mpc5xxx
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
new file mode 100644
index 0000000..9cb457d
--- /dev/null
+++ b/include/configs/a3m071.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_A3M071			/* ... on A3M071 board */
+#define CONFIG_MPC5200_DDR		/* ... use DDR RAM	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x01000000	/* boot low for 32 MiB boards */
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_LOWBOOT		/* Enable lowboot	*/
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	    /* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE		\
+	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SPL
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+/* define for 66MHz speed - undef for 33MHz PCI clock speed */
+#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,5200 at 0"
+#define OF_SOC			"soc5200 at f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc5200 at f0000000/serial at 2000"
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C				/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x40000)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR			0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
+#define	CONFIG_SYS_SRAM_BASE		0xF1000000
+#define	CONFIG_SYS_SRAM_SIZE		0x200000
+#define	CONFIG_SYS_LIME_BASE		0xE4000000
+#define	CONFIG_SYS_LIME_SIZE		0x04000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
+
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR			0x00
+
+/*
+ * GPIO configuration
+ */
+
+/*
+ * GPIO-config depends on failsave-level
+ * failsave 0 means just MPX-config, no digiboard, no fpga
+ *          1 means digiboard ok
+ *          2 means fpga ok
+ */
+
+/* for failsave-level 0 - full failsave */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x1005C005
+/* for failsave-level 1 - only digiboard ok */
+#define CONFIG_SYS_GPS_PORT_CONFIG_1	0x1005C005
+/* for failsave-level 2 - all ok */
+#define CONFIG_SYS_GPS_PORT_CONFIG_2	0x1005C005
+
+/*
+ * Configuration matrix
+ *                        MSB                          LSB
+ * failsave 0  0x1005C005  00010000000001011100000000000101  ( full failsave )
+ * failsave 1  0x1005C005  00010000000001011100000000000101  ( digib.-ver ok )
+ * failsave 2  0x1005C005  00010000000001011100000000000101  ( all ok )
+ *                         || ||| ||  |   ||| |   |   |   |
+ *                         || ||| ||  |   ||| |   |   |   |  bit rev name
+ *                         ++-+++-++--+---+++-+---+---+---+-  0   31 CS1
+ *                          +-+++-++--+---+++-+---+---+---+-  1   30 LPTZ
+ *                            ||| ||  |   ||| |   |   |   |   2   29 ALTs
+ *                            +++-++--+---+++-+---+---+---+-  3   28 ALTs
+ *                             ++-++--+---+++-+---+---+---+-  4   27 CS7
+ *                              +-++--+---+++-+---+---+---+-  5   26 CS6
+ *                                ||  |   ||| |   |   |   |   6   25 ATA
+ *                                ++--+---+++-+---+---+---+-  7   24 ATA
+ *                                 +--+---+++-+---+---+---+-  8   23 IR_USB_CLK
+ *                                    |   ||| |   |   |   |   9   22 IRDA
+ *                                    |   ||| |   |   |   |  10   21 IRDA
+ *                                    +---+++-+---+---+---+- 11   20 IRDA
+ *                                        ||| |   |   |   |  12   19 Ether
+ *                                        ||| |   |   |   |  13   18 Ether
+ *                                        ||| |   |   |   |  14   17 Ether
+ *                                        +++-+---+---+---+- 15   16 Ether
+ *                                         ++-+---+---+---+- 16   15 PCI_DIS
+ *                                          +-+---+---+---+- 17   14 USB_SE
+ *                                            |   |   |   |  18   13 USB
+ *                                            +---+---+---+- 19   12 USB
+ *                                                |   |   |  20   11 PSC3
+ *                                                |   |   |  21   10 PSC3
+ *                                                |   |   |  22    9 PSC3
+ *                                                +---+---+- 23    8 PSC3
+ *                                                    |   |  24    7 -
+ *                                                    |   |  25    6 PSC2
+ *                                                    |   |  26    5 PSC2
+ *                                                    +---+- 27    4 PSC2
+ *                                                        |  28    3 -
+ *                                                        |  29    2 PSC1
+ *                                                        |  30    1 PSC1
+ *                                                        +- 31    0 PSC1
+ */
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+
+#define CONFIG_CMDLINE_EDITING
+#define	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024
+#else
+#define CONFIG_SYS_CBSIZE		256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000
+#define CONFIG_SYS_MEMTEST_END		0x00f00000
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_LOOPW
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup*/
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_CS2_START		0xe0000000
+#define CONFIG_SYS_CS2_SIZE		0x00100000
+
+/* FPGA slave io (512kiB) - see ticket #66 */
+#define CONFIG_SYS_CS3_START		0xE9000000
+#define CONFIG_SYS_CS3_SIZE		0x00080000
+/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
+#define CONFIG_SYS_CS3_CFG		0x0032B900
+
+/* Diagnosis Interface - see ticket #63 */
+#define CONFIG_SYS_CS4_START		0xEA000000
+#define CONFIG_SYS_CS4_SIZE		0x00000001
+/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0002B900 */
+#define CONFIG_SYS_CS4_CFG		0x0002B900
+
+/* FPGA master io (64kiB) - see ticket #66 */
+#define CONFIG_SYS_CS5_START		0xE8000000
+#define CONFIG_SYS_CS5_SIZE		0x00010000
+/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
+#define CONFIG_SYS_CS5_CFG		0x0032B900
+
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* for pci_clk  = 66 MHz */
+#define CONFIG_SYS_BOOTCS_CFG		0x0006F900
+#define CONFIG_SYS_CS1_CFG		0x0004FB00
+#define CONFIG_SYS_CS2_CFG		0x0006F90C
+#else	/* for pci_clk = 33 MHz */
+#define CONFIG_SYS_BOOTCS_CFG		0x0002F900
+#define CONFIG_SYS_CS1_CFG		0x0001FB00
+#define CONFIG_SYS_CS2_CFG		0x0002F90C
+#endif
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
+/* R  7  R  6  R  5  R  4  R  3  R  2  R  1  R  0  */
+/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
+#define CONFIG_SYS_CS_DEADCYCLE		0x33030000
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_BOOTDELAY	0	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
+	"echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_SYS_OS_BASE	0xfc080000
+#define CONFIG_SYS_FDT_BASE	0xfc060000
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"verify=no\0"							\
+	"consoledev=ttyPSC0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0"\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=${consoledev},${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdtaddr}\0"			\
+	"flash_mtd=run mtdargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdtaddr}\0"			\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0"	\
+	"net_nfs=sleep 2; tftp ${loadaddr} ${bootfile}; tftp c00000 ${fdtfile};"\
+		"run nfsargs addip addtty;"				\
+		"bootm ${loadaddr} - c00000\0"				\
+	"load=tftp ${loadaddr} u-boot.bin\0"				\
+	"update=protect off fc000000 fc03ffff; "			\
+		"era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0"\
+	"upd=run load;run update\0"					\
+	"fdtaddr=" xstr(CONFIG_SYS_FDT_BASE) "\0"			\
+	"fdtfile=dtbFile\0"						\
+	"kernel_addr=" xstr(CONFIG_SYS_OS_BASE) "\0"			\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_mtd"
+
+/*
+ * SPL related defines
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NOR_SUPPORT
+#define CONFIG_SPL_TEXT_BASE	0xfc000000
+#define	CONFIG_SPL_START_S_PATH	"arch/powerpc/cpu/mpc5xxx"
+#define CONFIG_SPL_LDSCRIPT	"arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* image.c */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT	/* string.c */
+
+/* Place BSS for SPL near end of SDRAM */
+#define CONFIG_SPL_BSS_START_ADDR	((128 - 1) << 20)
+#define CONFIG_SPL_BSS_MAX_SIZE		(64 << 10)
+
+#define CONFIG_SPL_OS_BOOT
+/* Place patched DT blob (fdt)@this address */
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x01800000
+
+#define CONFIG_SYS_SPL_LEN		32768
+#define CONFIG_SYS_PAD_TO		0xfc008000
+
+/* Settings for real U-Boot to be loaded from NOR flash */
+#define CONFIG_SYS_UBOOT_BASE		(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_SYS_SPL_LEN)
+#define CONFIG_SYS_UBOOT_START		(CONFIG_SYS_TEXT_BASE + 0x100)
+
+#endif /* __CONFIG_H */
-- 
1.7.12

[U-Boot] [PATCH 1/6] SPL: Add NOR flash booting support

[Tom Rini]

On 08/23/2012 01:12 AM, Stefan Roese wrote:
> SPL NOR flash booting support is quite simple. Only copying of the
> images is needed.
> 
> On MPC5xxx we need to make sure to only use the standard memcpy()
> implementation and not the MPC5xxx specific one. As the MPC5xxx
> version has some complexity which is not needed for this SPL
> booting.

I assume there's good reason to use SPL on NOR here?  Is a near-future
goal to do SPL-boots-Linux and thus the desire for a very small loader?
 Thanks!

-- 
Tom

[U-Boot] [PATCH 1/6] SPL: Add NOR flash booting support

[Stefan Roese]

On 08/23/2012 05:07 PM, Tom Rini wrote:
> On 08/23/2012 01:12 AM, Stefan Roese wrote:
>> SPL NOR flash booting support is quite simple. Only copying of the
>> images is needed.
>>
>> On MPC5xxx we need to make sure to only use the standard memcpy()
>> implementation and not the MPC5xxx specific one. As the MPC5xxx
>> version has some complexity which is not needed for this SPL
>> booting.
> 
> I assume there's good reason to use SPL on NOR here?  Is a near-future
> goal to do SPL-boots-Linux and thus the desire for a very small loader?

Yes. As explained in the cover-letter, the board port using this SPL NOR
support (MPC5200 based) mainly uses this SPL framework to speed up
booting into Linux. Less code loaded from NOR, zero relocation (on this
PPC port at least), etc.

My first quick tests show a boot to Linux speedup by approx. 0.5 seconds
compared to the good-old U-Boot -> Linux booting. So it definitely makes
sense in time-critical bootup situation.

Thanks,
Stefan

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Tom Rini]

On 08/23/2012 01:12 AM, Stefan Roese wrote:

> This patch enables the SPL framework to be used on powerpc platforms
> and not only ARM.
[snip]
> +#ifdef CONFIG_ARM
>  /* Define global data structure pointer to it*/
>  gd_t gdata __attribute__ ((section(".data")));
> +#endif

So you handle cleaning up the BSS differently, interesting.  I'm going
to see if that would work for ARM too..

[snip]
> @@ -89,7 +106,11 @@ void spl_parse_image_header(const struct image_header *header)
>  		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
>  		spl_image.entry_point = __be32_to_cpu(header->ih_load);
>  		/* Load including the header */
> +#ifdef CONFIG_ARM
>  		spl_image.load_addr = spl_image.entry_point - header_size;
> +#else
> +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
> +#endif

This isn't an ARM-ism but is instead because spl_nor.c isn't offsetting
where the header is like mmc/nand/ymodem do, yes?  Would it be possible
to make spl_nor.c behave like the others?  One of the reasons I ask is
I'm looking at a NOR chip on my desk...

-- 
Tom

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

On 08/23/2012 07:10 PM, Tom Rini wrote:
>> +#ifdef CONFIG_ARM
>>  /* Define global data structure pointer to it*/
>>  gd_t gdata __attribute__ ((section(".data")));
>> +#endif
> 
> So you handle cleaning up the BSS differently, interesting.  I'm going
> to see if that would work for ARM too..

Yes. Might be that I missed something though. I'll re-check tomorrow.

> [snip]
>> @@ -89,7 +106,11 @@ void spl_parse_image_header(const struct image_header *header)
>>  		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
>>  		spl_image.entry_point = __be32_to_cpu(header->ih_load);
>>  		/* Load including the header */
>> +#ifdef CONFIG_ARM
>>  		spl_image.load_addr = spl_image.entry_point - header_size;
>> +#else
>> +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
>> +#endif
> 
> This isn't an ARM-ism but is instead because spl_nor.c isn't offsetting
> where the header is like mmc/nand/ymodem do, yes?  Would it be possible
> to make spl_nor.c behave like the others?  One of the reasons I ask is
> I'm looking at a NOR chip on my desk...

I was wondering about this line as well. Please explain: Why can't ARM
just use header->ih_load as load_addr?

Thanks,
Stefan

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Tom Rini]

On 08/23/2012 11:16 AM, Stefan Roese wrote:
> On 08/23/2012 07:10 PM, Tom Rini wrote:
>>> +#ifdef CONFIG_ARM
>>>  /* Define global data structure pointer to it*/
>>>  gd_t gdata __attribute__ ((section(".data")));
>>> +#endif
>>
>> So you handle cleaning up the BSS differently, interesting.  I'm going
>> to see if that would work for ARM too..
> 
> Yes. Might be that I missed something though. I'll re-check tomorrow.
> 
>> [snip]
>>> @@ -89,7 +106,11 @@ void spl_parse_image_header(const struct image_header *header)
>>>  		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
>>>  		spl_image.entry_point = __be32_to_cpu(header->ih_load);
>>>  		/* Load including the header */
>>> +#ifdef CONFIG_ARM
>>>  		spl_image.load_addr = spl_image.entry_point - header_size;
>>> +#else
>>> +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
>>> +#endif
>>
>> This isn't an ARM-ism but is instead because spl_nor.c isn't offsetting
>> where the header is like mmc/nand/ymodem do, yes?  Would it be possible
>> to make spl_nor.c behave like the others?  One of the reasons I ask is
>> I'm looking at a NOR chip on my desk...
> 
> I was wondering about this line as well. Please explain: Why can't ARM
> just use header->ih_load as load_addr?

Off the top of my head, I believe what goes on is that we read things
into SDRAM such that the header is taken into account and we don't need
to relocate the payload (U-Boot or Linux).

-- 
Tom

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Tom Rini]

On 08/23/2012 01:12 AM, Stefan Roese wrote:

> This patch enables the SPL framework to be used on powerpc platforms
> and not only ARM.
[snip]
> +#ifdef CONFIG_ARM
>  	gd = &gdata;
> +#endif

So, here's what I don't understand.  On ARM, in general, we can't rely
on the global data pointer register (r8) to be set to a useful value, so
we do the above to ensure it points to something useful.  Are you always
able to rely on r2 it looks like pointing to something useful?  Or do
you take care of this much earlier on in powerpc?  Thanks!

-- 
Tom

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Tom Rini]

On 08/23/2012 01:12 AM, Stefan Roese wrote:

> This patch enables the SPL framework to be used on powerpc platforms
> and not only ARM.
[snip]
> +#ifdef CONFIG_PPC
> +static void __noreturn jump_to_image_linux(void *arg)
> +{
> +	debug("Entering kernel arg pointer: 0x%p\n", arg);
> +	typedef void (*image_entry_arg_t)(void *, ulong r4, ulong r5, ulong r6,
> +					  ulong r7, ulong r8, ulong r9)
> +		__attribute__ ((noreturn));
> +	image_entry_arg_t image_entry =
> +		(image_entry_arg_t)spl_image.entry_point;
> +
> +	image_entry(arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, 0, 0);
> +}
> +#endif /* CONFIG_PPC */
> +#endif /* CONFIG_SPL_OS_BOOT */

This, along with board_init_f make me wonder if we shouldn't have an
arch/${ARCH}/lib/spl.c that contains them and make them non-static.
Perhaps sharing with the non-SPL code portion as well?

-- 
Tom

[U-Boot] [PATCH 0/6] SPL: Port SPL framework to powerpc

[Tom Rini]

On 08/23/2012 01:12 AM, Stefan Roese wrote:
> This patchset ports the SPL framework to powerpc. Its based on the
> SPL generalization lately done by Tom Rini. The patches can be applied
> on top of his 3rd version located here:
> 
> http://github.com/trini/u-boot WIP/spl-improvements
> 
> Additionally, a new MPC5200 board port is included, the a3m071 board
> port. This board port uses this SPL framework mainly to speed up
> booting into the OS (Linux of course). Detection of Linux vs. U-Boot
> booting is done here by checking the environment variable "boot_os".
> If "boot_os" is set to "yes", then the OS (Linux) is booted. Otherwise
> the "real" U-Boot is booted. For this env checking in the SPL, a small
> restructuring of the env code has been done.
> 
> Comments welcome!

My first comment is, yay!  In general, things look good, and I've just
got a few questions I've replied to the respective patch with.

-- 
Tom

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

Hi Tom,

On 08/23/2012 11:39 PM, Tom Rini wrote:
> On 08/23/2012 01:12 AM, Stefan Roese wrote:
> 
>> This patch enables the SPL framework to be used on powerpc platforms
>> and not only ARM.
> [snip]
>> +#ifdef CONFIG_ARM
>>  	gd = &gdata;
>> +#endif
> 
> So, here's what I don't understand.  On ARM, in general, we can't rely
> on the global data pointer register (r8) to be set to a useful value, so
> we do the above to ensure it points to something useful.  Are you always
> able to rely on r2 it looks like pointing to something useful?  Or do
> you take care of this much earlier on in powerpc?  Thanks!

You are correct, I missed something here. r2 was still configured to the
value written to it from the "real" U-Boot (pointing to internal SRAM).

I can't use the code in preloader_console_init() though to setup the gd
pointer. As I need to write some values in gd *before* calling
preloader_console_init() (mainly clocks for serial driver). And since
this "gd stuff" is quite platform specific, we should probably move this
into an platform/arch spl file instead. As you also mentioned in another
reply to create an arch/${ARCH}/lib/spl.c file.

What do you think? Can you move this gd init stuff into such a common
ARM spl file in the next patchset version?

Thanks,
Stefan

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

Hi Tom,

On 08/23/2012 11:52 PM, Tom Rini wrote:
> On 08/23/2012 01:12 AM, Stefan Roese wrote:
> 
>> This patch enables the SPL framework to be used on powerpc platforms
>> and not only ARM.
> [snip]
>> +#ifdef CONFIG_PPC
>> +static void __noreturn jump_to_image_linux(void *arg)
>> +{
>> +	debug("Entering kernel arg pointer: 0x%p\n", arg);
>> +	typedef void (*image_entry_arg_t)(void *, ulong r4, ulong r5, ulong r6,
>> +					  ulong r7, ulong r8, ulong r9)
>> +		__attribute__ ((noreturn));
>> +	image_entry_arg_t image_entry =
>> +		(image_entry_arg_t)spl_image.entry_point;
>> +
>> +	image_entry(arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, 0, 0);
>> +}
>> +#endif /* CONFIG_PPC */
>> +#endif /* CONFIG_SPL_OS_BOOT */
> 
> This, along with board_init_f make me wonder if we shouldn't have an
> arch/${ARCH}/lib/spl.c that contains them and make them non-static.
> Perhaps sharing with the non-SPL code portion as well?

Yes. Makes definitely sense. Please see my comments in the other mail.

Thanks,
Stefan

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

Hi Tom,

On 08/23/2012 09:31 PM, Tom Rini wrote:
>>>> @@ -89,7 +106,11 @@ void spl_parse_image_header(const struct image_header *header)
>>>>  		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
>>>>  		spl_image.entry_point = __be32_to_cpu(header->ih_load);
>>>>  		/* Load including the header */
>>>> +#ifdef CONFIG_ARM
>>>>  		spl_image.load_addr = spl_image.entry_point - header_size;
>>>> +#else
>>>> +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
>>>> +#endif
>>>
>>> This isn't an ARM-ism but is instead because spl_nor.c isn't offsetting
>>> where the header is like mmc/nand/ymodem do, yes?  Would it be possible
>>> to make spl_nor.c behave like the others?  One of the reasons I ask is
>>> I'm looking at a NOR chip on my desk...
>>
>> I was wondering about this line as well. Please explain: Why can't ARM
>> just use header->ih_load as load_addr?
> 
> Off the top of my head, I believe what goes on is that we read things
> into SDRAM such that the header is taken into account and we don't need
> to relocate the payload (U-Boot or Linux).

Hmmm. So for example, when ih_load is set to 0x100000, then you load the
image to (0x100000 - 0x40) = 0xfffc0? Is this correct?

This can't work for powerpc. As here for Linux both load-address and
entry-point are set to 0. So when loading the image (e.g. from NOR flash)
can't copy the image header in front of the image.

Another thing I'm wondering about: Why is only ih_load from the mkimage
header used and not ih_ep (entry-point)?

I suggest that we switch to copying the "real" image (payload) to the load
address, skipping the header. Then "ih_load" and "ih_ep" can be used
without modification.

BTW: There also seems to be a bug in some of the SPL loaders:

For example in drivers/mtd/nand/nand_spl_load.c:

		...
		if (header->ih_os == IH_OS_LINUX) {
			/* happy - was a linux */
			nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
				spl_image.size, (void *)spl_image.load_addr);

The problem here is that the last 64 bytes of the image are not
copied to SDRAM. Since the header is copied which is not included
in the spl_image.size variable. With my idea of only copying
the payload (skipping the header) this would be:

			nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS +
				sizeof(struct image_header),
				spl_image.size, (void *)spl_image.load_addr);

What do you think? Should we switch to this way of loading images?
Seems more logical to me. And we don't run into problems where the
load address is 0.

Thanks,
Stefan

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Heiko Schocher]

Hello Stefan

On 24.08.2012 10:17, Stefan Roese wrote:
> Hi Tom,
>
> On 08/23/2012 09:31 PM, Tom Rini wrote:
>>>>> @@ -89,7 +106,11 @@ void spl_parse_image_header(const struct image_header *header)
>>>>>   		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
>>>>>   		spl_image.entry_point = __be32_to_cpu(header->ih_load);
>>>>>   		/* Load including the header */
>>>>> +#ifdef CONFIG_ARM
>>>>>   		spl_image.load_addr = spl_image.entry_point - header_size;
>>>>> +#else
>>>>> +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
>>>>> +#endif
>>>>
>>>> This isn't an ARM-ism but is instead because spl_nor.c isn't offsetting
>>>> where the header is like mmc/nand/ymodem do, yes?  Would it be possible
>>>> to make spl_nor.c behave like the others?  One of the reasons I ask is
>>>> I'm looking at a NOR chip on my desk...
>>>
>>> I was wondering about this line as well. Please explain: Why can't ARM
>>> just use header->ih_load as load_addr?
>>
>> Off the top of my head, I believe what goes on is that we read things
>> into SDRAM such that the header is taken into account and we don't need
>> to relocate the payload (U-Boot or Linux).
>
> Hmmm. So for example, when ih_load is set to 0x100000, then you load the
> image to (0x100000 - 0x40) = 0xfffc0? Is this correct?
>
> This can't work for powerpc. As here for Linux both load-address and
> entry-point are set to 0. So when loading the image (e.g. from NOR flash)
> can't copy the image header in front of the image.
>
> Another thing I'm wondering about: Why is only ih_load from the mkimage
> header used and not ih_ep (entry-point)?
>
> I suggest that we switch to copying the "real" image (payload) to the load
> address, skipping the header. Then "ih_load" and "ih_ep" can be used
> without modification.

Yep, this seems a good idea to me.

> BTW: There also seems to be a bug in some of the SPL loaders:
>
> For example in drivers/mtd/nand/nand_spl_load.c:
>
> 		...
> 		if (header->ih_os == IH_OS_LINUX) {
> 			/* happy - was a linux */
> 			nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
> 				spl_image.size, (void *)spl_image.load_addr);
>
> The problem here is that the last 64 bytes of the image are not
> copied to SDRAM. Since the header is copied which is not included
> in the spl_image.size variable. With my idea of only copying
> the payload (skipping the header) this would be:
>
> 			nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS +
> 				sizeof(struct image_header),
> 				spl_image.size, (void *)spl_image.load_addr);
>
> What do you think? Should we switch to this way of loading images?
> Seems more logical to me. And we don't run into problems where the
> load address is 0.

Yes, that should be the way to go ... @Simon: Do you see here some
reason for not switching to copy the real payload?

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

Hi Heiko,

On 08/24/2012 12:17 PM, Heiko Schocher wrote:
>> BTW: There also seems to be a bug in some of the SPL loaders:
>>
>> For example in drivers/mtd/nand/nand_spl_load.c:
>>
>> 		...
>> 		if (header->ih_os == IH_OS_LINUX) {
>> 			/* happy - was a linux */
>> 			nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
>> 				spl_image.size, (void *)spl_image.load_addr);
>>
>> The problem here is that the last 64 bytes of the image are not
>> copied to SDRAM. Since the header is copied which is not included
>> in the spl_image.size variable.

Okay. I just noticed that it's not a bug. spl_image.size is set to
header->ih_size + header_size. So 64 is added and the complete payload
is copied.

I still would like to move to my suggestion to not copy the header and
use the mkimage header values ih_load and ih_ep directly. Right now I
don't see any showstopper for doing it this way. I'll send a patch to
change this shortly (if everything works out).

Stay tuned...

Thanks,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

On 08/24/2012 12:56 PM, Stefan Roese wrote:
> I still would like to move to my suggestion to not copy the header and
> use the mkimage header values ih_load and ih_ep directly. Right now I
> don't see any showstopper for doing it this way. I'll send a patch to
> change this shortly (if everything works out).

Hmmm. As it seems some SPL loading drivers (block like mmc, streaming
like ymodem) are not that easily converted to skipping the header. So
I'm not so sure if we should go this way after all...

Comments?

Thanks,
Stefan

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Daniel Schwierzeck]

Hi Stefan,

2012/8/24 Stefan Roese <sr@denx.de>:
> On 08/24/2012 12:56 PM, Stefan Roese wrote:
>> I still would like to move to my suggestion to not copy the header and
>> use the mkimage header values ih_load and ih_ep directly. Right now I
>> don't see any showstopper for doing it this way. I'll send a patch to
>> change this shortly (if everything works out).
>
> Hmmm. As it seems some SPL loading drivers (block like mmc, streaming
> like ymodem) are not that easily converted to skipping the header. So
> I'm not so sure if we should go this way after all...
>
> Comments?
>

I did similar work for my upcoming Lantiq MIPS SoC port. In my
approach I also support compressed u-boot
images as payload (LZO, LZMA). The u-boot image is merged with SPL
image without any padding or
fixed flash offsets to achieve a maximum reduction of flash footprint.

I ended up with doing something like this:

static int spl_parse_image(const image_header_t *hdr, struct spl_image *spl)
{
       u32 magic;

       magic = image_get_magic(hdr);
       if (magic != IH_MAGIC)
               return -1;

       spl->data_addr += image_get_header_size();
       spl->entry_addr = image_get_load(hdr);
       spl->size = image_get_data_size(hdr);
       spl->comp = image_get_comp(hdr);

       if (spl->comp == IH_COMP_NONE)
               spl->load_addr = spl->entry_addr;
       else
               spl->load_addr = CONFIG_LOADADDR;

       return 0;
}

spl->data_addr points to the image header of the payload and is
initialized by the caller
dependent on the used load mechanism. If the payload is uncompressed
it can be directly copied to
its final RAM location. A compressed payload needs an intermediate
copy step if it is stored in SPI or NAND flash.
I chose CONFIG_LOADADDR. After this the decompression function
extracts the image to its final RAM location.

I think we should keep an architecture-neutral SPL image context
inside the generic SPL framework.
The content of this context should be filled by architecture/SoC/board
specific code.

-- 
Best regards,
Daniel

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

Hi Daniel,

On 08/24/2012 01:49 PM, Daniel Schwierzeck wrote:
>>> I still would like to move to my suggestion to not copy the header and
>>> use the mkimage header values ih_load and ih_ep directly. Right now I
>>> don't see any showstopper for doing it this way. I'll send a patch to
>>> change this shortly (if everything works out).
>>
>> Hmmm. As it seems some SPL loading drivers (block like mmc, streaming
>> like ymodem) are not that easily converted to skipping the header. So
>> I'm not so sure if we should go this way after all...
>>
>> Comments?
> 
> I did similar work for my upcoming Lantiq MIPS SoC port. In my
> approach I also support compressed u-boot
> images as payload (LZO, LZMA).

Yes, I thought about adding this as well. Nice.

> The u-boot image is merged with SPL
> image without any padding or
> fixed flash offsets to achieve a maximum reduction of flash footprint.

Interesting. I'm still padding to the fixed offset. Let me look into
squeezing those two images together as well...

> I ended up with doing something like this:
> 
> static int spl_parse_image(const image_header_t *hdr, struct spl_image *spl)
> {
>        u32 magic;
> 
>        magic = image_get_magic(hdr);
>        if (magic != IH_MAGIC)
>                return -1;
> 
>        spl->data_addr += image_get_header_size();
>        spl->entry_addr = image_get_load(hdr);
>        spl->size = image_get_data_size(hdr);
>        spl->comp = image_get_comp(hdr);
> 
>        if (spl->comp == IH_COMP_NONE)
>                spl->load_addr = spl->entry_addr;
>        else
>                spl->load_addr = CONFIG_LOADADDR;
> 
>        return 0;
> }

So you introduced a new "struct spl_image" and did not use "struct
spl_image_info" from the SPL framework? Why is that? We should
definitely consolidate to one structure here.

> spl->data_addr points to the image header of the payload and is
> initialized by the caller
> dependent on the used load mechanism.

Good idea. Looks like your spl_parse_image might be a potential
replacement for spl_parse_image_header() from this common SPL framework.

> If the payload is uncompressed
> it can be directly copied to
> its final RAM location. A compressed payload needs an intermediate
> copy step if it is stored in SPI or NAND flash.
> I chose CONFIG_LOADADDR. After this the decompression function
> extracts the image to its final RAM location.

Sounds good. Do you have some patches that you could send for review?
Did you try to keep as much platform/arch independent as possible?

> I think we should keep an architecture-neutral SPL image context
> inside the generic SPL framework.
> The content of this context should be filled by architecture/SoC/board
> specific code.

Ack. It would be great to review your code here. Please keep us informed.

Thanks,
Stefan

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Daniel Schwierzeck]

Hi Stefan,

2012/8/24 Stefan Roese <sr@denx.de>:
> Hi Daniel,
>
> On 08/24/2012 01:49 PM, Daniel Schwierzeck wrote:
>>>> I still would like to move to my suggestion to not copy the header and
>>>> use the mkimage header values ih_load and ih_ep directly. Right now I
>>>> don't see any showstopper for doing it this way. I'll send a patch to
>>>> change this shortly (if everything works out).
>>>
>>> Hmmm. As it seems some SPL loading drivers (block like mmc, streaming
>>> like ymodem) are not that easily converted to skipping the header. So
>>> I'm not so sure if we should go this way after all...
>>>
>>> Comments?
>>
>> I did similar work for my upcoming Lantiq MIPS SoC port. In my
>> approach I also support compressed u-boot
>> images as payload (LZO, LZMA).
>
> Yes, I thought about adding this as well. Nice.
>
>> The u-boot image is merged with SPL
>> image without any padding or
>> fixed flash offsets to achieve a maximum reduction of flash footprint.
>
> Interesting. I'm still padding to the fixed offset. Let me look into
> squeezing those two images together as well...
>
>> I ended up with doing something like this:
>>
>> static int spl_parse_image(const image_header_t *hdr, struct spl_image *spl)
>> {
>>        u32 magic;
>>
>>        magic = image_get_magic(hdr);
>>        if (magic != IH_MAGIC)
>>                return -1;
>>
>>        spl->data_addr += image_get_header_size();
>>        spl->entry_addr = image_get_load(hdr);
>>        spl->size = image_get_data_size(hdr);
>>        spl->comp = image_get_comp(hdr);
>>
>>        if (spl->comp == IH_COMP_NONE)
>>                spl->load_addr = spl->entry_addr;
>>        else
>>                spl->load_addr = CONFIG_LOADADDR;
>>
>>        return 0;
>> }
>
> So you introduced a new "struct spl_image" and did not use "struct
> spl_image_info" from the SPL framework? Why is that? We should
> definitely consolidate to one structure here.

I implemented this after the initial SPL infrastructure got merged
into mainline one year ago.
At this time a generic SPL framework did not exist ;)

>
>> spl->data_addr points to the image header of the payload and is
>> initialized by the caller
>> dependent on the used load mechanism.
>
> Good idea. Looks like your spl_parse_image might be a potential
> replacement for spl_parse_image_header() from this common SPL framework.
>
>> If the payload is uncompressed
>> it can be directly copied to
>> its final RAM location. A compressed payload needs an intermediate
>> copy step if it is stored in SPI or NAND flash.
>> I chose CONFIG_LOADADDR. After this the decompression function
>> extracts the image to its final RAM location.
>
> Sounds good. Do you have some patches that you could send for review?
> Did you try to keep as much platform/arch independent as possible?

Not yet. I had not time yet to adopt my work to the new common SPL framework.

My current SPL solution is queued here:
http://dev.phrozen.org/gitweb/?p=uboot-upstream.git;a=commitdiff;h=39165fa145b2d959f1eaa6faa3ab3053823bb985

>
>> I think we should keep an architecture-neutral SPL image context
>> inside the generic SPL framework.
>> The content of this context should be filled by architecture/SoC/board
>> specific code.
>
> Ack. It would be great to review your code here. Please keep us informed.
>

Actually this was my response to your original question.
Quote:
> I still would like to move to my suggestion to not copy the header and
> use the mkimage header values ih_load and ih_ep directly. Right now I
> don't see any showstopper for doing it this way. I'll send a patch to
> change this shortly (if everything works out).

So I suggest to not remove the 'struct spl_image_info'.

-- 
Best regards,
Daniel

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Tom Rini]

On 08/24/2012 12:01 AM, Stefan Roese wrote:
> Hi Tom,
> 
> On 08/23/2012 11:39 PM, Tom Rini wrote:
>> On 08/23/2012 01:12 AM, Stefan Roese wrote:
>>
>>> This patch enables the SPL framework to be used on powerpc platforms
>>> and not only ARM.
>> [snip]
>>> +#ifdef CONFIG_ARM
>>>  	gd = &gdata;
>>> +#endif
>>
>> So, here's what I don't understand.  On ARM, in general, we can't rely
>> on the global data pointer register (r8) to be set to a useful value, so
>> we do the above to ensure it points to something useful.  Are you always
>> able to rely on r2 it looks like pointing to something useful?  Or do
>> you take care of this much earlier on in powerpc?  Thanks!
> 
> You are correct, I missed something here. r2 was still configured to the
> value written to it from the "real" U-Boot (pointing to internal SRAM).
> 
> I can't use the code in preloader_console_init() though to setup the gd
> pointer. As I need to write some values in gd *before* calling
> preloader_console_init() (mainly clocks for serial driver). And since
> this "gd stuff" is quite platform specific, we should probably move this
> into an platform/arch spl file instead. As you also mentioned in another
> reply to create an arch/${ARCH}/lib/spl.c file.
> 
> What do you think? Can you move this gd init stuff into such a common
> ARM spl file in the next patchset version?

Yes.  We should probably say it's the job of board_init_f.  I know full
U-Boot does it at the start of board_init_r but I think for SPL it makes
sense to document that board_init_f does any early init it needs to,
clears BSS, sets up gd and calls board_init_r.

-- 
Tom

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

Hi Daniel,

On 08/24/2012 04:11 PM, Stefan Roese wrote:
>> The u-boot image is merged with SPL
>> image without any padding or
>> fixed flash offsets to achieve a maximum reduction of flash footprint.
> 
> Interesting. I'm still padding to the fixed offset. Let me look into
> squeezing those two images together as well...

Looks good. One question though: How do you make sure, that your SPL
image length is 4-byte aligned?

Thanks,
Stefan

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

On 08/24/2012 05:55 PM, Tom Rini wrote:
>>> So, here's what I don't understand.  On ARM, in general, we can't rely
>>> on the global data pointer register (r8) to be set to a useful value, so
>>> we do the above to ensure it points to something useful.  Are you always
>>> able to rely on r2 it looks like pointing to something useful?  Or do
>>> you take care of this much earlier on in powerpc?  Thanks!
>>
>> You are correct, I missed something here. r2 was still configured to the
>> value written to it from the "real" U-Boot (pointing to internal SRAM).
>>
>> I can't use the code in preloader_console_init() though to setup the gd
>> pointer. As I need to write some values in gd *before* calling
>> preloader_console_init() (mainly clocks for serial driver). And since
>> this "gd stuff" is quite platform specific, we should probably move this
>> into an platform/arch spl file instead. As you also mentioned in another
>> reply to create an arch/${ARCH}/lib/spl.c file.
>>
>> What do you think? Can you move this gd init stuff into such a common
>> ARM spl file in the next patchset version?
> 
> Yes.  We should probably say it's the job of board_init_f.  I know full
> U-Boot does it at the start of board_init_r but I think for SPL it makes
> sense to document that board_init_f does any early init it needs to,
> clears BSS, sets up gd and calls board_init_r.

Full ack. In my next patchset version, I already extracted this gd setup
into board_init_f().

Thanks,
Stefan

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Tom Rini]

On 08/24/2012 09:07 AM, Stefan Roese wrote:
> On 08/24/2012 05:55 PM, Tom Rini wrote:
>>>> So, here's what I don't understand.  On ARM, in general, we can't rely
>>>> on the global data pointer register (r8) to be set to a useful value, so
>>>> we do the above to ensure it points to something useful.  Are you always
>>>> able to rely on r2 it looks like pointing to something useful?  Or do
>>>> you take care of this much earlier on in powerpc?  Thanks!
>>>
>>> You are correct, I missed something here. r2 was still configured to the
>>> value written to it from the "real" U-Boot (pointing to internal SRAM).
>>>
>>> I can't use the code in preloader_console_init() though to setup the gd
>>> pointer. As I need to write some values in gd *before* calling
>>> preloader_console_init() (mainly clocks for serial driver). And since
>>> this "gd stuff" is quite platform specific, we should probably move this
>>> into an platform/arch spl file instead. As you also mentioned in another
>>> reply to create an arch/${ARCH}/lib/spl.c file.
>>>
>>> What do you think? Can you move this gd init stuff into such a common
>>> ARM spl file in the next patchset version?
>>
>> Yes.  We should probably say it's the job of board_init_f.  I know full
>> U-Boot does it at the start of board_init_r but I think for SPL it makes
>> sense to document that board_init_f does any early init it needs to,
>> clears BSS, sets up gd and calls board_init_r.
> 
> Full ack. In my next patchset version, I already extracted this gd setup
> into board_init_f().

OK good, I just booted and reset my arm9 platform with this
proof-of-concepted over.  I should post v4 today.

-- 
Tom

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Daniel Schwierzeck]

Hi Stefan,

2012/8/24 Stefan Roese <stefan.roese@gmail.com>:
> Hi Daniel,
>
> On 08/24/2012 04:11 PM, Stefan Roese wrote:
>>> The u-boot image is merged with SPL
>>> image without any padding or
>>> fixed flash offsets to achieve a maximum reduction of flash footprint.
>>
>> Interesting. I'm still padding to the fixed offset. Let me look into
>> squeezing those two images together as well...
>
> Looks good. One question though: How do you make sure, that your SPL
> image length is 4-byte aligned?

I have 4-byte alignments for each section and for each address symbol
in my linker script.
Actually all MIPS linker scripts do this.

-- 
Best regards,
Daniel

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

On 08/24/2012 06:19 PM, Tom Rini wrote:
>>>> What do you think? Can you move this gd init stuff into such a common
>>>> ARM spl file in the next patchset version?
>>>
>>> Yes.  We should probably say it's the job of board_init_f.  I know full
>>> U-Boot does it at the start of board_init_r but I think for SPL it makes
>>> sense to document that board_init_f does any early init it needs to,
>>> clears BSS, sets up gd and calls board_init_r.
>>
>> Full ack. In my next patchset version, I already extracted this gd setup
>> into board_init_f().
> 
> OK good, I just booted and reset my arm9 platform with this
> proof-of-concepted over.  I should post v4 today.

Great. I'll rebase my patches on top of that next week then.

Thanks,
Stefan

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

On 08/24/2012 06:42 PM, Daniel Schwierzeck wrote:
>>>> The u-boot image is merged with SPL
>>>> image without any padding or
>>>> fixed flash offsets to achieve a maximum reduction of flash footprint.
>>>
>>> Interesting. I'm still padding to the fixed offset. Let me look into
>>> squeezing those two images together as well...
>>
>> Looks good. One question though: How do you make sure, that your SPL
>> image length is 4-byte aligned?
> 
> I have 4-byte alignments for each section and for each address symbol
> in my linker script.
> Actually all MIPS linker scripts do this.

Yes. I have those section alignments in the linker script as well. The
problem is the end of the last (physical end in flash) section. If I
have here a string with length 7 for example, the SPL binary has a
non-4-byte aligned length.

Any ideas on this?

Thanks,
Stefan

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Tom Rini]

On 08/24/2012 04:13 AM, Stefan Roese wrote:
> On 08/24/2012 12:56 PM, Stefan Roese wrote:
>> I still would like to move to my suggestion to not copy the header and
>> use the mkimage header values ih_load and ih_ep directly. Right now I
>> don't see any showstopper for doing it this way. I'll send a patch to
>> change this shortly (if everything works out).
> 
> Hmmm. As it seems some SPL loading drivers (block like mmc, streaming
> like ymodem) are not that easily converted to skipping the header. So
> I'm not so sure if we should go this way after all...

Maybe I'm missing something, but maybe we just need to mimic the
behavior full U-Boot does and if we haven't been loaded where we need to
execute, shift bits around?

-- 
Tom

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Daniel Schwierzeck]

2012/8/24 Stefan Roese <stefan.roese@gmail.com>:
> On 08/24/2012 06:42 PM, Daniel Schwierzeck wrote:
>>>>> The u-boot image is merged with SPL
>>>>> image without any padding or
>>>>> fixed flash offsets to achieve a maximum reduction of flash footprint.
>>>>
>>>> Interesting. I'm still padding to the fixed offset. Let me look into
>>>> squeezing those two images together as well...
>>>
>>> Looks good. One question though: How do you make sure, that your SPL
>>> image length is 4-byte aligned?
>>
>> I have 4-byte alignments for each section and for each address symbol
>> in my linker script.
>> Actually all MIPS linker scripts do this.
>
> Yes. I have those section alignments in the linker script as well. The
> problem is the end of the last (physical end in flash) section. If I
> have here a string with length 7 for example, the SPL binary has a
> non-4-byte aligned length.
>
> Any ideas on this?

MIPS linker scripts have a symbol in front of the BSS section that is
named uboot_end_data.
I think most ARM linker scripts have it too but it is named __image_copy_end.
This symbol is 4-byte-aligned. If I want to know the length of SPL
image i can simply do

ulong len = (ulong) &__image_copy_end - CONFIG_SPL_TEXT_BASE

and len is 4-byte-aligned

-- 
Best regards,
Daniel

[U-Boot] [PATCH 3/6] SPL: Port SPL framework to powerpc

[Stefan Roese]

On 08/24/2012 09:15 PM, Tom Rini wrote:
>>> I still would like to move to my suggestion to not copy the header and
>>> use the mkimage header values ih_load and ih_ep directly. Right now I
>>> don't see any showstopper for doing it this way. I'll send a patch to
>>> change this shortly (if everything works out).
>>
>> Hmmm. As it seems some SPL loading drivers (block like mmc, streaming
>> like ymodem) are not that easily converted to skipping the header. So
>> I'm not so sure if we should go this way after all...
> 
> Maybe I'm missing something, but maybe we just need to mimic the
> behavior full U-Boot does and if we haven't been loaded where we need to
> execute, shift bits around?

Of course its possible. The main problem is speed here. With the
"problematic" drivers like mmc, you would need to copy the image a 2nd
time, once from MMC to a temp. SDRAM location, and then to its final
(load_addr) destination. With the current approach, the image is only
copied once from MMC to SDRAM. The 2nd copy shouldn't take that long
though. Its SDRAM to SDRAM after all.

I really do like Daniel's approach, with the decompression support:

http://dev.phrozen.org/gitweb/?p=uboot-upstream.git;a=commitdiff;h=39165fa145b2d959f1eaa6faa3ab3053823bb985

We should try to merge this into the current SPL framework. I'll try to
look into this next week.

Thanks,
Stefan