From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bo Shen Date: Mon, 27 Aug 2012 14:01:14 +0800 Subject: [U-Boot] [PATCH v3 4/5] at91: 9x5: change SMC config timing that both works for PMECC & non-PMECC. In-Reply-To: <1345716338-11217-5-git-send-email-josh.wu@atmel.com> References: <1345716338-11217-1-git-send-email-josh.wu@atmel.com> <1345716338-11217-5-git-send-email-josh.wu@atmel.com> Message-ID: <503B0D2A.7050906@atmel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Josh, On 8/23/2012 18:05, Josh Wu wrote: > Signed-off-by: Josh Wu > --- > board/atmel/at91sam9x5ek/at91sam9x5ek.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c > index 88b3478..ae408bc 100644 > --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c > +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c > @@ -65,13 +65,13 @@ static void at91sam9x5ek_nand_hw_init(void) > writel(csa, &matrix->ebicsa); > > /* Configure SMC CS3 for NAND/SmartMedia */ > - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | > - AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), > + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | > + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), > &smc->cs[3].setup); > - writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | > - AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), > + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | > + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), > &smc->cs[3].pulse); > - writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), > + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), > &smc->cs[3].cycle); > writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | > AT91_SMC_MODE_EXNW_DISABLE | > @@ -80,7 +80,7 @@ static void at91sam9x5ek_nand_hw_init(void) > #else /* CONFIG_SYS_NAND_DBW_8 */ > AT91_SMC_MODE_DBW_8 | > #endif > - AT91_SMC_MODE_TDF_CYCLE(3), > + AT91_SMC_MODE_TDF_CYCLE(1), > &smc->cs[3].mode); Test these parameters for NAND using software ECC. It works well. Tested-by: voice.shen at atmel.com > > writel(1 << ATMEL_ID_PIOCD, &pmc->pcer); >