[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
---
 MAINTAINERS                                        |    5 +
 Makefile                                           |    2 +-
 arch/arm/cpu/armv7/socfpga/Makefile                |   51 +++++
 arch/arm/cpu/armv7/socfpga/lowlevel_init.S         |   79 +++++++
 arch/arm/cpu/armv7/socfpga/reset_manager.c         |   45 ++++
 arch/arm/cpu/armv7/socfpga/sdram.c                 |   26 +++
 arch/arm/cpu/armv7/socfpga/spl.c                   |  182 +++++++++++++++
 arch/arm/cpu/armv7/socfpga/timer.c                 |  118 ++++++++++
 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds          |   60 +++++
 arch/arm/include/asm/arch-socfpga/reset_manager.h  |   37 +++
 .../include/asm/arch-socfpga/socfpga_base_addrs.h  |   27 +++
 arch/arm/include/asm/arch-socfpga/socfpga_spl.h    |   30 +++
 board/altera/socfpga_cyclone5/Makefile             |   50 ++++
 board/altera/socfpga_cyclone5/socfpga_cyclone5.c   |   97 ++++++++
 boards.cfg                                         |    1 +
 include/configs/socfpga_cyclone5.h                 |  240 ++++++++++++++++++++
 16 files changed, 1049 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/socfpga/Makefile
 create mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/socfpga/reset_manager.c
 create mode 100644 arch/arm/cpu/armv7/socfpga/sdram.c
 create mode 100644 arch/arm/cpu/armv7/socfpga/spl.c
 create mode 100644 arch/arm/cpu/armv7/socfpga/timer.c
 create mode 100644 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
 create mode 100644 arch/arm/include/asm/arch-socfpga/reset_config.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/reset_manager.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/socfpga_spl.h
 create mode 100644 board/altera/socfpga_cyclone5/Makefile
 create mode 100644 board/altera/socfpga_cyclone5/socfpga_cyclone5.c
 create mode 100644 include/configs/socfpga_cyclone5.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c5a6f2f..df48dea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -765,6 +765,11 @@ Nagendra T S  <nagendra@mistralsolutions.com>
 
    am3517_crane    ARM ARMV7 (AM35x SoC)
 
+Dinh Nguyen <dinguyen@altera.com>
+Chin Liang See <clsee@altera.com>
+
+	socfpga		socfpga_cyclone5
+
 Kyungmin Park <kyungmin.park@samsung.com>
 
 	apollon		ARM1136EJS
diff --git a/Makefile b/Makefile
index 5ce5cc3..12aa372 100644
--- a/Makefile
+++ b/Makefile
@@ -369,7 +369,7 @@ BOARD_SIZE_CHECK =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
+ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)u-boot.img $(obj)System.map
 
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
new file mode 100644
index 0000000..e4c1213
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2012 Altera Corporation <www.altera.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	:= lowlevel_init.o
+COBJS-y	:= reset_manager.o sdram.o timer.o
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
new file mode 100644
index 0000000..815073e
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
@@ -0,0 +1,79 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Save the parameter pass in by previous boot loader */
+.global save_boot_params
+save_boot_params:
+	/* save the parameter here */
+
+	/*
+	 * Setup stack for exception, which is located
+	 * at the end of on-chip RAM. We don't expect exception prior to
+	 * relocation and if that happens, we won't worry -- it will overide
+	 * global data region as the code will goto reset. After relocation,
+	 * this region won't be used by other part of program.
+	 * Hence it is safe.
+	 */
+	ldr	r0, =CONFIG_SYS_INIT_RAM_ADDR
+	ldr	r1, =CONFIG_SYS_INIT_RAM_SIZE
+	add	r0, r0, r1
+	ldr	r1, =IRQ_STACK_START_IN
+	str	r0, [r1]
+
+	bx	lr
+
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Remap */
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * SPL : configure the remap (L3 NIC-301 GPV)
+	 * so the on-chip RAM at lower memory instead ROM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x19
+	str	r1, [r0]
+#else
+	/*
+	 * U-Boot : configure the remap (L3 NIC-301 GPV)
+	 * so the SDRAM at lower memory instead on-chip RAM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x2
+	str	r1, [r0]
+
+	/* Private components security */
+
+	/*
+	 * U-Boot : configure private timer, global timer and cpu
+	 * component access as non secure for kernel stage (as required
+	 * by kernel)
+	 */
+	mrc	p15,4,r0,c15,c0,0
+	add	r1, r0, #0x54
+	ldr	r2, [r1]
+	orr	r2, r2, #0xff
+	orr	r2, r2, #0xf00
+	str	r2, [r1]
+#endif	/* #ifdef CONFIG_SPL_BUILD */
+	mov	pc, lr
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
new file mode 100644
index 0000000..b0fa211
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -0,0 +1,45 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+	/* request a warm reset */
+	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
+	/* infinite loop here as watchdog will trigger and reset
+	 * the processor */
+	while (1)
+		;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+	unsigned int val = 0;
+	writel(val, &reset_manager_base->per_mod_reset);
+}
diff --git a/arch/arm/cpu/armv7/socfpga/sdram.c b/arch/arm/cpu/armv7/socfpga/sdram.c
new file mode 100644
index 0000000..6714983
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/sdram.c
@@ -0,0 +1,26 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
new file mode 100644
index 0000000..7bd1e2f
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -0,0 +1,182 @@
+ /*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <asm/arch/socfpga_spl.h>
+#include <version.h>
+#include <image.h>
+#include <malloc.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 *boot_params_ptr;
+static struct spl_image_info spl_image;
+
+extern void __malloc_start, __malloc_end, __stack_start;
+
+/* Define global data structure pointer to it */
+static gd_t gdata __attribute__ ((section(".data")));
+
+/*
+ * Error action
+ */
+inline void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+/*
+ * Read the mkimage signature to extract info such as entry point.
+ * The header is generated by tools/mkimage
+ */
+static unsigned long spl_parse_image_header(const struct image_header *header)
+{
+	/* checking for mkimage signature */
+	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
+		/* Valid image. Extract information out of header */
+		spl_image.size = __be32_to_cpu(header->ih_size);
+		spl_image.entry_point = __be32_to_cpu(header->ih_load);
+		spl_image.load_addr = __be32_to_cpu(header->ih_load);
+		spl_image.os = header->ih_os;
+		spl_image.name = (const char *)&header->ih_name;
+		spl_image.crc = __be32_to_cpu(header->ih_dcrc);
+		debug("Subsequent boot image info\n");
+		debug("   Image Name:   %.*s\n", IH_NMLEN, spl_image.name);
+		debug("   Data Size:    %d\n", spl_image.size);
+		debug("   Load Address: 0x%x\n", spl_image.load_addr);
+		debug("   Entry Point:  0x%X\n", spl_image.entry_point);
+	} else {
+		/* Not a valid image as mkimage signature not found */
+		printf("Error : mkimage signature not found - ih_magic = %x\n",
+			header->ih_magic);
+		return 1;
+	}
+
+	/* Checking image type. Do any customize stuff per image type here */
+	switch (spl_image.os) {
+	case IH_OS_U_BOOT:
+		debug("   Image Type:   U-Boot\n");
+		break;
+	default:
+		printf("   Image Type:   Unknown (%d)\n", spl_image.os);
+		;
+	}
+	return 0;
+}
+
+static void spl_ram_load_image(void)
+{
+	u32 err;
+	const struct image_header *header;
+
+	/* get the header */
+	/* it will point to a address defined by handoff which
+	will tell where the image located inside the flash. For now,
+	it will temporary fixed to address pointed by U-Boot */
+	header = (struct image_header *)
+		(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+
+	err = spl_parse_image_header(header);
+	if (err) {
+		puts("SPL : RAM image header error\n");
+		hang();
+	}
+}
+
+/*
+ * Jump to subseqeuent bootloaders / U-boot
+ */
+static void jump_to_image_no_args(void)
+{
+	typedef void (*image_entry_noargs_t)(u32 *)__attribute__ ((noreturn));
+	image_entry_noargs_t image_entry =
+			(image_entry_noargs_t) spl_image.entry_point;
+	/* Pass the saved boot_params from rom code */
+	u32 boot_params_ptr_addr = (u32)&boot_params_ptr;
+
+	puts("\nLeaving SPL ...\n");
+	image_entry((u32 *)boot_params_ptr_addr);
+}
+void jump_to_image_no_args(void) __attribute__ ((noreturn));
+
+
+/*
+ * Console Initialization
+ */
+static void spl_console_init(void)
+{
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+
+	/* serial communications setup */
+	serial_init();
+	gd->have_console = 1;
+}
+
+/*
+ * Board initialization prior bss clearance
+ * Do note below concerns when inserting your function here.
+ * Please refer to README for more details.
+
+ * Initialized global data (data segment) is read-only. Do not attempt
+	to write it.
+
+ * Do not use any uninitialized global data (or implicitely initialized
+	as zero data - BSS segment) at all - this is undefined, initiali-
+	zation is performed later (when relocating to RAM).
+
+ * Stack space is very limited. Avoid big data buffers or things like
+	that.
+ */
+void board_init_f(ulong dummy)
+{
+	/* Will clear bss then jump back to function board_init_r */
+	relocate_code((ulong) &__stack_start, &gdata, CONFIG_SPL_TEXT_BASE);
+}
+
+/*
+ * Board initialization after bss clearance
+ */
+void board_init_r(gd_t *id, ulong dummy)
+{
+	gd = &gdata;
+
+	/* init timer for enabling delay function */
+	timer_init();
+
+	/* de-assert reset for peripherals and bridges based on handoff */
+	reset_deassert_peripherals_handoff();
+
+	/* enable console uart printing */
+	spl_console_init();
+
+	/* setup MALLOC after clocks going faster */
+	mem_malloc_init((ulong) &__malloc_start,
+			(&__malloc_end - &__malloc_start));
+
+	puts("SPL Boot from RAM\n");
+	spl_ram_load_image();
+
+	/* jump to subsequent bootloader */
+	jump_to_image_no_args();
+}
diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
new file mode 100644
index 0000000..1fb3a83
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/timer.c
@@ -0,0 +1,118 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-armv7/systimer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef SYSTIMER_BASE
+#define SYSTIMER_BASE	CONFIG_SYS_TIMERBASE /* Timer 0 base */
+
+static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
+
+static inline unsigned long long time_to_tick()
+{
+	return CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ;
+}
+
+int timer_init(void)
+{
+	writel(TIMER_LOAD_VAL, &systimer_base->timer0load);
+	writel(TIMER_LOAD_VAL, &systimer_base->timer0value);
+	writel((readl((&systimer_base->timer0control)) | 0x3),
+		(&systimer_base->timer0control));
+
+	reset_timer();
+	return 0;
+}
+
+static u32 read_timer(void)
+{
+	return readl(&systimer_base->timer0value);
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long now, last;
+	/*
+	 * get the tmo value based on timer clock speed
+	 * tmo = delay required / period of timer clock
+	 */
+	long tmo = usec * time_to_tick();
+
+	last = read_timer();
+	while (tmo > 0) {
+		now = read_timer();
+		if (last >= now)
+			/* normal mode (non roll) */
+			tmo -= last - now;
+		else
+			/* we have overflow of the count down timer */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		last = now;
+	}
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = read_timer() / time_to_tick();
+	if (gd->lastinc >= now) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* we have overflow of the count down timer */
+		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+	}
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+void reset_timer(void)
+{
+	gd->lastinc = read_timer() / time_to_tick();
+	gd->tbl = 0;
+}
+
+ulong get_timer_count_masked(void)
+{
+	ulong now = read_timer();
+	if (gd->lastinc >= now) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* we have overflow of the count down timer */
+		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+	}
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+ulong get_timer_count(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
new file mode 100644
index 0000000..de74341
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) }
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss : {
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+	. = . + 4;
+	. = ALIGN(8);
+	__malloc_start = .;
+	. = . + CONFIG_SPL_MALLOC_SIZE;
+	__malloc_end = .;
+
+	. = . + 4;
+	. = . + CONFIG_SPL_STACK_SIZE;
+	. = ALIGN(8);
+	__stack_start = .;
+}
diff --git a/arch/arm/include/asm/arch-socfpga/reset_config.h b/arch/arm/include/asm/arch-socfpga/reset_config.h
new file mode 100644
index 0000000..e69de29
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
new file mode 100644
index 0000000..d9d2c1c
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_RESET_MANAGER_H_
+#define	_RESET_MANAGER_H_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+	u32	padding1;
+	u32	ctrl;
+	u32	padding2;
+	u32	padding3;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+};
+
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+
+#endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
new file mode 100644
index 0000000..f353eb2
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_spl.h b/arch/arm/include/asm/arch-socfpga/socfpga_spl.h
new file mode 100644
index 0000000..ee4b6d3
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_spl.h
@@ -0,0 +1,30 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_SOCPFGA_SPL_H_
+#define	_SOCPFGA_SPL_H_
+
+struct spl_image_info {
+	const char *name;
+	u8 os;
+	u32 load_addr;
+	u32 entry_point;
+	u32 size;
+	u32 crc;
+};
+
+#endif /* _SOCPFGA_SPL_H_ */
diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile
new file mode 100644
index 0000000..43bbc37
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= socfpga_cyclone5.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
new file mode 100644
index 0000000..1248e3d
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
@@ -0,0 +1,97 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void show_boot_progress(int progress)
+{
+	debug("Boot reached stage %d\n", progress);
+}
+
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	puts("CPU   : Altera SOCFPGA Platform\n");
+	return 0;
+}
+
+/*
+ * Print Board information
+ */
+int checkboard(void)
+{
+	puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
+	return 0;
+}
+
+/*
+ * Initialization function which happen at early stage of c code
+ */
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	icache_enable();
+	return 0;
+}
+
+/*
+ * miscellaneous platform dependent initialisations
+ */
+int misc_init_r(void)
+{
+	/* Set to "n" for not verifying the uImage */
+	setenv("verify", "n");
+	return 0;
+}
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	return 0;
+}
+#endif
+
+/*
+ * DesignWare Ethernet initialization
+ */
+/* We know all the init functions have been run now */
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..1b5c860 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -261,6 +261,7 @@ seaboard                     arm         armv7       seaboard            nvidia
 ventana                      arm         armv7       ventana             nvidia         tegra2
 whistler                     arm         armv7       whistler            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
+socfpga_cyclone5              arm         armv7      socfpga_cyclone5    altera		    socfpga
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
new file mode 100644
index 0000000..29aa9da
--- /dev/null
+++ b/include/configs/socfpga_cyclone5.h
@@ -0,0 +1,240 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/socfpga_base_addrs.h>
+
+/*
+ * High level configuration
+ */
+
+#define CONFIG_ARMV7
+#define CONFIG_L2_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SINGLE_BOOTLOADER
+#define CONFIG_SOCFPGA
+
+#define CONFIG_SYS_TEXT_BASE		0x08000040
+#define V_NS16550_CLK			1000000
+#define CONFIG_BAUDRATE			57600
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_TIMER_CLOCK_KHZ		2400
+#define CONFIG_SYS_LOAD_ADDR		0x7fc0
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"SOCFPGA_CYCLONE5 # "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Enable early stage initialization at C environment
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* flat device tree */
+#define CONFIG_OF_LIBFDT
+/* skip updating the FDT blob */
+#define CONFIG_FDT_BLOB_SKIP_UPDATE
+/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
+#define CONFIG_SYS_BOOTMAPSZ		((256*1024*1024) - (4*1024))
+
+/*
+ * Memory allocation (MALLOC)
+ */
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE			1024
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+/* regular stack */
+#define CONFIG_STACKSIZE		(128 << 10)
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack */
+#define CONFIG_STACKSIZE_IRQ		(4 << 10)
+/* FIQ stack */
+#define CONFIG_STACKSIZE_FIQ		(4 << 10)
+#endif
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+/* Reserving 0x100 space at back of scratch RAM for debug info */
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
+/* Stack pointer prior relocation, must situated@on-chip RAM */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+/* FAT file system support */
+#define CONFIG_CMD_FAT
+
+
+/*
+ * Misc
+ */
+#define CONFIG_DOS_PARTITION            1
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+/*
+ * Environment setup
+ */
+
+/* Delay before automatically booting the default image */
+#define CONFIG_BOOTDELAY		3
+/* Enable auto completion of commands using TAB */
+#define CONFIG_AUTO_COMPLETE
+/* use "hush" command parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMD_RUN
+
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+/*
+ * arguments passed to the bootm command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M at 0x0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=uImage\0" \
+	"fdt_addr=100\0" \
+	"fsloadcmd=ext2load\0" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* using environment setting for stdin, stdout, stderr */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* Enable the call to overwrite_console() */
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+/* Enable overwrite of previous console environment settings */
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* max number of command args	 */
+#define CONFIG_SYS_MAXARGS		16
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * SDRAM Memory Map
+ */
+/* We have 1 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+/* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+/* SDRAM memory size */
+#define PHYS_SDRAM_1_SIZE		0x80000000
+
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
+
+/*
+ * NS16550 Configuration
+ */
+#define UART0_BASE			SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
+#define CONFIG_CONS_INDEX               1
+#define CONFIG_SYS_NS16550_COM1		UART0_BASE
+
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * FLASH
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/*
+ * SPL "Second Program Loader" aka Initial Software
+ */
+
+/* Enable building of SPL globally */
+#define CONFIG_SPL
+
+/* TEXT_BASE for linking the SPL binary */
+#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
+
+/* Stack size for SPL */
+#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
+
+/* MALLOC size for SPL */
+#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)
+
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CHUNKSZ_CRC32			(1 * 1024)
+
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+/* Support for common/libcommon.o in SPL binary */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+/* Support for lib/libgeneric.o in SPL binary */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#endif	/* __CONFIG_H */
-- 
1.7.9.5

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.

Albert, it seems you should be one merging this...? (Am I right?) Is
there anything we need to fix? Was it too late?

Thanks,
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Marek Vasut]

Dear dinguyen at altera.com,

> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Signed-off-by: Pavel Machek <pavel@denx.de>

[...]

Please CC albert with new arches.

> diff --git a/Makefile b/Makefile
> index 5ce5cc3..12aa372 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -369,7 +369,7 @@ BOARD_SIZE_CHECK =
>  endif
> 
>  # Always append ALL so that arch config.mk's can add custom ones
> -ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
> +ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)u-boot.img
> $(obj)System.map

This won't slide

>  ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
>  ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
[...]

> +/*
> + * Write the reset manager register to cause reset
> + */
> +void reset_cpu(ulong addr)
> +{
> +	/* request a warm reset */
> +	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
> +	/* infinite loop here as watchdog will trigger and reset
> +	 * the processor */
> +	while (1)
> +		;
> +}
> +
> +/*
> + * Release peripherals from reset based on handoff
> + */
> +void reset_deassert_peripherals_handoff(void)
> +{
> +	unsigned int val = 0;
> +	writel(val, &reset_manager_base->per_mod_reset);

writel(0, ...

> +}
> diff --git a/arch/arm/cpu/armv7/socfpga/sdram.c
> b/arch/arm/cpu/armv7/socfpga/sdram.c new file mode 100644
> index 0000000..6714983
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/sdram.c
> @@ -0,0 +1,26 @@
> +/*
> + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <common.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> +	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
> +	return 0;
> +}

Can all this be concentrated into single file (reset, sdram, etc. all those 
small functions).

> diff --git a/arch/arm/cpu/armv7/socfpga/spl.c
> b/arch/arm/cpu/armv7/socfpga/spl.c new file mode 100644
> index 0000000..7bd1e2f
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/spl.c
> @@ -0,0 +1,182 @@
> + /*
> + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/u-boot.h>
> +#include <asm/utils.h>
> +#include <asm/arch/socfpga_spl.h>
> +#include <version.h>
> +#include <image.h>
> +#include <malloc.h>
> +#include <asm/arch/reset_manager.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static u32 *boot_params_ptr;
> +static struct spl_image_info spl_image;
> +
> +extern void __malloc_start, __malloc_end, __stack_start;
> +
> +/* Define global data structure pointer to it */
> +static gd_t gdata __attribute__ ((section(".data")));
> +
> +/*
> + * Error action
> + */
> +inline void hang(void)
> +{
> +	puts("### ERROR ### Please RESET the board ###\n");
> +	for (;;)
> +		;
> +}
> +
> +/*
> + * Read the mkimage signature to extract info such as entry point.
> + * The header is generated by tools/mkimage
> + */
> +static unsigned long spl_parse_image_header(const struct image_header
> *header) +{
> +	/* checking for mkimage signature */
> +	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
> +		/* Valid image. Extract information out of header */
> +		spl_image.size = __be32_to_cpu(header->ih_size);
> +		spl_image.entry_point = __be32_to_cpu(header->ih_load);
> +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
> +		spl_image.os = header->ih_os;
> +		spl_image.name = (const char *)&header->ih_name;
> +		spl_image.crc = __be32_to_cpu(header->ih_dcrc);
> +		debug("Subsequent boot image info\n");
> +		debug("   Image Name:   %.*s\n", IH_NMLEN, spl_image.name);
> +		debug("   Data Size:    %d\n", spl_image.size);
> +		debug("   Load Address: 0x%x\n", spl_image.load_addr);
> +		debug("   Entry Point:  0x%X\n", spl_image.entry_point);
> +	} else {
> +		/* Not a valid image as mkimage signature not found */
> +		printf("Error : mkimage signature not found - ih_magic = %x\n",
> +			header->ih_magic);
> +		return 1;
> +	}
> +
> +	/* Checking image type. Do any customize stuff per image type here */
> +	switch (spl_image.os) {
> +	case IH_OS_U_BOOT:
> +		debug("   Image Type:   U-Boot\n");
> +		break;
> +	default:
> +		printf("   Image Type:   Unknown (%d)\n", spl_image.os);
> +		;
> +	}
> +	return 0;
> +}

I think I don't even wanna know what's the purpose here :-)

[...]

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On Thu, Aug 23, 2012 at 12:26:53AM +0200, Marek Vasut wrote:
> Dear dinguyen at altera.com,
> 
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Signed-off-by: Pavel Machek <pavel@denx.de>
> 
> [...]
> 
> Please CC albert with new arches.
> 
> > diff --git a/Makefile b/Makefile
> > index 5ce5cc3..12aa372 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -369,7 +369,7 @@ BOARD_SIZE_CHECK =
> >  endif
> > 
> >  # Always append ALL so that arch config.mk's can add custom ones
> > -ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
> > +ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)u-boot.img
> > $(obj)System.map
> 
> This won't slide

You can place this into arch/arm/cpu/armv7/socfpga/config.mk (see
am33xx/config.mk or any of the others) for examples.

[snip]
> > diff --git a/arch/arm/cpu/armv7/socfpga/spl.c
> > b/arch/arm/cpu/armv7/socfpga/spl.c new file mode 100644
> > index 0000000..7bd1e2f
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/socfpga/spl.c
> > @@ -0,0 +1,182 @@
> > + /*
> > + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/u-boot.h>
> > +#include <asm/utils.h>
> > +#include <asm/arch/socfpga_spl.h>
> > +#include <version.h>
> > +#include <image.h>
> > +#include <malloc.h>
> > +#include <asm/arch/reset_manager.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static u32 *boot_params_ptr;
> > +static struct spl_image_info spl_image;
> > +
> > +extern void __malloc_start, __malloc_end, __stack_start;
> > +
> > +/* Define global data structure pointer to it */
> > +static gd_t gdata __attribute__ ((section(".data")));
> > +
> > +/*
> > + * Error action
> > + */
> > +inline void hang(void)
> > +{
> > +	puts("### ERROR ### Please RESET the board ###\n");
> > +	for (;;)
> > +		;
> > +}
> > +
> > +/*
> > + * Read the mkimage signature to extract info such as entry point.
> > + * The header is generated by tools/mkimage
> > + */
> > +static unsigned long spl_parse_image_header(const struct image_header
> > *header) +{
> > +	/* checking for mkimage signature */
> > +	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
> > +		/* Valid image. Extract information out of header */
> > +		spl_image.size = __be32_to_cpu(header->ih_size);
> > +		spl_image.entry_point = __be32_to_cpu(header->ih_load);
> > +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
> > +		spl_image.os = header->ih_os;
> > +		spl_image.name = (const char *)&header->ih_name;
> > +		spl_image.crc = __be32_to_cpu(header->ih_dcrc);
> > +		debug("Subsequent boot image info\n");
> > +		debug("   Image Name:   %.*s\n", IH_NMLEN, spl_image.name);
> > +		debug("   Data Size:    %d\n", spl_image.size);
> > +		debug("   Load Address: 0x%x\n", spl_image.load_addr);
> > +		debug("   Entry Point:  0x%X\n", spl_image.entry_point);
> > +	} else {
> > +		/* Not a valid image as mkimage signature not found */
> > +		printf("Error : mkimage signature not found - ih_magic = %x\n",
> > +			header->ih_magic);
> > +		return 1;
> > +	}
> > +
> > +	/* Checking image type. Do any customize stuff per image type here */
> > +	switch (spl_image.os) {
> > +	case IH_OS_U_BOOT:
> > +		debug("   Image Type:   U-Boot\n");
> > +		break;
> > +	default:
> > +		printf("   Image Type:   Unknown (%d)\n", spl_image.os);
> > +		;
> > +	}
> > +	return 0;
> > +}
> 
> I think I don't even wanna know what's the purpose here :-)

It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
:)  Can you please re-do your series on top of the SPL series I just
posted that provides a common SPL framework?  Thanks!

-- 
Tom

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> > > diff --git a/Makefile b/Makefile
> > > index 5ce5cc3..12aa372 100644
> > > --- a/Makefile
> > > +++ b/Makefile
> > > @@ -369,7 +369,7 @@ BOARD_SIZE_CHECK =
> > >  endif
> > > 
> > >  # Always append ALL so that arch config.mk's can add custom ones
> > > -ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
> > > +ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)u-boot.img
> > > $(obj)System.map
> > 
> > This won't slide
> 
> You can place this into arch/arm/cpu/armv7/socfpga/config.mk (see
> am33xx/config.mk or any of the others) for examples.

Thanks.

> > > +static unsigned long spl_parse_image_header(const struct image_header
> > > *header) +{
> > > +	/* checking for mkimage signature */
> > > +	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
> > > +		/* Valid image. Extract information out of header */
> > > +		spl_image.size = __be32_to_cpu(header->ih_size);
> > > +		spl_image.entry_point = __be32_to_cpu(header->ih_load);
> > > +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
> > > +		spl_image.os = header->ih_os;
> > > +		spl_image.name = (const char *)&header->ih_name;
> > > +		spl_image.crc = __be32_to_cpu(header->ih_dcrc);
> > > +		debug("Subsequent boot image info\n");
> > > +		debug("   Image Name:   %.*s\n", IH_NMLEN, spl_image.name);
> > > +		debug("   Data Size:    %d\n", spl_image.size);
> > > +		debug("   Load Address: 0x%x\n", spl_image.load_addr);
> > > +		debug("   Entry Point:  0x%X\n", spl_image.entry_point);
> > > +	} else {
> > > +		/* Not a valid image as mkimage signature not found */
> > > +		printf("Error : mkimage signature not found - ih_magic = %x\n",
> > > +			header->ih_magic);
> > > +		return 1;
> > > +	}
> > > +
> > > +	/* Checking image type. Do any customize stuff per image type here */
> > > +	switch (spl_image.os) {
> > > +	case IH_OS_U_BOOT:
> > > +		debug("   Image Type:   U-Boot\n");
> > > +		break;
> > > +	default:
> > > +		printf("   Image Type:   Unknown (%d)\n", spl_image.os);
> > > +		;
> > > +	}
> > > +	return 0;
> > > +}
> > 
> > I think I don't even wanna know what's the purpose here :-)
> 
> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
> :)  Can you please re-do your series on top of the SPL series I just
> posted that provides a common SPL framework?  Thanks!

I'll take a look. OTOH, ammount of code duplication here is quite low,
and redoing it on top of SPL series will mean delaying merge, right?
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Stefan Roese]

Hi Pavel,

On 08/23/2012 12:43 PM, Pavel Machek wrote:
>>>> +static unsigned long spl_parse_image_header(const struct image_header
>>>> *header) +{
>>>> +	/* checking for mkimage signature */
>>>> +	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
>>>> +		/* Valid image. Extract information out of header */
>>>> +		spl_image.size = __be32_to_cpu(header->ih_size);
>>>> +		spl_image.entry_point = __be32_to_cpu(header->ih_load);
>>>> +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
>>>> +		spl_image.os = header->ih_os;
>>>> +		spl_image.name = (const char *)&header->ih_name;
>>>> +		spl_image.crc = __be32_to_cpu(header->ih_dcrc);
>>>> +		debug("Subsequent boot image info\n");
>>>> +		debug("   Image Name:   %.*s\n", IH_NMLEN, spl_image.name);
>>>> +		debug("   Data Size:    %d\n", spl_image.size);
>>>> +		debug("   Load Address: 0x%x\n", spl_image.load_addr);
>>>> +		debug("   Entry Point:  0x%X\n", spl_image.entry_point);
>>>> +	} else {
>>>> +		/* Not a valid image as mkimage signature not found */
>>>> +		printf("Error : mkimage signature not found - ih_magic = %x\n",
>>>> +			header->ih_magic);
>>>> +		return 1;
>>>> +	}
>>>> +
>>>> +	/* Checking image type. Do any customize stuff per image type here */
>>>> +	switch (spl_image.os) {
>>>> +	case IH_OS_U_BOOT:
>>>> +		debug("   Image Type:   U-Boot\n");
>>>> +		break;
>>>> +	default:
>>>> +		printf("   Image Type:   Unknown (%d)\n", spl_image.os);
>>>> +		;
>>>> +	}
>>>> +	return 0;
>>>> +}
>>>
>>> I think I don't even wanna know what's the purpose here :-)
>>
>> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
>> :)  Can you please re-do your series on top of the SPL series I just
>> posted that provides a common SPL framework?  Thanks!
> 
> I'll take a look. OTOH, ammount of code duplication here is quite low,
> and redoing it on top of SPL series will mean delaying merge, right?

Yes, that might happen. But we learned in the past that if we don't try
to do such code consolidations right from the beginning, it won't happen
at all (most of the time). So I'm also in favor of using the common SPL
framework now. Please take a look at Tom Rini's v3 series:

http://www.mail-archive.com/u-boot at lists.denx.de/msg91405.html

I also based my powerpc SPL NOR flash booting series on it:

http://www.mail-archive.com/u-boot at lists.denx.de/msg91443.html

Thanks,
Stefan

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> > I'll take a look. OTOH, ammount of code duplication here is quite low,
> > and redoing it on top of SPL series will mean delaying merge, right?
> 
> Yes, that might happen. But we learned in the past that if we don't try
> to do such code consolidations right from the beginning, it won't happen
> at all (most of the time). So I'm also in favor of using the common SPL
> framework now. Please take a look at Tom Rini's v3 series:

No problem, it really looks much better on top of Tom's patches.

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Stefan Roese]

Hi Pavel,

On 08/29/2012 02:30 PM, Pavel Machek wrote:
> Hi!
> 
>>> I'll take a look. OTOH, ammount of code duplication here is quite low,
>>> and redoing it on top of SPL series will mean delaying merge, right?
>>
>> Yes, that might happen. But we learned in the past that if we don't try
>> to do such code consolidations right from the beginning, it won't happen
>> at all (most of the time). So I'm also in favor of using the common SPL
>> framework now. Please take a look at Tom Rini's v3 series:
> 
> No problem, it really looks much better on top of Tom's patches.

Great. Thanks for the extra work.

Cheers,
Stefan

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On 08/23/2012 03:43 AM, Pavel Machek wrote:

[snip]
>> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
>> :)  Can you please re-do your series on top of the SPL series I just
>> posted that provides a common SPL framework?  Thanks!
> 
> I'll take a look. OTOH, ammount of code duplication here is quite low,
> and redoing it on top of SPL series will mean delaying merge, right?

My hope is that since I got the SPL patches posted in time we can get
them in for v2012.10 so no, this will only help your chances :)

-- 
Tom

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> [snip]
> >> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
> >> :)  Can you please re-do your series on top of the SPL series I just
> >> posted that provides a common SPL framework?  Thanks!
> > 
> > I'll take a look. OTOH, ammount of code duplication here is quite low,
> > and redoing it on top of SPL series will mean delaying merge, right?
> 
> My hope is that since I got the SPL patches posted in time we can get
> them in for v2012.10 so no, this will only help your chances :)

Ok, but how do I get them applied?

I tried applying them over:

commit e66443fdb5355e68cfdbbdd37248c4b7eb4968f5
Author: Scott Wood <scottwood@freescale.com>
Date:   Tue Aug 14 01:44:29 2012 +0000

    Makefile: fix HAVE_VENDOR_COMMON_LIB
    
    Commit 8b5a02640adf77301f943e8754992c50df004e8a ("Makefile:
    cosmetic:
    optimize usage of LIBS-y") broke the build of boards that have a
    board
    vendor "common" directory, by introducing a space between "LIBS-"
    and
    "y".
    
    Signed-off-by: Scott Wood <scottwood@freescale.com>
    Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
    Acked-by: Kim Phillips <kim.phillips@freescale.com>

and am getting errors:

|index b314ed7..d8ade27 100644
|--- a/common/spl/spl.c
|+++ b/common/spl/spl.c
--------------------------
File to patch: ^C

Is there git to pull? One big patch for easier application?

Thanks,

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

On Fri 2012-08-24 12:18:27, Tom Rini wrote:
> On 08/23/2012 03:43 AM, Pavel Machek wrote:
> 
> [snip]
> >> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
> >> :)  Can you please re-do your series on top of the SPL series I just
> >> posted that provides a common SPL framework?  Thanks!
> > 
> > I'll take a look. OTOH, ammount of code duplication here is quite low,
> > and redoing it on top of SPL series will mean delaying merge, right?
> 
> My hope is that since I got the SPL patches posted in time we can get
> them in for v2012.10 so no, this will only help your chances :)

Got it. I pulled Stefan's version -- he seems to have your changes as
a git tree. I merged altera code into that, and with these quick hacks
on top of that, it boots. Good sign :-).

diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 7bd1e2f..74ac8e6 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -33,7 +33,7 @@ static struct spl_image_info spl_image;
 extern void __malloc_start, __malloc_end, __stack_start;
 
 /* Define global data structure pointer to it */
-static gd_t gdata __attribute__ ((section(".data")));
+gd_t gdata __attribute__ ((section(".data")));
 
 /*
  * Error action
@@ -134,27 +134,6 @@ static void spl_console_init(void)
 }
 
 /*
- * Board initialization prior bss clearance
- * Do note below concerns when inserting your function here.
- * Please refer to README for more details.
-
- * Initialized global data (data segment) is read-only. Do not attempt
-	to write it.
-
- * Do not use any uninitialized global data (or implicitely initialized
-	as zero data - BSS segment) at all - this is undefined, initiali-
-	zation is performed later (when relocating to RAM).
-
- * Stack space is very limited. Avoid big data buffers or things like
-	that.
- */
-void board_init_f(ulong dummy)
-{
-	/* Will clear bss then jump back to function board_init_r */
-	relocate_code((ulong) &__stack_start, &gdata, CONFIG_SPL_TEXT_BASE);
-}
-
-/*
  * Board initialization after bss clearance
  */
 void board_init_r(gd_t *id, ulong dummy)
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index c892f82..9db93d8 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -45,7 +45,7 @@ COBJS-y	+= reset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
 else
-COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
+COBJS-y += spl.o
 endif
 
 COBJS-y	+= cache.o
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index 2d1f47a..8c8806e 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -41,8 +41,9 @@ extern char __bss_start[], __bss_end__[];
  */
 void __weak board_init_f(ulong dummy)
 {
+  extern void __stack_start;
 	/* Set the stack pointer. */
-	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+	asm volatile("mov sp, %0\n" : : "r"(&__stack_start));
 
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end__ - __bss_start);
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 29aa9da..ac52e57 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -109,6 +109,7 @@
 #define CONFIG_DOS_PARTITION            1
 
 #ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_FRAMEWORK
 #undef CONFIG_PARTITIONS
 #endif
 


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> [snip]
> >> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
> >> :)  Can you please re-do your series on top of the SPL series I just
> >> posted that provides a common SPL framework?  Thanks!
> > 
> > I'll take a look. OTOH, ammount of code duplication here is quite low,
> > and redoing it on top of SPL series will mean delaying merge, right?
> 
> My hope is that since I got the SPL patches posted in time we can get
> them in for v2012.10 so no, this will only help your chances :)

Hopefully.

Some observations:

Not sure what to do with CONFIG_SPL_STACK: altera was just using
symbol from linker script. Is there way to keep it like that? I'd hate
to invent magic constant.

Same issue with CONFIG_SYS_SPL_MALLOC_START... I was doing:

        /* setup MALLOC after clocks going faster */
	mem_malloc_init((ulong) &__malloc_start,
					(&__malloc_end -
	&__malloc_start));

I guess defines allow me to keep my definition. Good.

spl_parse_image_header(): We have "modern" system, we'd prefer not to
do
                /* Signature not found - assume u-boot.bin */
...but to hang in that case, in order not to jump to random code.

Ok, I should have something publishable, soon ;-).
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On 08/25/2012 04:56 AM, Pavel Machek wrote:
> Hi!
> 
>> [snip]
>>>> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
>>>> :)  Can you please re-do your series on top of the SPL series I just
>>>> posted that provides a common SPL framework?  Thanks!
>>>
>>> I'll take a look. OTOH, ammount of code duplication here is quite low,
>>> and redoing it on top of SPL series will mean delaying merge, right?
>>
>> My hope is that since I got the SPL patches posted in time we can get
>> them in for v2012.10 so no, this will only help your chances :)
> 
> Hopefully.
> 
> Some observations:
> 
> Not sure what to do with CONFIG_SPL_STACK: altera was just using
> symbol from linker script. Is there way to keep it like that? I'd hate
> to invent magic constant.

Well, lets think about this.  Previously, everyone has been saying "use
this spot in SRAM" or "use this spot in DRAM (which has been setup
previously)".  But I think you should be able to do
#define CONFIG_SPL_STACK __linker_symbol and be done with it.

> Same issue with CONFIG_SYS_SPL_MALLOC_START... I was doing:
> 
>         /* setup MALLOC after clocks going faster */
> 	mem_malloc_init((ulong) &__malloc_start,
> 					(&__malloc_end -
> 	&__malloc_start));
> 
> I guess defines allow me to keep my definition. Good.

Should be fine, yes.

> spl_parse_image_header(): We have "modern" system, we'd prefer not to
> do
>                 /* Signature not found - assume u-boot.bin */
> ...but to hang in that case, in order not to jump to random code.
> 
> Ok, I should have something publishable, soon ;-).

The only reason I like the assumption idea is that I've already seen at
least one distribution ship new MLO (based on SPL) and u-boot.bin rather
than u-boot.img for their beagleboard images.

-- 
Tom

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> > Some observations:
> > 
> > Not sure what to do with CONFIG_SPL_STACK: altera was just using
> > symbol from linker script. Is there way to keep it like that? I'd hate
> > to invent magic constant.
> 
> Well, lets think about this.  Previously, everyone has been saying "use
> this spot in SRAM" or "use this spot in DRAM (which has been setup
> previously)".  But I think you should be able to do
> #define CONFIG_SPL_STACK __linker_symbol and be done with it.

Yes, that seems to do the trick... if it is acceptable.

									Pavel

commit 2cc99bcf39dc90ec4f43b949b8db75d5b019c92f
Author: Pavel <pavel@ucw.cz>
Date:   Wed Aug 29 14:04:47 2012 +0200

    Use CONFIG_SPL_START as suggested by Tom Rini.
    
    Signed-off-by: Pavel Machek <pavel@denx.de>

diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index ca5f4cf..88f809d 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -27,8 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void __malloc_start, __malloc_end, __stack_start;
-
 /*
  * Console Initialization
  */
diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h
index 68ceec6..43efa67 100644
--- a/arch/arm/include/asm/arch-socfpga/spl.h
+++ b/arch/arm/include/asm/arch-socfpga/spl.h
@@ -1 +1,28 @@
+/*
+ *  Copyright (C) 2012 Pavel Machek <pavel@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_SPL_H_
+#define _SOCFPGA_SPL_H_
+
+/* Symbols from linker script */
+extern void __malloc_start, __malloc_end, __stack_start;
+
+#define CONFIG_SPL_STACK (&__stack_start)
+
 #define BOOT_DEVICE_RAM 1
+
+#endif
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index 8c8806e..2d1f47a 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -41,9 +41,8 @@ extern char __bss_start[], __bss_end__[];
  */
 void __weak board_init_f(ulong dummy)
 {
-  extern void __stack_start;
 	/* Set the stack pointer. */
-	asm volatile("mov sp, %0\n" : : "r"(&__stack_start));
+	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
 
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end__ - __bss_start);

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> [snip]
> >> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
> >> :)  Can you please re-do your series on top of the SPL series I just
> >> posted that provides a common SPL framework?  Thanks!
> > 
> > I'll take a look. OTOH, ammount of code duplication here is quite low,
> > and redoing it on top of SPL series will mean delaying merge, right?
> 
> My hope is that since I got the SPL patches posted in time we can get
> them in for v2012.10 so no, this will only help your chances :)

Ok, this is promissed patch for comments. socfpga spl.c now got
reasonably smaller. It is on top of 

http://github.com/trini/u-boot WIP/spl-improvements

Now... can I leave spl_ram_load_image() where it is? Probably add some
#ifdef?

Dinh, does this look acceptable to you? Could we switch to absolute
addresses for stack/heap in the SPL?

Thanks,

								Pavel

diff --git a/MAINTAINERS b/MAINTAINERS
index c5a6f2f..df48dea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -765,6 +765,11 @@ Nagendra T S  <nagendra@mistralsolutions.com>
 
    am3517_crane    ARM ARMV7 (AM35x SoC)
 
+Dinh Nguyen <dinguyen@altera.com>
+Chin Liang See <clsee@altera.com>
+
+	socfpga		socfpga_cyclone5
+
 Kyungmin Park <kyungmin.park@samsung.com>
 
 	apollon		ARM1136EJS
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
new file mode 100644
index 0000000..376a4bd
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2012 Altera Corporation <www.altera.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	:= lowlevel_init.o
+COBJS-y	:= misc.o timer.o
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk
new file mode 100644
index 0000000..b72ed1e
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/config.mk
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+ifndef CONFIG_SPL_BUILD
+ALL-y	+= $(obj)u-boot.img
+endif
diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
new file mode 100644
index 0000000..815073e
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
@@ -0,0 +1,79 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Save the parameter pass in by previous boot loader */
+.global save_boot_params
+save_boot_params:
+	/* save the parameter here */
+
+	/*
+	 * Setup stack for exception, which is located
+	 * at the end of on-chip RAM. We don't expect exception prior to
+	 * relocation and if that happens, we won't worry -- it will overide
+	 * global data region as the code will goto reset. After relocation,
+	 * this region won't be used by other part of program.
+	 * Hence it is safe.
+	 */
+	ldr	r0, =CONFIG_SYS_INIT_RAM_ADDR
+	ldr	r1, =CONFIG_SYS_INIT_RAM_SIZE
+	add	r0, r0, r1
+	ldr	r1, =IRQ_STACK_START_IN
+	str	r0, [r1]
+
+	bx	lr
+
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Remap */
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * SPL : configure the remap (L3 NIC-301 GPV)
+	 * so the on-chip RAM at lower memory instead ROM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x19
+	str	r1, [r0]
+#else
+	/*
+	 * U-Boot : configure the remap (L3 NIC-301 GPV)
+	 * so the SDRAM at lower memory instead on-chip RAM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x2
+	str	r1, [r0]
+
+	/* Private components security */
+
+	/*
+	 * U-Boot : configure private timer, global timer and cpu
+	 * component access as non secure for kernel stage (as required
+	 * by kernel)
+	 */
+	mrc	p15,4,r0,c15,c0,0
+	add	r1, r0, #0x54
+	ldr	r2, [r1]
+	orr	r2, r2, #0xff
+	orr	r2, r2, #0xf00
+	str	r2, [r1]
+#endif	/* #ifdef CONFIG_SPL_BUILD */
+	mov	pc, lr
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
new file mode 100644
index 0000000..b906701
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -0,0 +1,54 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+	/* request a warm reset */
+	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
+	/* 
+	 * infinite loop here as watchdog will trigger and reset
+	 * the processor 
+	 */
+	while (1)
+		;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+	writel(0, &reset_manager_base->per_mod_reset);
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
new file mode 100644
index 0000000..ca5f4cf
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -0,0 +1,69 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <version.h>
+#include <image.h>
+#include <malloc.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void __malloc_start, __malloc_end, __stack_start;
+
+/*
+ * Console Initialization
+ */
+static void spl_console_init(void)
+{
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+
+	/* serial communications setup */
+	serial_init();
+	gd->have_console = 1;
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_RAM;
+}
+
+/*
+ * Board initialization after bss clearance
+ */
+void spl_board_init(void)
+{
+	/* init timer for enabling delay function */
+	timer_init();
+
+	/* de-assert reset for peripherals and bridges based on handoff */
+	reset_deassert_peripherals_handoff();
+
+	/* enable console uart printing */
+	spl_console_init();
+
+	/* setup MALLOC after clocks going faster */
+	mem_malloc_init((ulong) &__malloc_start,
+			(&__malloc_end - &__malloc_start));
+
+	puts("SPL Boot\n");
+}
diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
new file mode 100644
index 0000000..28da4d0
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/timer.c
@@ -0,0 +1,149 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+
+/*
+ * Timer initialization
+ */
+int timer_init(void)
+{
+	writel(TIMER_LOAD_VAL, &timer_base->load_val);
+	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
+	writel((readl((&timer_base->ctrl)) | 0x3),
+		(&timer_base->ctrl));
+	return 0;
+}
+
+static u32 read_timer(void)
+{
+	return readl(&timer_base->curr_val);
+}
+
+/*
+ * Delay x useconds
+ */
+void __udelay(unsigned long usec)
+{
+	unsigned long now, last;
+	/*
+	 * get the tmo value based on timer clock speed
+	 * tmo = delay required / period of timer clock
+	 */
+	long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000;
+
+	last = read_timer();
+	while (tmo > 0) {
+		now = read_timer();
+		if (last >= now)
+			/* normal mode (non roll) */
+			tmo -= last - now;
+		else
+			/* we have overflow of the count down timer */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		last = now;
+	}
+}
+
+/*
+ * Get the timer value
+ */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * Timer : get the time difference
+ * Unit of tick is based on the CONFIG_SYS_HZ
+ */
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+	if (gd->lastinc >= now) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* we have overflow of the count down timer */
+		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+	}
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+/*
+ * Reset the timer
+ */
+void reset_timer(void)
+{
+	/* capture current decrementer value time */
+	gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+	/* start "advancing" time stamp from 0 */
+	gd->tbl = 0;
+}
+
+/*
+ * Delay function in number of clocks (not in time unit).
+ *
+ * Below is an example of use case:
+ * > reset_timer_count();
+ * > start = get_timer_count (0);
+ * > while (get_timer (start) < num_count) {...}
+ */
+
+/*
+ * Get the timer count value
+ */
+ulong get_timer_count_masked(void)
+{
+	/* current tick value */
+	ulong now = read_timer();
+	if (gd->lastinc >= now) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* we have overflow of the count down timer */
+		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+	}
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+ulong get_timer_count(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * Reset the timer
+ */
+void reset_timer_count(void)
+{
+	/* capture current decrementer value time */
+	gd->lastinc = read_timer();
+	/* start "advancing" time stamp from 0 */
+	gd->tbl = 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
new file mode 100644
index 0000000..de74341
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) }
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss : {
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+	. = . + 4;
+	. = ALIGN(8);
+	__malloc_start = .;
+	. = . + CONFIG_SPL_MALLOC_SIZE;
+	__malloc_end = .;
+
+	. = . + 4;
+	. = . + CONFIG_SPL_STACK_SIZE;
+	. = ALIGN(8);
+	__stack_start = .;
+}
diff --git a/arch/arm/include/asm/arch-socfpga/reset_config.h b/arch/arm/include/asm/arch-socfpga/reset_config.h
new file mode 100644
index 0000000..e69de29
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
new file mode 100644
index 0000000..d9d2c1c
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_RESET_MANAGER_H_
+#define	_RESET_MANAGER_H_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+	u32	padding1;
+	u32	ctrl;
+	u32	padding2;
+	u32	padding3;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+};
+
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+
+#endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
new file mode 100644
index 0000000..f353eb2
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h
new file mode 100644
index 0000000..68ceec6
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/spl.h
@@ -0,0 +1 @@
+#define BOOT_DEVICE_RAM 1
diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/include/asm/arch-socfpga/timer.h
new file mode 100644
index 0000000..830c94a
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/timer.h
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_TIMER_H_
+#define _SOCFPGA_TIMER_H_
+
+struct socfpga_timer {
+	u32	load_val;
+	u32	curr_val;
+	u32	ctrl;
+	u32	eoi;
+	u32	int_stat;
+};
+
+#endif
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index 2d1f47a..8c8806e 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -41,8 +41,9 @@ extern char __bss_start[], __bss_end__[];
  */
 void __weak board_init_f(ulong dummy)
 {
+  extern void __stack_start;
 	/* Set the stack pointer. */
-	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+	asm volatile("mov sp, %0\n" : : "r"(&__stack_start));
 
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end__ - __bss_start);
diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile
new file mode 100644
index 0000000..43bbc37
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= socfpga_cyclone5.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
new file mode 100644
index 0000000..1248e3d
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
@@ -0,0 +1,97 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void show_boot_progress(int progress)
+{
+	debug("Boot reached stage %d\n", progress);
+}
+
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	puts("CPU   : Altera SOCFPGA Platform\n");
+	return 0;
+}
+
+/*
+ * Print Board information
+ */
+int checkboard(void)
+{
+	puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
+	return 0;
+}
+
+/*
+ * Initialization function which happen at early stage of c code
+ */
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	icache_enable();
+	return 0;
+}
+
+/*
+ * miscellaneous platform dependent initialisations
+ */
+int misc_init_r(void)
+{
+	/* Set to "n" for not verifying the uImage */
+	setenv("verify", "n");
+	return 0;
+}
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	return 0;
+}
+#endif
+
+/*
+ * DesignWare Ethernet initialization
+ */
+/* We know all the init functions have been run now */
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..1b5c860 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -261,6 +261,7 @@ seaboard                     arm         armv7       seaboard            nvidia
 ventana                      arm         armv7       ventana             nvidia         tegra2
 whistler                     arm         armv7       whistler            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
+socfpga_cyclone5              arm         armv7      socfpga_cyclone5    altera		    socfpga
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
diff --git a/common/spl/spl.c b/common/spl/spl.c
index eaea1c8..b87df65 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -78,6 +78,7 @@ void spl_parse_image_header(const struct image_header *header)
 	u32 header_size = sizeof(struct image_header);
 
 	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
+		/* Valid image. Extract information out of header */
 		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
 		spl_image.entry_point = __be32_to_cpu(header->ih_load);
 		/* Load including the header */
@@ -115,6 +116,21 @@ static void __noreturn jump_to_image_no_args(void)
 	image_entry((u32 *)boot_params_ptr_addr);
 }
 
+static void spl_ram_load_image(void)
+{
+	u32 err;
+	const struct image_header *header;
+
+	/* get the header */
+	/* it will point to a address defined by handoff which
+	will tell where the image located inside the flash. For now,
+	it will temporary fixed to address pointed by U-Boot */
+	header = (struct image_header *)
+		(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+
+	spl_parse_image_header(header);
+}
+
 void board_init_r(gd_t *dummy1, ulong dummy2)
 {
 	u32 boot_device;
@@ -132,6 +148,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	boot_device = spl_boot_device();
 	debug("boot device - %d\n", boot_device);
 	switch (boot_device) {
+	case BOOT_DEVICE_RAM:
+		spl_ram_load_image();
+		break;
 #ifdef CONFIG_SPL_MMC_SUPPORT
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
diff --git a/include/common.h b/include/common.h
index 55025c0..469a3af 100644
--- a/include/common.h
+++ b/include/common.h
@@ -704,7 +704,9 @@ void	external_interrupt (struct pt_regs *);
 void	irq_install_handler(int, interrupt_handler_t *, void *);
 void	irq_free_handler   (int);
 void	reset_timer	   (void);
-ulong	get_timer	   (ulong base);
+ulong	get_timer(ulong base);
+void	reset_timer_count(void);
+ulong	get_timer_count(ulong base);
 void	enable_interrupts  (void);
 int	disable_interrupts (void);
 
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
new file mode 100644
index 0000000..d001cbb
--- /dev/null
+++ b/include/configs/socfpga_cyclone5.h
@@ -0,0 +1,242 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/socfpga_base_addrs.h>
+
+/*
+ * High level configuration
+ */
+
+#define CONFIG_ARMV7
+#define CONFIG_L2_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SINGLE_BOOTLOADER
+#define CONFIG_SOCFPGA
+
+#define CONFIG_SYS_TEXT_BASE		0x08000040
+#define V_NS16550_CLK			1000000
+#define CONFIG_BAUDRATE			57600
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_TIMER_CLOCK_KHZ		2400
+#define CONFIG_SYS_LOAD_ADDR		0x7fc0
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"SOCFPGA_CYCLONE5 # "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Enable early stage initialization at C environment
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* flat device tree */
+#define CONFIG_OF_LIBFDT
+/* skip updating the FDT blob */
+#define CONFIG_FDT_BLOB_SKIP_UPDATE
+/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
+#define CONFIG_SYS_BOOTMAPSZ		((256*1024*1024) - (4*1024))
+
+/*
+ * Memory allocation (MALLOC)
+ */
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE			1024
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+/* regular stack */
+#define CONFIG_STACKSIZE		(128 << 10)
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack */
+#define CONFIG_STACKSIZE_IRQ		(4 << 10)
+/* FIQ stack */
+#define CONFIG_STACKSIZE_FIQ		(4 << 10)
+#endif
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+/* Reserving 0x100 space at back of scratch RAM for debug info */
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
+/* Stack pointer prior relocation, must situated@on-chip RAM */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+/* FAT file system support */
+#define CONFIG_CMD_FAT
+
+
+/*
+ * Misc
+ */
+#define CONFIG_DOS_PARTITION            1
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+/*
+ * Environment setup
+ */
+
+/* Delay before automatically booting the default image */
+#define CONFIG_BOOTDELAY		3
+/* Enable auto completion of commands using TAB */
+#define CONFIG_AUTO_COMPLETE
+/* use "hush" command parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMD_RUN
+
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+/*
+ * arguments passed to the bootm command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M at 0x0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=uImage\0" \
+	"fdt_addr=100\0" \
+	"fsloadcmd=ext2load\0" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* using environment setting for stdin, stdout, stderr */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* Enable the call to overwrite_console() */
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+/* Enable overwrite of previous console environment settings */
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* max number of command args	 */
+#define CONFIG_SYS_MAXARGS		16
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * SDRAM Memory Map
+ */
+/* We have 1 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+/* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+/* SDRAM memory size */
+#define PHYS_SDRAM_1_SIZE		0x80000000
+
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
+
+/*
+ * NS16550 Configuration
+ */
+#define UART0_BASE			SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
+#define CONFIG_CONS_INDEX               1
+#define CONFIG_SYS_NS16550_COM1		UART0_BASE
+
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * FLASH
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/*
+ * SPL "Second Program Loader" aka Initial Software
+ */
+
+/* Enable building of SPL globally */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+
+/* TEXT_BASE for linking the SPL binary */
+#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
+
+/* Stack size for SPL */
+#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
+
+/* MALLOC size for SPL */
+#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)
+
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#define CHUNKSZ_CRC32			(1 * 1024)
+
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+/* Support for common/libcommon.o in SPL binary */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+/* Support for lib/libgeneric.o in SPL binary */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#endif	/* __CONFIG_H */
diff --git a/spl/Makefile b/spl/Makefile
index f96c08e4..d757448 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -58,6 +58,7 @@ LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
 LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
 LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
 LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o
+LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
 
 ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On 08/25/2012 05:05 AM, Pavel Machek wrote:
> Hi!
> 
>> [snip]
>>>> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
>>>> :)  Can you please re-do your series on top of the SPL series I just
>>>> posted that provides a common SPL framework?  Thanks!
>>>
>>> I'll take a look. OTOH, ammount of code duplication here is quite low,
>>> and redoing it on top of SPL series will mean delaying merge, right?
>>
>> My hope is that since I got the SPL patches posted in time we can get
>> them in for v2012.10 so no, this will only help your chances :)
> 
> Ok, this is promissed patch for comments. socfpga spl.c now got
> reasonably smaller. It is on top of 

Looks good overall.  I don't see asm/arch/spl.h but that's where you
could put the extern for __stack_start and then define CONFIG_SPL_STACK
to &__stack_start.

> http://github.com/trini/u-boot WIP/spl-improvements
> 
> Now... can I leave spl_ram_load_image() where it is? Probably add some
> #ifdef?

Yeah, I think that's OK to start with, we can move things more later if
needed.

> 
> Dinh, does this look acceptable to you? Could we switch to absolute
> addresses for stack/heap in the SPL?
[snip]
> +/*
> + * Console Initialization
> + */
> +static void spl_console_init(void)
> +{
> +	gd->flags |= GD_FLG_RELOC;
> +	gd->baudrate = CONFIG_BAUDRATE;
> +
> +	/* serial communications setup */
> +	serial_init();
> +	gd->have_console = 1;
> +}

Looks like preloader_console_init :)

> +
> +u32 spl_boot_device(void)
> +{
> +	return BOOT_DEVICE_RAM;
> +}
> +
> +/*
> + * Board initialization after bss clearance
> + */
> +void spl_board_init(void)
> +{
> +	/* init timer for enabling delay function */
> +	timer_init();
> +
> +	/* de-assert reset for peripherals and bridges based on handoff */
> +	reset_deassert_peripherals_handoff();
> +
> +	/* enable console uart printing */
> +	spl_console_init();
> +
> +	/* setup MALLOC after clocks going faster */
> +	mem_malloc_init((ulong) &__malloc_start,
> +			(&__malloc_end - &__malloc_start));

Shouldn't need this, should already be called before you get to
spl_board_init.

[snip]
> diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds

You should setup MEMORY declarations like the other u-boot-spl linker
scripts do so we get build-time confirmation that we haven't exceeded
our size limitations.

> +	. = . + 4;
> +	. = ALIGN(8);
> +	__malloc_start = .;
> +	. = . + CONFIG_SPL_MALLOC_SIZE;
> +	__malloc_end = .;
> +
> +	. = . + 4;
> +	. = . + CONFIG_SPL_STACK_SIZE;
> +	. = ALIGN(8);
> +	__stack_start = .;

Do you really need to do . = . + 4 and then align statements?

[snip]
> diff --git a/spl/Makefile b/spl/Makefile
> index f96c08e4..d757448 100644
> --- a/spl/Makefile
> +++ b/spl/Makefile
> @@ -58,6 +58,7 @@ LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
>  LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
>  LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
>  LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o
> +LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
>  
>  ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
>  LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
> 

Er?  There's already a line for lib/libgeneric.o

> 

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> > Ok, this is promissed patch for comments. socfpga spl.c now got
> > reasonably smaller. It is on top of 
> 
> Looks good overall.  I don't see asm/arch/spl.h but that's where you
> could put the extern for __stack_start and then define CONFIG_SPL_STACK
> to &__stack_start.

Yep, that works, thanks!

> > http://github.com/trini/u-boot WIP/spl-improvements
> > 
> > Now... can I leave spl_ram_load_image() where it is? Probably add some
> > #ifdef?
> 
> Yeah, I think that's OK to start with, we can move things more later if
> needed.

Cool.

> > +static void spl_console_init(void)
> 
> Looks like preloader_console_init :)

And works the same, too. Shared. Thanks!

> > +	/* setup MALLOC after clocks going faster */
> > +	mem_malloc_init((ulong) &__malloc_start,
> > +			(&__malloc_end - &__malloc_start));
> 
> Shouldn't need this, should already be called before you get to
> spl_board_init.

Yep, I set up CONFIG_SYS_... and it seems to work.

> [snip]
> > diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
> 
> You should setup MEMORY declarations like the other u-boot-spl linker
> scripts do so we get build-time confirmation that we haven't exceeded
> our size limitations.

Ok, I'll do that as a next step.

> > +	. = . + 4;
> > +	. = ALIGN(8);
> > +	__malloc_start = .;
> > +	. = . + CONFIG_SPL_MALLOC_SIZE;
> > +	__malloc_end = .;
> > +
> > +	. = . + 4;
> > +	. = . + CONFIG_SPL_STACK_SIZE;
> > +	. = ALIGN(8);
> > +	__stack_start = .;
> 
> Do you really need to do . = . + 4 and then align statements?

Probably not. Removed.

> > +LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
> q
> Er?  There's already a line for lib/libgeneric.o

Sorry. Deleted.

Thanks,
									Pavel

diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index c12e339..bf03333 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -46,9 +46,5 @@ void spl_board_init(void)
 	/* enable console uart printing */
 	preloader_console_init();
 
-	/* setup MALLOC after clocks going faster */
-	mem_malloc_init((ulong) &__malloc_start,
-			(&__malloc_end - &__malloc_start));
-
 	puts("SPL Boot\n");
 }
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
index de74341..2c90753 100644
--- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -47,13 +47,11 @@ SECTIONS
 		__bss_end__ = .;
 	}
 
-	. = . + 4;
 	. = ALIGN(8);
 	__malloc_start = .;
 	. = . + CONFIG_SPL_MALLOC_SIZE;
 	__malloc_end = .;
 
-	. = . + 4;
 	. = . + CONFIG_SPL_STACK_SIZE;
 	. = ALIGN(8);
 	__stack_start = .;
diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h
index 43efa67..c9e5f50 100644
--- a/arch/arm/include/asm/arch-socfpga/spl.h
+++ b/arch/arm/include/asm/arch-socfpga/spl.h
@@ -22,6 +22,8 @@
 extern void __malloc_start, __malloc_end, __stack_start;
 
 #define CONFIG_SPL_STACK (&__stack_start)
+#define CONFIG_SYS_SPL_MALLOC_START (&__malloc_start)
+#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
 
 #define BOOT_DEVICE_RAM 1
 
diff --git a/common/spl/spl.c b/common/spl/spl.c
index b87df65..5adbf0e 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -118,7 +118,6 @@ static void __noreturn jump_to_image_no_args(void)
 
 static void spl_ram_load_image(void)
 {
-	u32 err;
 	const struct image_header *header;
 
 	/* get the header */
diff --git a/spl/Makefile b/spl/Makefile
index d757448..f96c08e4 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -58,7 +58,6 @@ LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
 LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
 LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
 LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o
-LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
 
 ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> > diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
> 
> You should setup MEMORY declarations like the other u-boot-spl linker
> scripts do so we get build-time confirmation that we haven't exceeded
> our size limitations.

Hmm, I tried, but I don't know socfpga memory layout by heart.

Dinh, can you help here?

Thanks,
								Pavel

diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
index 8867e06..1d8efb2 100644
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -37,9 +37,9 @@ SECTIONS
 {
 	.text      :
 	{
-	__start = .;
-	  arch/arm/cpu/armv7/start.o	(.text)
-	  *(.text*)
+		__start = .;
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
 	} >.sram
 
 	. = ALIGN(4);
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
index 2c90753..7cd409c 100644
--- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -15,6 +15,8 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) }
+
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 ENTRY(_start)
@@ -27,13 +29,13 @@ SECTIONS
 	{
 		arch/arm/cpu/armv7/start.o	(.text)
 		*(.text*)
-	}
+	} >.sdram
 
 	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram
 
 	. = ALIGN(4);
-	.data : { *(SORT_BY_ALIGNMENT(.data*)) }
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram
 
 	. = ALIGN(4);
 	__image_copy_end = .;
@@ -45,7 +47,7 @@ SECTIONS
 		*(.bss*)
 		. = ALIGN(4);
 		__bss_end__ = .;
-	}
+	} >.sdram
 
 	. = ALIGN(8);
 	__malloc_start = .;



-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On Wed, Aug 29, 2012 at 03:41:54PM +0200, Pavel Machek wrote:
> Hi!
> 
> > > diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
> > 
> > You should setup MEMORY declarations like the other u-boot-spl linker
> > scripts do so we get build-time confirmation that we haven't exceeded
> > our size limitations.
> 
> Hmm, I tried, but I don't know socfpga memory layout by heart.
> 
> Dinh, can you help here?

I think once you get the answers you should be able to re-post the
series cleanly and depend on my v5 (or v6) branch.  Thanks!

-- 
Tom

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> > > > diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
> > > 
> > > You should setup MEMORY declarations like the other u-boot-spl linker
> > > scripts do so we get build-time confirmation that we haven't exceeded
> > > our size limitations.
> > 
> > Hmm, I tried, but I don't know socfpga memory layout by heart.
> > 
> > Dinh, can you help here?
> 
> I think once you get the answers you should be able to re-post the
> series cleanly and depend on my v5 (or v6) branch.  Thanks!

Ok, figuring the .lds might be tricky. But... that's mostly additional
(safety) feature. Would it be possible to merge it without that and
add it later?

Port to v5 of the patch should not be a problem.

For the record and review, current version of patch is here.

									Pavel
diff --git a/MAINTAINERS b/MAINTAINERS
index c5a6f2f..df48dea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -765,6 +765,11 @@ Nagendra T S  <nagendra@mistralsolutions.com>
 
    am3517_crane    ARM ARMV7 (AM35x SoC)
 
+Dinh Nguyen <dinguyen@altera.com>
+Chin Liang See <clsee@altera.com>
+
+	socfpga		socfpga_cyclone5
+
 Kyungmin Park <kyungmin.park@samsung.com>
 
 	apollon		ARM1136EJS
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
new file mode 100644
index 0000000..376a4bd
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2012 Altera Corporation <www.altera.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	:= lowlevel_init.o
+COBJS-y	:= misc.o timer.o
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk
new file mode 100644
index 0000000..b72ed1e
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/config.mk
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+ifndef CONFIG_SPL_BUILD
+ALL-y	+= $(obj)u-boot.img
+endif
diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
new file mode 100644
index 0000000..815073e
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
@@ -0,0 +1,79 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Save the parameter pass in by previous boot loader */
+.global save_boot_params
+save_boot_params:
+	/* save the parameter here */
+
+	/*
+	 * Setup stack for exception, which is located
+	 * at the end of on-chip RAM. We don't expect exception prior to
+	 * relocation and if that happens, we won't worry -- it will overide
+	 * global data region as the code will goto reset. After relocation,
+	 * this region won't be used by other part of program.
+	 * Hence it is safe.
+	 */
+	ldr	r0, =CONFIG_SYS_INIT_RAM_ADDR
+	ldr	r1, =CONFIG_SYS_INIT_RAM_SIZE
+	add	r0, r0, r1
+	ldr	r1, =IRQ_STACK_START_IN
+	str	r0, [r1]
+
+	bx	lr
+
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Remap */
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * SPL : configure the remap (L3 NIC-301 GPV)
+	 * so the on-chip RAM at lower memory instead ROM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x19
+	str	r1, [r0]
+#else
+	/*
+	 * U-Boot : configure the remap (L3 NIC-301 GPV)
+	 * so the SDRAM at lower memory instead on-chip RAM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x2
+	str	r1, [r0]
+
+	/* Private components security */
+
+	/*
+	 * U-Boot : configure private timer, global timer and cpu
+	 * component access as non secure for kernel stage (as required
+	 * by kernel)
+	 */
+	mrc	p15,4,r0,c15,c0,0
+	add	r1, r0, #0x54
+	ldr	r2, [r1]
+	orr	r2, r2, #0xff
+	orr	r2, r2, #0xf00
+	str	r2, [r1]
+#endif	/* #ifdef CONFIG_SPL_BUILD */
+	mov	pc, lr
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
new file mode 100644
index 0000000..b906701
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -0,0 +1,54 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+	/* request a warm reset */
+	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
+	/* 
+	 * infinite loop here as watchdog will trigger and reset
+	 * the processor 
+	 */
+	while (1)
+		;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+	writel(0, &reset_manager_base->per_mod_reset);
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
new file mode 100644
index 0000000..bf03333
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <version.h>
+#include <image.h>
+#include <malloc.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_RAM;
+}
+
+/*
+ * Board initialization after bss clearance
+ */
+void spl_board_init(void)
+{
+	/* init timer for enabling delay function */
+	timer_init();
+
+	/* de-assert reset for peripherals and bridges based on handoff */
+	reset_deassert_peripherals_handoff();
+
+	/* enable console uart printing */
+	preloader_console_init();
+
+	puts("SPL Boot\n");
+}
diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
new file mode 100644
index 0000000..28da4d0
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/timer.c
@@ -0,0 +1,149 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+
+/*
+ * Timer initialization
+ */
+int timer_init(void)
+{
+	writel(TIMER_LOAD_VAL, &timer_base->load_val);
+	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
+	writel((readl((&timer_base->ctrl)) | 0x3),
+		(&timer_base->ctrl));
+	return 0;
+}
+
+static u32 read_timer(void)
+{
+	return readl(&timer_base->curr_val);
+}
+
+/*
+ * Delay x useconds
+ */
+void __udelay(unsigned long usec)
+{
+	unsigned long now, last;
+	/*
+	 * get the tmo value based on timer clock speed
+	 * tmo = delay required / period of timer clock
+	 */
+	long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000;
+
+	last = read_timer();
+	while (tmo > 0) {
+		now = read_timer();
+		if (last >= now)
+			/* normal mode (non roll) */
+			tmo -= last - now;
+		else
+			/* we have overflow of the count down timer */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		last = now;
+	}
+}
+
+/*
+ * Get the timer value
+ */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * Timer : get the time difference
+ * Unit of tick is based on the CONFIG_SYS_HZ
+ */
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+	if (gd->lastinc >= now) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* we have overflow of the count down timer */
+		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+	}
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+/*
+ * Reset the timer
+ */
+void reset_timer(void)
+{
+	/* capture current decrementer value time */
+	gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+	/* start "advancing" time stamp from 0 */
+	gd->tbl = 0;
+}
+
+/*
+ * Delay function in number of clocks (not in time unit).
+ *
+ * Below is an example of use case:
+ * > reset_timer_count();
+ * > start = get_timer_count (0);
+ * > while (get_timer (start) < num_count) {...}
+ */
+
+/*
+ * Get the timer count value
+ */
+ulong get_timer_count_masked(void)
+{
+	/* current tick value */
+	ulong now = read_timer();
+	if (gd->lastinc >= now) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* we have overflow of the count down timer */
+		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+	}
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+ulong get_timer_count(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * Reset the timer
+ */
+void reset_timer_count(void)
+{
+	/* capture current decrementer value time */
+	gd->lastinc = read_timer();
+	/* start "advancing" time stamp from 0 */
+	gd->tbl = 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
new file mode 100644
index 0000000..7cd409c
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
+	} >.sdram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss : {
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sdram
+
+	. = ALIGN(8);
+	__malloc_start = .;
+	. = . + CONFIG_SPL_MALLOC_SIZE;
+	__malloc_end = .;
+
+	. = . + CONFIG_SPL_STACK_SIZE;
+	. = ALIGN(8);
+	__stack_start = .;
+}
diff --git a/arch/arm/include/asm/arch-socfpga/reset_config.h b/arch/arm/include/asm/arch-socfpga/reset_config.h
new file mode 100644
index 0000000..e69de29
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
new file mode 100644
index 0000000..d9d2c1c
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_RESET_MANAGER_H_
+#define	_RESET_MANAGER_H_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+	u32	padding1;
+	u32	ctrl;
+	u32	padding2;
+	u32	padding3;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+};
+
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+
+#endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
new file mode 100644
index 0000000..f353eb2
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h
new file mode 100644
index 0000000..c9e5f50
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/spl.h
@@ -0,0 +1,30 @@
+/*
+ *  Copyright (C) 2012 Pavel Machek <pavel@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_SPL_H_
+#define _SOCFPGA_SPL_H_
+
+/* Symbols from linker script */
+extern void __malloc_start, __malloc_end, __stack_start;
+
+#define CONFIG_SPL_STACK (&__stack_start)
+#define CONFIG_SYS_SPL_MALLOC_START (&__malloc_start)
+#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
+
+#define BOOT_DEVICE_RAM 1
+
+#endif
diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/include/asm/arch-socfpga/timer.h
new file mode 100644
index 0000000..830c94a
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/timer.h
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_TIMER_H_
+#define _SOCFPGA_TIMER_H_
+
+struct socfpga_timer {
+	u32	load_val;
+	u32	curr_val;
+	u32	ctrl;
+	u32	eoi;
+	u32	int_stat;
+};
+
+#endif
diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile
new file mode 100644
index 0000000..43bbc37
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= socfpga_cyclone5.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
new file mode 100644
index 0000000..1248e3d
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
@@ -0,0 +1,97 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void show_boot_progress(int progress)
+{
+	debug("Boot reached stage %d\n", progress);
+}
+
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	puts("CPU   : Altera SOCFPGA Platform\n");
+	return 0;
+}
+
+/*
+ * Print Board information
+ */
+int checkboard(void)
+{
+	puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
+	return 0;
+}
+
+/*
+ * Initialization function which happen at early stage of c code
+ */
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	icache_enable();
+	return 0;
+}
+
+/*
+ * miscellaneous platform dependent initialisations
+ */
+int misc_init_r(void)
+{
+	/* Set to "n" for not verifying the uImage */
+	setenv("verify", "n");
+	return 0;
+}
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	return 0;
+}
+#endif
+
+/*
+ * DesignWare Ethernet initialization
+ */
+/* We know all the init functions have been run now */
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..1b5c860 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -261,6 +261,7 @@ seaboard                     arm         armv7       seaboard            nvidia
 ventana                      arm         armv7       ventana             nvidia         tegra2
 whistler                     arm         armv7       whistler            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
+socfpga_cyclone5              arm         armv7      socfpga_cyclone5    altera		    socfpga
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
diff --git a/common/spl/spl.c b/common/spl/spl.c
index eaea1c8..5adbf0e 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -78,6 +78,7 @@ void spl_parse_image_header(const struct image_header *header)
 	u32 header_size = sizeof(struct image_header);
 
 	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
+		/* Valid image. Extract information out of header */
 		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
 		spl_image.entry_point = __be32_to_cpu(header->ih_load);
 		/* Load including the header */
@@ -115,6 +116,20 @@ static void __noreturn jump_to_image_no_args(void)
 	image_entry((u32 *)boot_params_ptr_addr);
 }
 
+static void spl_ram_load_image(void)
+{
+	const struct image_header *header;
+
+	/* get the header */
+	/* it will point to a address defined by handoff which
+	will tell where the image located inside the flash. For now,
+	it will temporary fixed to address pointed by U-Boot */
+	header = (struct image_header *)
+		(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+
+	spl_parse_image_header(header);
+}
+
 void board_init_r(gd_t *dummy1, ulong dummy2)
 {
 	u32 boot_device;
@@ -132,6 +147,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	boot_device = spl_boot_device();
 	debug("boot device - %d\n", boot_device);
 	switch (boot_device) {
+	case BOOT_DEVICE_RAM:
+		spl_ram_load_image();
+		break;
 #ifdef CONFIG_SPL_MMC_SUPPORT
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
diff --git a/include/common.h b/include/common.h
index 55025c0..469a3af 100644
--- a/include/common.h
+++ b/include/common.h
@@ -704,7 +704,9 @@ void	external_interrupt (struct pt_regs *);
 void	irq_install_handler(int, interrupt_handler_t *, void *);
 void	irq_free_handler   (int);
 void	reset_timer	   (void);
-ulong	get_timer	   (ulong base);
+ulong	get_timer(ulong base);
+void	reset_timer_count(void);
+ulong	get_timer_count(ulong base);
 void	enable_interrupts  (void);
 int	disable_interrupts (void);
 
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
new file mode 100644
index 0000000..d001cbb
--- /dev/null
+++ b/include/configs/socfpga_cyclone5.h
@@ -0,0 +1,242 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/socfpga_base_addrs.h>
+
+/*
+ * High level configuration
+ */
+
+#define CONFIG_ARMV7
+#define CONFIG_L2_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SINGLE_BOOTLOADER
+#define CONFIG_SOCFPGA
+
+#define CONFIG_SYS_TEXT_BASE		0x08000040
+#define V_NS16550_CLK			1000000
+#define CONFIG_BAUDRATE			57600
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_TIMER_CLOCK_KHZ		2400
+#define CONFIG_SYS_LOAD_ADDR		0x7fc0
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"SOCFPGA_CYCLONE5 # "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Enable early stage initialization at C environment
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* flat device tree */
+#define CONFIG_OF_LIBFDT
+/* skip updating the FDT blob */
+#define CONFIG_FDT_BLOB_SKIP_UPDATE
+/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
+#define CONFIG_SYS_BOOTMAPSZ		((256*1024*1024) - (4*1024))
+
+/*
+ * Memory allocation (MALLOC)
+ */
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE			1024
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+/* regular stack */
+#define CONFIG_STACKSIZE		(128 << 10)
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack */
+#define CONFIG_STACKSIZE_IRQ		(4 << 10)
+/* FIQ stack */
+#define CONFIG_STACKSIZE_FIQ		(4 << 10)
+#endif
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+/* Reserving 0x100 space at back of scratch RAM for debug info */
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
+/* Stack pointer prior relocation, must situated@on-chip RAM */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+/* FAT file system support */
+#define CONFIG_CMD_FAT
+
+
+/*
+ * Misc
+ */
+#define CONFIG_DOS_PARTITION            1
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+/*
+ * Environment setup
+ */
+
+/* Delay before automatically booting the default image */
+#define CONFIG_BOOTDELAY		3
+/* Enable auto completion of commands using TAB */
+#define CONFIG_AUTO_COMPLETE
+/* use "hush" command parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMD_RUN
+
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+/*
+ * arguments passed to the bootm command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M at 0x0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=uImage\0" \
+	"fdt_addr=100\0" \
+	"fsloadcmd=ext2load\0" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* using environment setting for stdin, stdout, stderr */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* Enable the call to overwrite_console() */
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+/* Enable overwrite of previous console environment settings */
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* max number of command args	 */
+#define CONFIG_SYS_MAXARGS		16
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * SDRAM Memory Map
+ */
+/* We have 1 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+/* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+/* SDRAM memory size */
+#define PHYS_SDRAM_1_SIZE		0x80000000
+
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
+
+/*
+ * NS16550 Configuration
+ */
+#define UART0_BASE			SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
+#define CONFIG_CONS_INDEX               1
+#define CONFIG_SYS_NS16550_COM1		UART0_BASE
+
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * FLASH
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/*
+ * SPL "Second Program Loader" aka Initial Software
+ */
+
+/* Enable building of SPL globally */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+
+/* TEXT_BASE for linking the SPL binary */
+#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
+
+/* Stack size for SPL */
+#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
+
+/* MALLOC size for SPL */
+#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)
+
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#define CHUNKSZ_CRC32			(1 * 1024)
+
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+/* Support for common/libcommon.o in SPL binary */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+/* Support for lib/libgeneric.o in SPL binary */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#endif	/* __CONFIG_H */


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On 08/29/2012 04:21 PM, Pavel Machek wrote:
> Hi!
> 
>>>>> diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
>>>>
>>>> You should setup MEMORY declarations like the other u-boot-spl linker
>>>> scripts do so we get build-time confirmation that we haven't exceeded
>>>> our size limitations.
>>>
>>> Hmm, I tried, but I don't know socfpga memory layout by heart.
>>>
>>> Dinh, can you help here?
>>
>> I think once you get the answers you should be able to re-post the
>> series cleanly and depend on my v5 (or v6) branch.  Thanks!
> 
> Ok, figuring the .lds might be tricky. But... that's mostly additional
> (safety) feature. Would it be possible to merge it without that and
> add it later?
> 
> Port to v5 of the patch should not be a problem.
> 
> For the record and review, current version of patch is here.

A few small comments.  No need to re-post intermediate patches, just
address in the next full go-round.  Thanks!

> diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
[snip]
> +/*
> + * Board initialization after bss clearance
> + */
> +void spl_board_init(void)
[snip]
> +	puts("SPL Boot\n");

Sure you want to keep that line?  We already have a general "U-Boot SPL
..." line being printed.

[snip]
> diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h
[snip]
> +#define CONFIG_SPL_STACK (&__stack_start)
> +#define CONFIG_SYS_SPL_MALLOC_START (&__malloc_start)
> +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)

These should be in the config file.

> diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
[snip]
> +/*
> + * miscellaneous platform dependent initialisations
> + */
> +int misc_init_r(void)
> +{
> +	/* Set to "n" for not verifying the uImage */
> +	setenv("verify", "n");
> +	return 0;
> +}

Not good to enforce policy like this.  Just don't set it in the config
file by default and let users do as they need.

[snip]
> diff --git a/common/spl/spl.c b/common/spl/spl.c
> index eaea1c8..5adbf0e 100644
> --- a/common/spl/spl.c
> +++ b/common/spl/spl.c
> @@ -78,6 +78,7 @@ void spl_parse_image_header(const struct image_header *header)
>  	u32 header_size = sizeof(struct image_header);
>  
>  	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
> +		/* Valid image. Extract information out of header */
>  		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
>  		spl_image.entry_point = __be32_to_cpu(header->ih_load);
>  		/* Load including the header */

Just an extra comment, drop please.  Or split out if you feel it's
really helpful.  No strong opinion here other than not in the same patch
as the rest.

[snip]
> diff --git a/include/common.h b/include/common.h
> index 55025c0..469a3af 100644
> --- a/include/common.h
> +++ b/include/common.h
> @@ -704,7 +704,9 @@ void	external_interrupt (struct pt_regs *);
>  void	irq_install_handler(int, interrupt_handler_t *, void *);
>  void	irq_free_handler   (int);
>  void	reset_timer	   (void);
> -ulong	get_timer	   (ulong base);
> +ulong	get_timer(ulong base);
> +void	reset_timer_count(void);
> +ulong	get_timer_count(ulong base);
>  void	enable_interrupts  (void);
>  int	disable_interrupts (void);

Make the new declarations match the old, spacing wise please.

>  
> diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
> new file mode 100644
> index 0000000..d001cbb
> --- /dev/null
> +++ b/include/configs/socfpga_cyclone5.h
[snip]
> +#undef CONFIG_USE_IRQ
[snip]
> +
> +/*
> + * Stack sizes
> + * The stack sizes are set up in start.S using the settings below
> + */
> +/* regular stack */
> +#define CONFIG_STACKSIZE		(128 << 10)
> +#ifdef CONFIG_USE_IRQ
> +/* IRQ stack */
> +#define CONFIG_STACKSIZE_IRQ		(4 << 10)
> +/* FIQ stack */
> +#define CONFIG_STACKSIZE_FIQ		(4 << 10)
> +#endif

Unused, please drop.

[snip]
> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

This is the default now, can be dropped.

-- 
Tom

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> >> I think once you get the answers you should be able to re-post the
> >> series cleanly and depend on my v5 (or v6) branch.  Thanks!
> > 
> > Ok, figuring the .lds might be tricky. But... that's mostly additional
> > (safety) feature. Would it be possible to merge it without that and
> > add it later?
> > 
> > Port to v5 of the patch should not be a problem.
> > 
> > For the record and review, current version of patch is here.
> 
> A few small comments.  No need to re-post intermediate patches, just
> address in the next full go-round.  Thanks!

They were mostly for synchronization with Dinh. Sorry for the noise.

> > +void spl_board_init(void)
> [snip]
> > +	puts("SPL Boot\n");
> 
> Sure you want to keep that line?  We already have a general "U-Boot SPL
> ..." line being printed.

Killed.

> > + * miscellaneous platform dependent initialisations
> > + */
> > +int misc_init_r(void)
> > +{
> > +	/* Set to "n" for not verifying the uImage */
> > +	setenv("verify", "n");
> > +	return 0;
> > +}
> 
> Not good to enforce policy like this.  Just don't set it in the config
> file by default and let users do as they need.

Hmm. I moved it to CONFIG_EXTRA_ENV_SETTINGS as done by for eample
u8500_href.h. Is that ok?

> [snip]
> > diff --git a/common/spl/spl.c b/common/spl/spl.c
> > index eaea1c8..5adbf0e 100644
> > --- a/common/spl/spl.c
> > +++ b/common/spl/spl.c
> > @@ -78,6 +78,7 @@ void spl_parse_image_header(const struct image_header *header)
> >  	u32 header_size = sizeof(struct image_header);
> >  
> >  	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
> > +		/* Valid image. Extract information out of header */
> >  		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
> >  		spl_image.entry_point = __be32_to_cpu(header->ih_load);
> >  		/* Load including the header */
> 
> Just an extra comment, drop please.  Or split out if you feel it's
> really helpful.  No strong opinion here other than not in the same patch
> as the rest.

Ok, I'll drop it, and the omap cleanup also. Not worth the merge
effort.

spl_ram_load_image... will I need to create some kind of #ifdef? Or
would #ifdef BOOT_DEVICE_RAM do the trick?

> [snip]
> > diff --git a/include/common.h b/include/common.h
> > index 55025c0..469a3af 100644
> > --- a/include/common.h
> > +++ b/include/common.h
> > @@ -704,7 +704,9 @@ void	external_interrupt (struct pt_regs *);
> >  void	irq_install_handler(int, interrupt_handler_t *, void *);
> >  void	irq_free_handler   (int);
> >  void	reset_timer	   (void);
> > -ulong	get_timer	   (ulong base);
> > +ulong	get_timer(ulong base);
> > +void	reset_timer_count(void);
> > +ulong	get_timer_count(ulong base);
> >  void	enable_interrupts  (void);
> >  int	disable_interrupts (void);
> 
> Make the new declarations match the old, spacing wise please.

Ok, but checkpatch will complain. ... .... hmm. Why do I have feeling
that they are not needed at all? Removed, and things still work. Good.

Rest was fixed in obvious way. Thanks for comments!
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On 08/30/2012 10:18 AM, Pavel Machek wrote:

>>> + * miscellaneous platform dependent initialisations
>>> + */
>>> +int misc_init_r(void)
>>> +{
>>> +	/* Set to "n" for not verifying the uImage */
>>> +	setenv("verify", "n");
>>> +	return 0;
>>> +}
>>
>> Not good to enforce policy like this.  Just don't set it in the config
>> file by default and let users do as they need.
> 
> Hmm. I moved it to CONFIG_EXTRA_ENV_SETTINGS as done by for eample
> u8500_href.h. Is that ok?

It defaults to no, I believe is the thing (so yes, there's a few bad
examples out there including, urk, one that I own).

>> [snip]
>>> diff --git a/common/spl/spl.c b/common/spl/spl.c
>>> index eaea1c8..5adbf0e 100644
>>> --- a/common/spl/spl.c
>>> +++ b/common/spl/spl.c
>>> @@ -78,6 +78,7 @@ void spl_parse_image_header(const struct image_header *header)
>>>  	u32 header_size = sizeof(struct image_header);
>>>  
>>>  	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
>>> +		/* Valid image. Extract information out of header */
>>>  		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
>>>  		spl_image.entry_point = __be32_to_cpu(header->ih_load);
>>>  		/* Load including the header */
>>
>> Just an extra comment, drop please.  Or split out if you feel it's
>> really helpful.  No strong opinion here other than not in the same patch
>> as the rest.
> 
> Ok, I'll drop it, and the omap cleanup also. Not worth the merge
> effort.
> 
> spl_ram_load_image... will I need to create some kind of #ifdef? Or
> would #ifdef BOOT_DEVICE_RAM do the trick?

Good point, yes, we should add CONFIG_SPL_RAM_DEVICE and document it in
docs/README.SPL and the toplevel README.

-- 
Tom

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On 08/30/2012 10:34 AM, Tom Rini wrote:
> On 08/30/2012 10:18 AM, Pavel Machek wrote:
> 
>>>> + * miscellaneous platform dependent initialisations
>>>> + */
>>>> +int misc_init_r(void)
>>>> +{
>>>> +	/* Set to "n" for not verifying the uImage */
>>>> +	setenv("verify", "n");
>>>> +	return 0;
>>>> +}
>>>
>>> Not good to enforce policy like this.  Just don't set it in the config
>>> file by default and let users do as they need.
>>
>> Hmm. I moved it to CONFIG_EXTRA_ENV_SETTINGS as done by for eample
>> u8500_href.h. Is that ok?
> 
> It defaults to no, I believe is the thing (so yes, there's a few bad
> examples out there including, urk, one that I own).

I take it back, yes is the default, so yes, doing
CONFIG_EXTRA_ENV_SETTINGS with verify=no is correct.

-- 
Tom

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> >>> diff --git a/common/spl/spl.c b/common/spl/spl.c
> >>> index eaea1c8..5adbf0e 100644
> >>> --- a/common/spl/spl.c
> >>> +++ b/common/spl/spl.c
> >>> @@ -78,6 +78,7 @@ void spl_parse_image_header(const struct image_header *header)
> >>>  	u32 header_size = sizeof(struct image_header);
> >>>  
> >>>  	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
> >>> +		/* Valid image. Extract information out of header */
> >>>  		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
> >>>  		spl_image.entry_point = __be32_to_cpu(header->ih_load);
> >>>  		/* Load including the header */
> >>
> >> Just an extra comment, drop please.  Or split out if you feel it's
> >> really helpful.  No strong opinion here other than not in the same patch
> >> as the rest.
> > 
> > Ok, I'll drop it, and the omap cleanup also. Not worth the merge
> > effort.
> > 
> > spl_ram_load_image... will I need to create some kind of #ifdef? Or
> > would #ifdef BOOT_DEVICE_RAM do the trick?
> 
> Good point, yes, we should add CONFIG_SPL_RAM_DEVICE and document it in
> docs/README.SPL and the toplevel README.

Ok, something like this? Posting separately, maybe it makes sense to
merge to your PATCH v6...?

[And mental note that HEAP_SIZE needs to be cleaned up in socfpga].

Thanks,
								Pavel
commit 644da18450edd725263f3bf4a721654707a700af
Author: Pavel <pavel@ucw.cz>
Date:   Thu Aug 30 20:03:42 2012 +0200

    Introduce CONFIG_SPL_RAM_DEVICE, as suggested by Tom.

Signed-off-by: Pavel Machek <pavel@denx.de>

diff --git a/README b/README
index ddbeb1b..e782cce 100644
--- a/README
+++ b/README
@@ -2636,6 +2636,9 @@ FIT uImage format:
 		CONFIG_SPL_SPI_SUPPORT
 		Support for drivers/spi/libspi.o in SPL binary
 
+		CONFIG_SPL_RAM_DEVICE
+		Support for running image already present in ram, in SPL binary 
+
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary
 
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 229fd01..fb96a75 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -115,6 +115,7 @@ static void __noreturn jump_to_image_no_args(void)
 	image_entry((u32 *)boot_params_ptr_addr);
 }
 
+#ifdef CONFIG_SPL_RAM_DEVICE
 static void spl_ram_load_image(void)
 {
 	const struct image_header *header;
@@ -128,6 +129,7 @@ static void spl_ram_load_image(void)
 
 	spl_parse_image_header(header);
 }
+#endif
 
 void board_init_r(gd_t *dummy1, ulong dummy2)
 {
@@ -146,9 +148,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	boot_device = spl_boot_device();
 	debug("boot device - %d\n", boot_device);
 	switch (boot_device) {
+#ifdef CONFIG_SPL_RAM_DEVICE
 	case BOOT_DEVICE_RAM:
 		spl_ram_load_image();
 		break;
+#endif
 #ifdef CONFIG_SPL_MMC_SUPPORT
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
diff --git a/doc/README.SPL b/doc/README.SPL
index e4a5ac3..2acafba 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -66,6 +66,7 @@ CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
 CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
 CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
 CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o)
+CONFIG_SPL_RAM_DEVICE (common/spl/spl.c)
 
 
 Normally CPU is assumed to be the same between the SPL and normal

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On 08/30/2012 11:05 AM, Pavel Machek wrote:
> Hi!
> 
>>>>> diff --git a/common/spl/spl.c b/common/spl/spl.c
>>>>> index eaea1c8..5adbf0e 100644
>>>>> --- a/common/spl/spl.c
>>>>> +++ b/common/spl/spl.c
>>>>> @@ -78,6 +78,7 @@ void spl_parse_image_header(const struct image_header *header)
>>>>>  	u32 header_size = sizeof(struct image_header);
>>>>>  
>>>>>  	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
>>>>> +		/* Valid image. Extract information out of header */
>>>>>  		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
>>>>>  		spl_image.entry_point = __be32_to_cpu(header->ih_load);
>>>>>  		/* Load including the header */
>>>>
>>>> Just an extra comment, drop please.  Or split out if you feel it's
>>>> really helpful.  No strong opinion here other than not in the same patch
>>>> as the rest.
>>>
>>> Ok, I'll drop it, and the omap cleanup also. Not worth the merge
>>> effort.
>>>
>>> spl_ram_load_image... will I need to create some kind of #ifdef? Or
>>> would #ifdef BOOT_DEVICE_RAM do the trick?
>>
>> Good point, yes, we should add CONFIG_SPL_RAM_DEVICE and document it in
>> docs/README.SPL and the toplevel README.
> 
> Ok, something like this? Posting separately, maybe it makes sense to
> merge to your PATCH v6...?

Sure, just include the actual spl_ram_load_image bits as well and I'll
pick it up.

-- 
Tom

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> >>> spl_ram_load_image... will I need to create some kind of #ifdef? Or
> >>> would #ifdef BOOT_DEVICE_RAM do the trick?
> >>
> >> Good point, yes, we should add CONFIG_SPL_RAM_DEVICE and document it in
> >> docs/README.SPL and the toplevel README.
> > 
> > Ok, something like this? Posting separately, maybe it makes sense to
> > merge to your PATCH v6...?
> 
> Sure, just include the actual spl_ram_load_image bits as well and I'll
> pick it up.

Here you go.

--

Add support for loading image from ram in SPL.

Signed-off-by: Pavel Machek <pavel@denx.de>

diff --git a/README b/README
index ddbeb1b..e782cce 100644
--- a/README
+++ b/README
@@ -2636,6 +2636,9 @@ FIT uImage format:
 		CONFIG_SPL_SPI_SUPPORT
 		Support for drivers/spi/libspi.o in SPL binary
 
+		CONFIG_SPL_RAM_DEVICE
+		Support for running image already present in ram, in SPL binary 
+
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary
 
diff --git a/common/spl/spl.c b/common/spl/spl.c
index eaea1c8..fb96a75 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -115,6 +115,22 @@ static void __noreturn jump_to_image_no_args(void)
 	image_entry((u32 *)boot_params_ptr_addr);
 }
 
+#ifdef CONFIG_SPL_RAM_DEVICE
+static void spl_ram_load_image(void)
+{
+	const struct image_header *header;
+
+	/* get the header */
+	/* it will point to a address defined by handoff which
+	will tell where the image located inside the flash. For now,
+	it will temporary fixed to address pointed by U-Boot */
+	header = (struct image_header *)
+		(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+
+	spl_parse_image_header(header);
+}
+#endif
+
 void board_init_r(gd_t *dummy1, ulong dummy2)
 {
 	u32 boot_device;
@@ -132,6 +148,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	boot_device = spl_boot_device();
 	debug("boot device - %d\n", boot_device);
 	switch (boot_device) {
+#ifdef CONFIG_SPL_RAM_DEVICE
+	case BOOT_DEVICE_RAM:
+		spl_ram_load_image();
+		break;
+#endif
 #ifdef CONFIG_SPL_MMC_SUPPORT
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
diff --git a/doc/README.SPL b/doc/README.SPL
index e4a5ac3..2acafba 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -66,6 +66,7 @@ CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
 CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
 CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
 CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o)
+CONFIG_SPL_RAM_DEVICE (common/spl/spl.c)
 
 
 Normally CPU is assumed to be the same between the SPL and normal

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On Thu, Aug 30, 2012 at 10:42:11PM +0200, Pavel Machek wrote:
> Hi!
> 
> > >>> spl_ram_load_image... will I need to create some kind of #ifdef? Or
> > >>> would #ifdef BOOT_DEVICE_RAM do the trick?
> > >>
> > >> Good point, yes, we should add CONFIG_SPL_RAM_DEVICE and document it in
> > >> docs/README.SPL and the toplevel README.
> > > 
> > > Ok, something like this? Posting separately, maybe it makes sense to
> > > merge to your PATCH v6...?
> > 
> > Sure, just include the actual spl_ram_load_image bits as well and I'll
> > pick it up.
> 
> Here you go.

With the multi-line comment fixed up, queued for my v6.

-- 
Tom

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Dinh Nguyen]

Hi Tom,

On Thu, Aug 30, 2012 at 4:25 PM, Tom Rini <trini@ti.com> wrote:

> On Thu, Aug 30, 2012 at 10:42:11PM +0200, Pavel Machek wrote:
> > Hi!
> >
> > > >>> spl_ram_load_image... will I need to create some kind of #ifdef? Or
> > > >>> would #ifdef BOOT_DEVICE_RAM do the trick?
> > > >>
> > > >> Good point, yes, we should add CONFIG_SPL_RAM_DEVICE and document
> it in
> > > >> docs/README.SPL and the toplevel README.
> > > >
> > > > Ok, something like this? Posting separately, maybe it makes sense to
> > > > merge to your PATCH v6...?
> > >
> > > Sure, just include the actual spl_ram_load_image bits as well and I'll
> > > pick it up.
> >
> > Here you go.
>
> With the multi-line comment fixed up, queued for my v6.
>

Do you need me to send a fresh version with all the fixes?

Thanks,
Dinh

>
> --
> Tom
>

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On 08/31/2012 02:26 PM, Dinh Nguyen wrote:
> Hi Tom,
> 
> On Thu, Aug 30, 2012 at 4:25 PM, Tom Rini <trini@ti.com
> <mailto:trini@ti.com>> wrote:
> 
>     On Thu, Aug 30, 2012 at 10:42:11PM +0200, Pavel Machek wrote:
>     > Hi!
>     >
>     > > >>> spl_ram_load_image... will I need to create some kind of
>     #ifdef? Or
>     > > >>> would #ifdef BOOT_DEVICE_RAM do the trick?
>     > > >>
>     > > >> Good point, yes, we should add CONFIG_SPL_RAM_DEVICE and
>     document it in
>     > > >> docs/README.SPL and the toplevel README.
>     > > >
>     > > > Ok, something like this? Posting separately, maybe it makes
>     sense to
>     > > > merge to your PATCH v6...?
>     > >
>     > > Sure, just include the actual spl_ram_load_image bits as well
>     and I'll
>     > > pick it up.
>     >
>     > Here you go.
> 
>     With the multi-line comment fixed up, queued for my v6.
> 
> 
> Do you need me to send a fresh version with all the fixes?

With all of the review comments addressed, a fresh series on top of my
v6 is something I would do my best to get pulled in for the next release.

-- 
Tom

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Stefan Roese]

On 08/30/2012 10:42 PM, Pavel Machek wrote:
> +++ b/common/spl/spl.c
> @@ -115,6 +115,22 @@ static void __noreturn jump_to_image_no_args(void)
>  	image_entry((u32 *)boot_params_ptr_addr);
>  }
>  
> +#ifdef CONFIG_SPL_RAM_DEVICE
> +static void spl_ram_load_image(void)
> +{
> +	const struct image_header *header;
> +
> +	/* get the header */
> +	/* it will point to a address defined by handoff which
> +	will tell where the image located inside the flash. For now,
> +	it will temporary fixed to address pointed by U-Boot */

Please use the proper multi-line comment style:

	/*
	 * ...
	 */

Thanks,
Stefan

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

On Wed 2012-08-29 11:26:45, Tom Rini wrote:
> On Wed, Aug 29, 2012 at 03:41:54PM +0200, Pavel Machek wrote:
> > Hi!
> > 
> > > > diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
> > > 
> > > You should setup MEMORY declarations like the other u-boot-spl linker
> > > scripts do so we get build-time confirmation that we haven't exceeded
> > > our size limitations.
> > 
> > Hmm, I tried, but I don't know socfpga memory layout by heart.
> > 
> > Dinh, can you help here?
> 
> I think once you get the answers you should be able to re-post the
> series cleanly and depend on my v5 (or v6) branch.  Thanks!

Porting it to your v5 was easy :-). Newer patch for review is attached.

I took oportunity to cleanup whitespace in
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds. Perhaps someone can
merge that...

Thanks,
								Pavel

commit a7ecaa40d9a02e84ac81da8f49d48595d7f342ad
Author: Pavel <pavel@ucw.cz>
Date:   Thu Aug 30 01:28:00 2012 +0200

    Add changes for socfpga

diff --git a/MAINTAINERS b/MAINTAINERS
index c5a6f2f..df48dea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -765,6 +765,11 @@ Nagendra T S  <nagendra@mistralsolutions.com>
 
    am3517_crane    ARM ARMV7 (AM35x SoC)
 
+Dinh Nguyen <dinguyen@altera.com>
+Chin Liang See <clsee@altera.com>
+
+	socfpga		socfpga_cyclone5
+
 Kyungmin Park <kyungmin.park@samsung.com>
 
 	apollon		ARM1136EJS
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
index 8867e06..1d8efb2 100644
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -37,9 +37,9 @@ SECTIONS
 {
 	.text      :
 	{
-	__start = .;
-	  arch/arm/cpu/armv7/start.o	(.text)
-	  *(.text*)
+		__start = .;
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
 	} >.sram
 
 	. = ALIGN(4);
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
new file mode 100644
index 0000000..376a4bd
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2012 Altera Corporation <www.altera.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	:= lowlevel_init.o
+COBJS-y	:= misc.o timer.o
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk
new file mode 100644
index 0000000..b72ed1e
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/config.mk
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+ifndef CONFIG_SPL_BUILD
+ALL-y	+= $(obj)u-boot.img
+endif
diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
new file mode 100644
index 0000000..815073e
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
@@ -0,0 +1,79 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Save the parameter pass in by previous boot loader */
+.global save_boot_params
+save_boot_params:
+	/* save the parameter here */
+
+	/*
+	 * Setup stack for exception, which is located
+	 * at the end of on-chip RAM. We don't expect exception prior to
+	 * relocation and if that happens, we won't worry -- it will overide
+	 * global data region as the code will goto reset. After relocation,
+	 * this region won't be used by other part of program.
+	 * Hence it is safe.
+	 */
+	ldr	r0, =CONFIG_SYS_INIT_RAM_ADDR
+	ldr	r1, =CONFIG_SYS_INIT_RAM_SIZE
+	add	r0, r0, r1
+	ldr	r1, =IRQ_STACK_START_IN
+	str	r0, [r1]
+
+	bx	lr
+
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Remap */
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * SPL : configure the remap (L3 NIC-301 GPV)
+	 * so the on-chip RAM at lower memory instead ROM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x19
+	str	r1, [r0]
+#else
+	/*
+	 * U-Boot : configure the remap (L3 NIC-301 GPV)
+	 * so the SDRAM at lower memory instead on-chip RAM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x2
+	str	r1, [r0]
+
+	/* Private components security */
+
+	/*
+	 * U-Boot : configure private timer, global timer and cpu
+	 * component access as non secure for kernel stage (as required
+	 * by kernel)
+	 */
+	mrc	p15,4,r0,c15,c0,0
+	add	r1, r0, #0x54
+	ldr	r2, [r1]
+	orr	r2, r2, #0xff
+	orr	r2, r2, #0xf00
+	str	r2, [r1]
+#endif	/* #ifdef CONFIG_SPL_BUILD */
+	mov	pc, lr
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
new file mode 100644
index 0000000..b906701
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -0,0 +1,54 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+	/* request a warm reset */
+	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
+	/* 
+	 * infinite loop here as watchdog will trigger and reset
+	 * the processor 
+	 */
+	while (1)
+		;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+	writel(0, &reset_manager_base->per_mod_reset);
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
new file mode 100644
index 0000000..bf03333
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <version.h>
+#include <image.h>
+#include <malloc.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_RAM;
+}
+
+/*
+ * Board initialization after bss clearance
+ */
+void spl_board_init(void)
+{
+	/* init timer for enabling delay function */
+	timer_init();
+
+	/* de-assert reset for peripherals and bridges based on handoff */
+	reset_deassert_peripherals_handoff();
+
+	/* enable console uart printing */
+	preloader_console_init();
+
+	puts("SPL Boot\n");
+}
diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
new file mode 100644
index 0000000..28da4d0
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/timer.c
@@ -0,0 +1,149 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+
+/*
+ * Timer initialization
+ */
+int timer_init(void)
+{
+	writel(TIMER_LOAD_VAL, &timer_base->load_val);
+	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
+	writel((readl((&timer_base->ctrl)) | 0x3),
+		(&timer_base->ctrl));
+	return 0;
+}
+
+static u32 read_timer(void)
+{
+	return readl(&timer_base->curr_val);
+}
+
+/*
+ * Delay x useconds
+ */
+void __udelay(unsigned long usec)
+{
+	unsigned long now, last;
+	/*
+	 * get the tmo value based on timer clock speed
+	 * tmo = delay required / period of timer clock
+	 */
+	long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000;
+
+	last = read_timer();
+	while (tmo > 0) {
+		now = read_timer();
+		if (last >= now)
+			/* normal mode (non roll) */
+			tmo -= last - now;
+		else
+			/* we have overflow of the count down timer */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		last = now;
+	}
+}
+
+/*
+ * Get the timer value
+ */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * Timer : get the time difference
+ * Unit of tick is based on the CONFIG_SYS_HZ
+ */
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+	if (gd->lastinc >= now) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* we have overflow of the count down timer */
+		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+	}
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+/*
+ * Reset the timer
+ */
+void reset_timer(void)
+{
+	/* capture current decrementer value time */
+	gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+	/* start "advancing" time stamp from 0 */
+	gd->tbl = 0;
+}
+
+/*
+ * Delay function in number of clocks (not in time unit).
+ *
+ * Below is an example of use case:
+ * > reset_timer_count();
+ * > start = get_timer_count (0);
+ * > while (get_timer (start) < num_count) {...}
+ */
+
+/*
+ * Get the timer count value
+ */
+ulong get_timer_count_masked(void)
+{
+	/* current tick value */
+	ulong now = read_timer();
+	if (gd->lastinc >= now) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* we have overflow of the count down timer */
+		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+	}
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+ulong get_timer_count(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * Reset the timer
+ */
+void reset_timer_count(void)
+{
+	/* capture current decrementer value time */
+	gd->lastinc = read_timer();
+	/* start "advancing" time stamp from 0 */
+	gd->tbl = 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
new file mode 100644
index 0000000..7cd409c
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
+	} >.sdram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss : {
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sdram
+
+	. = ALIGN(8);
+	__malloc_start = .;
+	. = . + CONFIG_SPL_MALLOC_SIZE;
+	__malloc_end = .;
+
+	. = . + CONFIG_SPL_STACK_SIZE;
+	. = ALIGN(8);
+	__stack_start = .;
+}
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
new file mode 100644
index 0000000..d9d2c1c
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_RESET_MANAGER_H_
+#define	_RESET_MANAGER_H_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+	u32	padding1;
+	u32	ctrl;
+	u32	padding2;
+	u32	padding3;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+};
+
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+
+#endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
new file mode 100644
index 0000000..f353eb2
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h
new file mode 100644
index 0000000..c9e5f50
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/spl.h
@@ -0,0 +1,30 @@
+/*
+ *  Copyright (C) 2012 Pavel Machek <pavel@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_SPL_H_
+#define _SOCFPGA_SPL_H_
+
+/* Symbols from linker script */
+extern void __malloc_start, __malloc_end, __stack_start;
+
+#define CONFIG_SPL_STACK (&__stack_start)
+#define CONFIG_SYS_SPL_MALLOC_START (&__malloc_start)
+#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
+
+#define BOOT_DEVICE_RAM 1
+
+#endif
diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/include/asm/arch-socfpga/timer.h
new file mode 100644
index 0000000..830c94a
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/timer.h
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_TIMER_H_
+#define _SOCFPGA_TIMER_H_
+
+struct socfpga_timer {
+	u32	load_val;
+	u32	curr_val;
+	u32	ctrl;
+	u32	eoi;
+	u32	int_stat;
+};
+
+#endif
diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile
new file mode 100644
index 0000000..43bbc37
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= socfpga_cyclone5.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
new file mode 100644
index 0000000..1248e3d
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
@@ -0,0 +1,97 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void show_boot_progress(int progress)
+{
+	debug("Boot reached stage %d\n", progress);
+}
+
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	puts("CPU   : Altera SOCFPGA Platform\n");
+	return 0;
+}
+
+/*
+ * Print Board information
+ */
+int checkboard(void)
+{
+	puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
+	return 0;
+}
+
+/*
+ * Initialization function which happen at early stage of c code
+ */
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	icache_enable();
+	return 0;
+}
+
+/*
+ * miscellaneous platform dependent initialisations
+ */
+int misc_init_r(void)
+{
+	/* Set to "n" for not verifying the uImage */
+	setenv("verify", "n");
+	return 0;
+}
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	return 0;
+}
+#endif
+
+/*
+ * DesignWare Ethernet initialization
+ */
+/* We know all the init functions have been run now */
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..1b5c860 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -261,6 +261,7 @@ seaboard                     arm         armv7       seaboard            nvidia
 ventana                      arm         armv7       ventana             nvidia         tegra2
 whistler                     arm         armv7       whistler            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
+socfpga_cyclone5              arm         armv7      socfpga_cyclone5    altera		    socfpga
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 7b5656a..e90146e 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -76,6 +76,7 @@ void spl_parse_image_header(const struct image_header *header)
 	u32 header_size = sizeof(struct image_header);
 
 	if (image_get_magic(header) == IH_MAGIC) {
+		/* Valid image. Extract information out of header */
 		if (spl_image.flags & SPL_COPY_PAYLOAD_ONLY) {
 			/*
 			 * On some system (e.g. powerpc), the load-address and
@@ -125,6 +126,20 @@ static void __noreturn jump_to_image_no_args(void)
 	image_entry((u32 *)boot_params_ptr_addr);
 }
 
+static void spl_ram_load_image(void)
+{
+	const struct image_header *header;
+
+	/* get the header */
+	/* it will point to a address defined by handoff which
+	will tell where the image located inside the flash. For now,
+	it will temporary fixed to address pointed by U-Boot */
+	header = (struct image_header *)
+		(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+
+	spl_parse_image_header(header);
+}
+
 void board_init_r(gd_t *dummy1, ulong dummy2)
 {
 	u32 boot_device;
@@ -142,6 +157,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	boot_device = spl_boot_device();
 	debug("boot device - %d\n", boot_device);
 	switch (boot_device) {
+	case BOOT_DEVICE_RAM:
+		spl_ram_load_image();
+		break;
 #ifdef CONFIG_SPL_MMC_SUPPORT
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
diff --git a/include/common.h b/include/common.h
index 55025c0..469a3af 100644
--- a/include/common.h
+++ b/include/common.h
@@ -704,7 +704,9 @@ void	external_interrupt (struct pt_regs *);
 void	irq_install_handler(int, interrupt_handler_t *, void *);
 void	irq_free_handler   (int);
 void	reset_timer	   (void);
-ulong	get_timer	   (ulong base);
+ulong	get_timer(ulong base);
+void	reset_timer_count(void);
+ulong	get_timer_count(ulong base);
 void	enable_interrupts  (void);
 int	disable_interrupts (void);
 
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
new file mode 100644
index 0000000..d001cbb
--- /dev/null
+++ b/include/configs/socfpga_cyclone5.h
@@ -0,0 +1,242 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/socfpga_base_addrs.h>
+
+/*
+ * High level configuration
+ */
+
+#define CONFIG_ARMV7
+#define CONFIG_L2_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SINGLE_BOOTLOADER
+#define CONFIG_SOCFPGA
+
+#define CONFIG_SYS_TEXT_BASE		0x08000040
+#define V_NS16550_CLK			1000000
+#define CONFIG_BAUDRATE			57600
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_TIMER_CLOCK_KHZ		2400
+#define CONFIG_SYS_LOAD_ADDR		0x7fc0
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"SOCFPGA_CYCLONE5 # "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Enable early stage initialization at C environment
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* flat device tree */
+#define CONFIG_OF_LIBFDT
+/* skip updating the FDT blob */
+#define CONFIG_FDT_BLOB_SKIP_UPDATE
+/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
+#define CONFIG_SYS_BOOTMAPSZ		((256*1024*1024) - (4*1024))
+
+/*
+ * Memory allocation (MALLOC)
+ */
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE			1024
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+/* regular stack */
+#define CONFIG_STACKSIZE		(128 << 10)
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack */
+#define CONFIG_STACKSIZE_IRQ		(4 << 10)
+/* FIQ stack */
+#define CONFIG_STACKSIZE_FIQ		(4 << 10)
+#endif
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+/* Reserving 0x100 space at back of scratch RAM for debug info */
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
+/* Stack pointer prior relocation, must situated@on-chip RAM */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+/* FAT file system support */
+#define CONFIG_CMD_FAT
+
+
+/*
+ * Misc
+ */
+#define CONFIG_DOS_PARTITION            1
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+/*
+ * Environment setup
+ */
+
+/* Delay before automatically booting the default image */
+#define CONFIG_BOOTDELAY		3
+/* Enable auto completion of commands using TAB */
+#define CONFIG_AUTO_COMPLETE
+/* use "hush" command parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMD_RUN
+
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+/*
+ * arguments passed to the bootm command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M at 0x0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=uImage\0" \
+	"fdt_addr=100\0" \
+	"fsloadcmd=ext2load\0" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* using environment setting for stdin, stdout, stderr */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* Enable the call to overwrite_console() */
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+/* Enable overwrite of previous console environment settings */
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* max number of command args	 */
+#define CONFIG_SYS_MAXARGS		16
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * SDRAM Memory Map
+ */
+/* We have 1 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+/* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+/* SDRAM memory size */
+#define PHYS_SDRAM_1_SIZE		0x80000000
+
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
+
+/*
+ * NS16550 Configuration
+ */
+#define UART0_BASE			SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
+#define CONFIG_CONS_INDEX               1
+#define CONFIG_SYS_NS16550_COM1		UART0_BASE
+
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * FLASH
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/*
+ * SPL "Second Program Loader" aka Initial Software
+ */
+
+/* Enable building of SPL globally */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+
+/* TEXT_BASE for linking the SPL binary */
+#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
+
+/* Stack size for SPL */
+#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
+
+/* MALLOC size for SPL */
+#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)
+
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#define CHUNKSZ_CRC32			(1 * 1024)
+
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+/* Support for common/libcommon.o in SPL binary */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+/* Support for lib/libgeneric.o in SPL binary */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#endif	/* __CONFIG_H */


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Marek Vasut]

Dear Pavel Machek,

Minor ramblings below :)

> On Wed 2012-08-29 11:26:45, Tom Rini wrote:
> > On Wed, Aug 29, 2012 at 03:41:54PM +0200, Pavel Machek wrote:
> > > Hi!
> > > 
> > > > > diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
> > > > > b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
> > > > 
> > > > You should setup MEMORY declarations like the other u-boot-spl linker
> > > > scripts do so we get build-time confirmation that we haven't exceeded
> > > > our size limitations.
> > > 
> > > Hmm, I tried, but I don't know socfpga memory layout by heart.
> > > 
> > > Dinh, can you help here?
> > 
> > I think once you get the answers you should be able to re-post the
> > series cleanly and depend on my v5 (or v6) branch.  Thanks!
> 
> Porting it to your v5 was easy :-). Newer patch for review is attached.
> 
> I took oportunity to cleanup whitespace in
> arch/arm/cpu/armv7/omap-common/u-boot-spl.lds. Perhaps someone can
> merge that...

Argh ... what about using git send-email for the patch submission please?

NOTE: I really have a great deal of respect for Pavel, so i do have trouble 
stepping on him properly during the patch review ;-)

> Thanks,
> 								Pavel
> 
> commit a7ecaa40d9a02e84ac81da8f49d48595d7f342ad
> Author: Pavel <pavel@ucw.cz>
> Date:   Thu Aug 30 01:28:00 2012 +0200
> 
>     Add changes for socfpga
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c5a6f2f..df48dea 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -765,6 +765,11 @@ Nagendra T S  <nagendra@mistralsolutions.com>
> 
>     am3517_crane    ARM ARMV7 (AM35x SoC)
> 
> +Dinh Nguyen <dinguyen@altera.com>
> +Chin Liang See <clsee@altera.com>
> +
> +	socfpga		socfpga_cyclone5
> +
>  Kyungmin Park <kyungmin.park@samsung.com>
> 
>  	apollon		ARM1136EJS
> diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
> b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 8867e06..1d8efb2
> 100644
> --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
> +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
> @@ -37,9 +37,9 @@ SECTIONS
>  {
>  	.text      :
>  	{
> -	__start = .;
> -	  arch/arm/cpu/armv7/start.o	(.text)
> -	  *(.text*)
> +		__start = .;
> +		arch/arm/cpu/armv7/start.o	(.text)
> +		*(.text*)
>  	} >.sram

Maybe the cleanup should simply be split into separate patch?

>  	. = ALIGN(4);
> diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
> b/arch/arm/cpu/armv7/socfpga/Makefile new file mode 100644
> index 0000000..376a4bd
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/Makefile
> @@ -0,0 +1,51 @@
> +#
> +# (C) Copyright 2000-2003
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# Copyright (C) 2012 Altera Corporation <www.altera.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB	=  $(obj)lib$(SOC).o
> +
> +SOBJS	:= lowlevel_init.o
> +COBJS-y	:= misc.o timer.o
> +COBJS-$(CONFIG_SPL_BUILD) += spl.o
> +
> +COBJS	:= $(COBJS-y)
> +SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
> +
> +all:	 $(obj).depend $(LIB)
> +
> +$(LIB):	$(OBJS)
> +	$(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/arch/arm/cpu/armv7/socfpga/config.mk
> b/arch/arm/cpu/armv7/socfpga/config.mk new file mode 100644
> index 0000000..b72ed1e
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/config.mk
> @@ -0,0 +1,16 @@
> +#
> +# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed "as is" WITHOUT ANY WARRANTY of any
> +# kind, whether express or implied; without even the implied warranty
> +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +ifndef CONFIG_SPL_BUILD
> +ALL-y	+= $(obj)u-boot.img
> +endif
> diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
> b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S new file mode 100644
> index 0000000..815073e
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
> @@ -0,0 +1,79 @@
> +/*
> + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +
> +/* Save the parameter pass in by previous boot loader */
> +.global save_boot_params
> +save_boot_params:
> +	/* save the parameter here */
> +
> +	/*
> +	 * Setup stack for exception, which is located
> +	 * at the end of on-chip RAM. We don't expect exception prior to
> +	 * relocation and if that happens, we won't worry -- it will overide
> +	 * global data region as the code will goto reset. After relocation,
> +	 * this region won't be used by other part of program.
> +	 * Hence it is safe.
> +	 */
> +	ldr	r0, =CONFIG_SYS_INIT_RAM_ADDR
> +	ldr	r1, =CONFIG_SYS_INIT_RAM_SIZE
> +	add	r0, r0, r1

Won't the preprocessor compute (CONFIG_SYS_INIT_RAM_ADDR + 
CONFIG_SYS_INIT_RAM_SIZE) for you? Then you'd only have to do one LDR and no ADD 
instruction, saving two ticks of CPU :-)

> +	ldr	r1, =IRQ_STACK_START_IN
> +	str	r0, [r1]
> +
> +	bx	lr
> +
> +
> +/* Set up the platform, once the cpu has been initialized */
> +.globl lowlevel_init
> +lowlevel_init:
> +
> +	/* Remap */
> +#ifdef CONFIG_SPL_BUILD
> +	/*
> +	 * SPL : configure the remap (L3 NIC-301 GPV)
> +	 * so the on-chip RAM at lower memory instead ROM.
> +	 */
> +	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
> +	mov	r1, #0x19
> +	str	r1, [r0]
> +#else
> +	/*
> +	 * U-Boot : configure the remap (L3 NIC-301 GPV)
> +	 * so the SDRAM at lower memory instead on-chip RAM.
> +	 */
> +	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
> +	mov	r1, #0x2
> +	str	r1, [r0]
> +
> +	/* Private components security */
> +
> +	/*
> +	 * U-Boot : configure private timer, global timer and cpu
> +	 * component access as non secure for kernel stage (as required
> +	 * by kernel)
> +	 */
> +	mrc	p15,4,r0,c15,c0,0
> +	add	r1, r0, #0x54
> +	ldr	r2, [r1]
> +	orr	r2, r2, #0xff
> +	orr	r2, r2, #0xf00
> +	str	r2, [r1]
> +#endif	/* #ifdef CONFIG_SPL_BUILD */
> +	mov	pc, lr
> diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
> b/arch/arm/cpu/armv7/socfpga/misc.c new file mode 100644
> index 0000000..b906701
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/misc.c
> @@ -0,0 +1,54 @@
> +/*
> + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/reset_manager.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_reset_manager *reset_manager_base =
> +		(void *)SOCFPGA_RSTMGR_ADDRESS;
> +
> +/*
> + * Write the reset manager register to cause reset
> + */

You might want to add __attribute__((noreturn)) to this function :-)

> +void reset_cpu(ulong addr)
> +{
> +	/* request a warm reset */
> +	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
> +	/*
> +	 * infinite loop here as watchdog will trigger and reset
> +	 * the processor
> +	 */
> +	while (1)
> +		;
> +}

[...]

> diff --git a/arch/arm/cpu/armv7/socfpga/timer.c
> b/arch/arm/cpu/armv7/socfpga/timer.c new file mode 100644
> index 0000000..28da4d0
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/timer.c
> @@ -0,0 +1,149 @@
> +/*
> + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/timer.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_timer *timer_base = (void
> *)CONFIG_SYS_TIMERBASE; +
> +/*
> + * Timer initialization
> + */
> +int timer_init(void)
> +{
> +	writel(TIMER_LOAD_VAL, &timer_base->load_val);
> +	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
> +	writel((readl((&timer_base->ctrl)) | 0x3),

I think you should stick to programming in C here, not ((((LISP)))), so try 
cutting down on the ((braces)) :-)

btw. what's this 0x3 magic constant ?

> +		(&timer_base->ctrl));
> +	return 0;
> +}

[...]

> +#include <common.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/io.h>
> +
> +#include <netdev.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void show_boot_progress(int progress)
> +{
> +	debug("Boot reached stage %d\n", progress);
> +}
> +
> +static inline void delay(unsigned long loops)
> +{
> +	__asm__ volatile ("1:\n"
> +		"subs %0, %1, #1\n"
> +		"bne 1b" : "=r" (loops) : "0" (loops));
> +}

Am I flat blind or is this not used here?
[...]

All in all, the code is nice.

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> > I took oportunity to cleanup whitespace in
> > arch/arm/cpu/armv7/omap-common/u-boot-spl.lds. Perhaps someone can
> > merge that...
> 
> Argh ... what about using git send-email for the patch submission please?

I'm not supposed to submit patches here, these are just requests for
review ;-).

> NOTE: I really have a great deal of respect for Pavel, so i do have trouble 
> stepping on him properly during the patch review ;-)

;-).

> > +	ldr	r0, =CONFIG_SYS_INIT_RAM_ADDR
> > +	ldr	r1, =CONFIG_SYS_INIT_RAM_SIZE
> > +	add	r0, r0, r1
> 
> Won't the preprocessor compute (CONFIG_SYS_INIT_RAM_ADDR + 
> CONFIG_SYS_INIT_RAM_SIZE) for you? Then you'd only have to do one LDR and no ADD 
> instruction, saving two ticks of CPU :-)

:-). And opportunity for me to try my luck at arm assembly. Does this
look correct?

        ldr     r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
        ldr     r1, =IRQ_STACK_START_IN
        str     r0, [r1]

        bx      lr

> > +static const struct socfpga_reset_manager *reset_manager_base =
> > +		(void *)SOCFPGA_RSTMGR_ADDRESS;
> > +
> > +/*
> > + * Write the reset manager register to cause reset
> > + */
> 
> You might want to add __attribute__((noreturn)) to this function :-)

Hmm... I guess that should go to the central header file? No need to
sprinkle it all through the C files. (Done).

> > +	writel(TIMER_LOAD_VAL, &timer_base->load_val);
> > +	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
> > +	writel((readl((&timer_base->ctrl)) | 0x3),
> 
> I think you should stick to programming in C here, not ((((LISP)))), so try 
> cutting down on the ((braces)) :-)

Some braces have been harmed by creation of this patch.

> btw. what's this 0x3 magic constant ?

Dinh has to help here :-(.

> > +static inline void delay(unsigned long loops)
> > +{
> > +	__asm__ volatile ("1:\n"
> > +		"subs %0, %1, #1\n"
> > +		"bne 1b" : "=r" (loops) : "0" (loops));
> > +}
> 
> Am I flat blind or is this not used here?

Killed, thanks. Lets see what the compiler thinks.

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Marek Vasut]

Dear Pavel Machek,

> Hi!
> 
> > > I took oportunity to cleanup whitespace in
> > > arch/arm/cpu/armv7/omap-common/u-boot-spl.lds. Perhaps someone can
> > > merge that...
> > 
> > Argh ... what about using git send-email for the patch submission please?
> 
> I'm not supposed to submit patches here, these are just requests for
> review ;-).
> 
> > NOTE: I really have a great deal of respect for Pavel, so i do have
> > trouble stepping on him properly during the patch review ;-)
> 
> ;-).
> 
> > > +	ldr	r0, =CONFIG_SYS_INIT_RAM_ADDR
> > > +	ldr	r1, =CONFIG_SYS_INIT_RAM_SIZE
> > > +	add	r0, r0, r1
> > 
> > Won't the preprocessor compute (CONFIG_SYS_INIT_RAM_ADDR +
> > CONFIG_SYS_INIT_RAM_SIZE) for you? Then you'd only have to do one LDR and
> > no ADD instruction, saving two ticks of CPU :-)
> :
> :-). And opportunity for me to try my luck at arm assembly. Does this
> 
> look correct?
> 
>         ldr     r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
>         ldr     r1, =IRQ_STACK_START_IN
>         str     r0, [r1]
> 
>         bx      lr

Yes

> > > +static const struct socfpga_reset_manager *reset_manager_base =
> > > +		(void *)SOCFPGA_RSTMGR_ADDRESS;
> > > +
> > > +/*
> > > + * Write the reset manager register to cause reset
> > > + */
> > 
> > You might want to add __attribute__((noreturn)) to this function :-)
> 
> Hmm... I guess that should go to the central header file? No need to
> sprinkle it all through the C files. (Done).
> 
> > > +	writel(TIMER_LOAD_VAL, &timer_base->load_val);
> > > +	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
> > > +	writel((readl((&timer_base->ctrl)) | 0x3),
> > 
> > I think you should stick to programming in C here, not ((((LISP)))), so
> > try cutting down on the ((braces)) :-)
> 
> Some braces have been harmed by creation of this patch.

At least one more pair must be killed on the above statement :)

> > btw. what's this 0x3 magic constant ?
> 
> Dinh has to help here :-(.

Also, use setbits_le32() there instead anyway.

> > > +static inline void delay(unsigned long loops)
> > > +{
> > > +	__asm__ volatile ("1:\n"
> > > +		"subs %0, %1, #1\n"
> > > +		"bne 1b" : "=r" (loops) : "0" (loops));
> > > +}
> > 
> > Am I flat blind or is this not used here?
> 
> Killed, thanks. Lets see what the compiler thinks.
> 
> 									Pavel

Best regards,
Marek Vasut

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> > > > +	writel(TIMER_LOAD_VAL, &timer_base->load_val);
> > > > +	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
> > > > +	writel((readl((&timer_base->ctrl)) | 0x3),
> > > 
> > > I think you should stick to programming in C here, not ((((LISP)))), so
> > > try cutting down on the ((braces)) :-)
> > 
> > Some braces have been harmed by creation of this patch.
> 
> At least one more pair must be killed on the above statement :)

I removed two pairs but failed to post the patch ;-). Be sure you'll
never see them again.

> > > btw. what's this 0x3 magic constant ?
> > 
> > Dinh has to help here :-(.
> 
> Also, use setbits_le32() there instead anyway.

Uff, setbits_le32 looks seriously strange. Should I do this?

Thanks for review,
										Pavel

diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
index 79fa081..1ceb6e9 100644
--- a/arch/arm/cpu/armv7/socfpga/timer.c
+++ b/arch/arm/cpu/armv7/socfpga/timer.c
@@ -30,7 +30,7 @@ int timer_init(void)
 {
 	writel(TIMER_LOAD_VAL, &timer_base->load_val);
 	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
-	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
+	setbits_le32(&timer_base->ctrl, 0x3);
 	return 0;
 }
 
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Marek Vasut]

Dear Pavel Machek,

> Hi!
> 
> > > > > +	writel(TIMER_LOAD_VAL, &timer_base->load_val);
> > > > > +	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
> > > > > +	writel((readl((&timer_base->ctrl)) | 0x3),
> > > > 
> > > > I think you should stick to programming in C here, not ((((LISP)))),
> > > > so try cutting down on the ((braces)) :-)
> > > 
> > > Some braces have been harmed by creation of this patch.
> > 
> > At least one more pair must be killed on the above statement :)
> 
> I removed two pairs but failed to post the patch ;-). Be sure you'll
> never see them again.
> 
> > > > btw. what's this 0x3 magic constant ?
> > > 
> > > Dinh has to help here :-(.
> > 
> > Also, use setbits_le32() there instead anyway.
> 
> Uff, setbits_le32 looks seriously strange. Should I do this?

Yes please, that's the suggested way:

Instead of:
ret = readl()
ret |= 1 << BIT;
writel(ret, )

You do:
setbits_le32()

> 
> Thanks for review,
> 										
Pavel
> 
> diff --git a/arch/arm/cpu/armv7/socfpga/timer.c
> b/arch/arm/cpu/armv7/socfpga/timer.c index 79fa081..1ceb6e9 100644
> --- a/arch/arm/cpu/armv7/socfpga/timer.c
> +++ b/arch/arm/cpu/armv7/socfpga/timer.c
> @@ -30,7 +30,7 @@ int timer_init(void)
>  {
>  	writel(TIMER_LOAD_VAL, &timer_base->load_val);
>  	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
> -	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
> +	setbits_le32(&timer_base->ctrl, 0x3);
>  	return 0;
>  }

Best regards,
Marek Vasut

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Chin Liang See]

Hi Pavel,

On the constant 0x3, its to enable the timer plus configure the timer mode to user-defined count mode.
We can covert them to constant as below:

#define TIMER_ENABLE 		(1<<0)
#define TIMER_MODE_USERDEF		(1<<1)

writel((readl((&timer_base->ctrl)) | TIMER_ENABLE | TIMER_MODE_USERDEF )

Thanks and have a nice day!

Chin Liang
Direct Line: +604 - 636 8776



-----Original Message-----
From: Pavel Machek [mailto:pavel at denx.de] 
Sent: Friday, August 31, 2012 1:00 AM
To: Marek Vasut
Cc: Tom Rini; albert.u.boot at aribaud.net; ZY - u-boot; dinh.linux at gmail.com; Chin Liang See
Subject: Re: [U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

Hi!

> > I took oportunity to cleanup whitespace in 
> > arch/arm/cpu/armv7/omap-common/u-boot-spl.lds. Perhaps someone can 
> > merge that...
> 
> Argh ... what about using git send-email for the patch submission please?

I'm not supposed to submit patches here, these are just requests for review ;-).

> NOTE: I really have a great deal of respect for Pavel, so i do have 
> trouble stepping on him properly during the patch review ;-)

;-).

> > +	ldr	r0, =CONFIG_SYS_INIT_RAM_ADDR
> > +	ldr	r1, =CONFIG_SYS_INIT_RAM_SIZE
> > +	add	r0, r0, r1
> 
> Won't the preprocessor compute (CONFIG_SYS_INIT_RAM_ADDR +
> CONFIG_SYS_INIT_RAM_SIZE) for you? Then you'd only have to do one LDR 
> and no ADD instruction, saving two ticks of CPU :-)

:-). And opportunity for me to try my luck at arm assembly. Does this look correct?

        ldr     r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
        ldr     r1, =IRQ_STACK_START_IN
        str     r0, [r1]

        bx      lr

> > +static const struct socfpga_reset_manager *reset_manager_base =
> > +		(void *)SOCFPGA_RSTMGR_ADDRESS;
> > +
> > +/*
> > + * Write the reset manager register to cause reset  */
> 
> You might want to add __attribute__((noreturn)) to this function :-)

Hmm... I guess that should go to the central header file? No need to sprinkle it all through the C files. (Done).

> > +	writel(TIMER_LOAD_VAL, &timer_base->load_val);
> > +	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
> > +	writel((readl((&timer_base->ctrl)) | 0x3),
> 
> I think you should stick to programming in C here, not ((((LISP)))), 
> so try cutting down on the ((braces)) :-)

Some braces have been harmed by creation of this patch.

> btw. what's this 0x3 magic constant ?

Dinh has to help here :-(.

> > +static inline void delay(unsigned long loops) {
> > +	__asm__ volatile ("1:\n"
> > +		"subs %0, %1, #1\n"
> > +		"bne 1b" : "=r" (loops) : "0" (loops)); }
> 
> Am I flat blind or is this not used here?

Killed, thanks. Lets see what the compiler thinks.

									Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On 08/29/2012 04:34 PM, Pavel Machek wrote:
> On Wed 2012-08-29 11:26:45, Tom Rini wrote:
>> On Wed, Aug 29, 2012 at 03:41:54PM +0200, Pavel Machek wrote:
>>> Hi!
>>>
>>>>> diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
>>>>
>>>> You should setup MEMORY declarations like the other u-boot-spl linker
>>>> scripts do so we get build-time confirmation that we haven't exceeded
>>>> our size limitations.
>>>
>>> Hmm, I tried, but I don't know socfpga memory layout by heart.
>>>
>>> Dinh, can you help here?
>>
>> I think once you get the answers you should be able to re-post the
>> series cleanly and depend on my v5 (or v6) branch.  Thanks!
> 
> Porting it to your v5 was easy :-). Newer patch for review is attached.
> 
> I took oportunity to cleanup whitespace in
> arch/arm/cpu/armv7/omap-common/u-boot-spl.lds. Perhaps someone can
> merge that...

Split it out and I'll grab it for v6.  Thanks!  Comments sent to the
other part of the thread just now.

-- 
Tom

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

On Wed 2012-08-29 17:03:22, Tom Rini wrote:
> On 08/29/2012 04:34 PM, Pavel Machek wrote:
> > On Wed 2012-08-29 11:26:45, Tom Rini wrote:
> >> On Wed, Aug 29, 2012 at 03:41:54PM +0200, Pavel Machek wrote:
> >>> Hi!
> >>>
> >>>>> diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
> >>>>
> >>>> You should setup MEMORY declarations like the other u-boot-spl linker
> >>>> scripts do so we get build-time confirmation that we haven't exceeded
> >>>> our size limitations.
> >>>
> >>> Hmm, I tried, but I don't know socfpga memory layout by heart.
> >>>
> >>> Dinh, can you help here?
> >>
> >> I think once you get the answers you should be able to re-post the
> >> series cleanly and depend on my v5 (or v6) branch.  Thanks!
> > 
> > Porting it to your v5 was easy :-). Newer patch for review is attached.
> > 
> > I took oportunity to cleanup whitespace in
> > arch/arm/cpu/armv7/omap-common/u-boot-spl.lds. Perhaps someone can
> > merge that...
> 
> Split it out and I'll grab it for v6.  Thanks!  Comments sent to the
> other part of the thread just now.

Here you go. Thanks!
									Pavel
--

Fix whitespace in omap-common/u-boot-spl.lds.

Signed-off-by: Pavel Machek <pavel@denx.de>

diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
index 8867e06..1d8efb2 100644
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -37,9 +37,9 @@ SECTIONS
 {
 	.text      :
 	{
-	__start = .;
-	  arch/arm/cpu/armv7/start.o	(.text)
-	  *(.text*)
+		__start = .;
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
 	} >.sram
 
 	. = ALIGN(4);


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

On Wed 2012-08-22 18:13:53, Tom Rini wrote:
> On Thu, Aug 23, 2012 at 12:26:53AM +0200, Marek Vasut wrote:
> > Dear dinguyen at altera.com,
> > 
> > > From: Dinh Nguyen <dinguyen@altera.com>
> > > 
> > > Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
> > > 
> > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > > Signed-off-by: Pavel Machek <pavel@denx.de>
> > 
> > [...]
> > 
> > Please CC albert with new arches.
> > 
> > > diff --git a/Makefile b/Makefile
> > > index 5ce5cc3..12aa372 100644
> > > --- a/Makefile
> > > +++ b/Makefile
> > > @@ -369,7 +369,7 @@ BOARD_SIZE_CHECK =
> > >  endif
> > > 
> > >  # Always append ALL so that arch config.mk's can add custom ones
> > > -ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
> > > +ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)u-boot.img
> > > $(obj)System.map
> > 
> > This won't slide
> 
> You can place this into arch/arm/cpu/armv7/socfpga/config.mk (see
> am33xx/config.mk or any of the others) for examples.

Thanks. This does the trick.
								Pavel

commit aa0c16f34948deb16f1d64417c0ce119a721103b
Author: Pavel <pavel@ucw.cz>
Date:   Thu Aug 23 12:54:51 2012 +0200

    Move build of u-boot.img to config.mk from main Makefile.

diff --git a/Makefile b/Makefile
index f12ccbe..73c8e39 100644
--- a/Makefile
+++ b/Makefile
@@ -374,7 +374,7 @@ BOARD_SIZE_CHECK =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)u-boot.img $(obj)System.map
+ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
 
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk
new file mode 100644
index 0000000..b72ed1e
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/config.mk
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+ifndef CONFIG_SPL_BUILD
+ALL-y	+= $(obj)u-boot.img
+endif


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Pavel Machek]

Hi!

> > +/*
> > + * Release peripherals from reset based on handoff
> > + */
> > +void reset_deassert_peripherals_handoff(void)
> > +{
> > +	unsigned int val = 0;
> > +	writel(val, &reset_manager_base->per_mod_reset);
> 
> writel(0, ...

Ok.

> > +int dram_init(void)
> > +{
> > +	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
> > +	return 0;
> > +}
> 
> Can all this be concentrated into single file (reset, sdram, etc. all those 
> small functions).

I created misc.c with those.

> > +	}
> > +	return 0;
> > +}
> 
> I think I don't even wanna know what's the purpose here :-)

Lets leave SPL for next mail :-).
									Pavel

commit ae990b2c7d7ffd0d57e594ec6cdadb769dcc2a9b
Author: Pavel <pavel@ucw.cz>
Date:   Thu Aug 23 12:48:59 2012 +0200

    Cleanups suggested by Marek Vasut: use constant zero instead of
    assigning it to variable, merge reset_manager.c and sdram.c into
    misc.c
    
    Signed-off-by: Pavel Machek <pavel@denx.de>

diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index e4c1213..376a4bd 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
-COBJS-y	:= reset_manager.o sdram.o timer.o
+COBJS-y	:= misc.o timer.o
 COBJS-$(CONFIG_SPL_BUILD) += spl.o
 
 COBJS	:= $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
new file mode 100644
index 0000000..f0229e8
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -0,0 +1,52 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+	/* request a warm reset */
+	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
+	/* infinite loop here as watchdog will trigger and reset
+	 * the processor */
+	while (1)
+		;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+	writel(0, &reset_manager_base->per_mod_reset);
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
deleted file mode 100644
index b0fa211..0000000
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/reset_manager.h>
-
-static const struct socfpga_reset_manager *reset_manager_base =
-		(void *)SOCFPGA_RSTMGR_ADDRESS;
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
-	/* request a warm reset */
-	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
-	/* infinite loop here as watchdog will trigger and reset
-	 * the processor */
-	while (1)
-		;
-}
-
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
-	unsigned int val = 0;
-	writel(val, &reset_manager_base->per_mod_reset);
-}
diff --git a/arch/arm/cpu/armv7/socfpga/sdram.c b/arch/arm/cpu/armv7/socfpga/sdram.c
deleted file mode 100644
index 6714983..0000000
--- a/arch/arm/cpu/armv7/socfpga/sdram.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
-	return 0;
-}

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini]

On Thu, Aug 23, 2012 at 12:50:28PM +0200, Pavel Machek wrote:

[snip]
> +void reset_cpu(ulong addr)
> +{
> +	/* request a warm reset */
> +	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
> +	/* infinite loop here as watchdog will trigger and reset
> +	 * the processor */

/*
 * Is the form of a multi line comment.
 * Or people get upset, sorry.
 */

:)

Things look fine, just expecting a proper v2 posting once you're able to
re-base to the SPL common series.  Thanks!

-- 
Tom