[U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

[Tom Rini <trini@ti.com>]

On 08/30/2012 11:05 AM, Pavel Machek wrote:
> Hi!
> 
>>>>> diff --git a/common/spl/spl.c b/common/spl/spl.c
>>>>> index eaea1c8..5adbf0e 100644
>>>>> --- a/common/spl/spl.c
>>>>> +++ b/common/spl/spl.c
>>>>> @@ -78,6 +78,7 @@ void spl_parse_image_header(const struct image_header *header)
>>>>>  	u32 header_size = sizeof(struct image_header);
>>>>>  
>>>>>  	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
>>>>> +		/* Valid image. Extract information out of header */
>>>>>  		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
>>>>>  		spl_image.entry_point = __be32_to_cpu(header->ih_load);
>>>>>  		/* Load including the header */
>>>>
>>>> Just an extra comment, drop please.  Or split out if you feel it's
>>>> really helpful.  No strong opinion here other than not in the same patch
>>>> as the rest.
>>>
>>> Ok, I'll drop it, and the omap cleanup also. Not worth the merge
>>> effort.
>>>
>>> spl_ram_load_image... will I need to create some kind of #ifdef? Or
>>> would #ifdef BOOT_DEVICE_RAM do the trick?
>>
>> Good point, yes, we should add CONFIG_SPL_RAM_DEVICE and document it in
>> docs/README.SPL and the toplevel README.
> 
> Ok, something like this? Posting separately, maybe it makes sense to
> merge to your PATCH v6...?

Sure, just include the actual spl_ram_load_image bits as well and I'll
pick it up.

-- 
Tom