[U-Boot] [PATCH 3/7] mx35: Fix decode_pll

[Stefano Babic <sbabic@denx.de>]

On 14/08/2012 22:32, Beno?t Th?baudeau wrote:
> The MFN bit-field of the PLL registers represents a signed value. See the
> reference manual.
> 
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---

Hi Beno?t,

>  .../arch/arm/cpu/arm1136/mx35/generic.c            |    9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c
> index dba4903..e369c86 100644
> --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c
> +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c
> @@ -24,6 +24,7 @@
>   */
>  
>  #include <common.h>
> +#include <div64.h>
>  #include <asm/io.h>
>  #include <asm/errno.h>
>  #include <asm/arch/imx-regs.h>
> @@ -126,15 +127,17 @@ static int get_ahb_div(u32 pdr0)
>  static u32 decode_pll(u32 reg, u32 infreq)
>  {
>  	u32 mfi = (reg >> 10) & 0xf;
> -	u32 mfn = reg & 0x3f;
> -	u32 mfd = (reg >> 16) & 0x3f;
> +	s32 mfn = reg & 0x3ff;
> +	u32 mfd = (reg >> 16) & 0x3ff;

The MFN is a signed value. But you are masking now 11 bits. According to
the manual, bit 9-0 are MFN. You are taking in the mask the first bit of
MFI, and this is wrong, isn't it ?

Best regards,
Stefano Babic


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