From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Mon, 03 Sep 2012 17:55:22 +0200 Subject: [U-Boot] [PATCH 5/7] mx35: Fix clock dividers In-Reply-To: <1332440066.3421502.1346686277274.JavaMail.root@advansee.com> References: <1332440066.3421502.1346686277274.JavaMail.root@advansee.com> Message-ID: <5044D2EA.9080507@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 03/09/2012 17:31, Beno?t Th?baudeau wrote: > Hi Stefano, > Hi Beno?t, >> It seems also to me that the current code is wrong if >> MXC_CCM_PDR0_PER_SEL is set. Maybe it was never set. As I see in >> figure >> 5-4, the ipg_per_clk depends only on pdr[21:16]. No idea where the >> second multiplier comes. > > It looks like the current code is based on a pre(PRDF)-/post(PODF)-divider > scheme. I thought the same. > Perhaps the first silicon revision was different and incompatible, or it > was just a bug in the older revisions of the reference manual. The history of > the reference manual says that this figure and some CCM register descriptions > have been updated at some point. Anyway, Linux does like my patch. > >>> + div = CCM_GET_DIVIDER(pdr4, >>> MXC_CCM_PDR4_PER0_PODF_MASK, >>> - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); >>> + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; >> >> The name remains quite confusing. In the manual is PER0_DIV, which is >> the meaning of PODF here ? > > It the abbreviation FSL uses for post-dividers. If the pre-divider is merged > with the post-divider to form a single divider, the naming from the RM makes > more sense. Do you want a new version changing this naming? Yes, make this small change - then from my point of view I am ready to merge it. Regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================