From: Stefano Babic <sbabic@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2] MX28: SPI: Fix the DMA chaining
Date: Thu, 06 Sep 2012 14:20:20 +0200 [thread overview]
Message-ID: <50489504.8020100@denx.de> (raw)
In-Reply-To: <1346465280-985-2-git-send-email-marex@denx.de>
On 01/09/2012 04:08, Marek Vasut wrote:
> It turns out that in order for the SPI DMA to properly support
> continuous transfers longer than 65280 bytes, there are some very
> important parts that were left out from the documentation.
>
> Firstly, the XFER_SIZE register is not written with the whole length
> of a transfer, but is written by each and every chained descriptor
> with the length of the descriptors data buffer.
>
> Next, unlike the demo code supplied by FSL, which only writes one PIO
> word per descriptor, this does not apply if the descriptors are chained,
> since the XFER_SIZE register must be written. Therefore, it is essential
> to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
> written with zero, since they don't apply. The DMA programs the PIO words
> in an incrementing order, so four PIO words.
>
> Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
> must not be set during the whole transfer, but it must be set only on the
> last descriptor in the chain.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Otavio Salvador <otavio@ossystems.com.br>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
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next prev parent reply other threads:[~2012-09-06 12:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-01 2:07 [U-Boot] [PATCH 1/2] MX28: SPI: Fix the DMA DCache race condition Marek Vasut
2012-09-01 2:08 ` [U-Boot] [PATCH 2/2] MX28: SPI: Fix the DMA chaining Marek Vasut
2012-09-06 12:20 ` Stefano Babic [this message]
2012-09-06 12:20 ` [U-Boot] [PATCH 1/2] MX28: SPI: Fix the DMA DCache race condition Stefano Babic
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