* [U-Boot] [PATCH] powerpc mpc85xx: Synchronization Required for mmucsr0 spr
[not found] <1347020643-25549-1-git-send-email-laurent.joye@haslerrail.com>
@ 2012-09-07 12:25 ` Laurent Joye
2012-09-07 18:50 ` Scott Wood
0 siblings, 1 reply; 3+ messages in thread
From: Laurent Joye @ 2012-09-07 12:25 UTC (permalink / raw)
To: u-boot
As explained in the PowerPC e500 Core Family Reference Manual
(Synchronization Requirements for SPRs), an isync instruction
is required after a mtspr mmucsr0 instruction.
Signed-off-by: Laurent Joye <laurent.joye@haslerrail.com>
---
arch/powerpc/cpu/mpc85xx/tlb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c
b/arch/powerpc/cpu/mpc85xx/tlb.c
index 929f6a6..c548f67 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -38,6 +38,7 @@ void invalidate_tlb(u8 tlb)
mtspr(MMUCSR0, 0x4);
if (tlb == 1)
mtspr(MMUCSR0, 0x2);
+ asm volatile("isync");
}
void init_tlbs(void)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* [U-Boot] [PATCH] powerpc mpc85xx: Synchronization Required for mmucsr0 spr
2012-09-07 12:25 ` [U-Boot] [PATCH] powerpc mpc85xx: Synchronization Required for mmucsr0 spr Laurent Joye
@ 2012-09-07 18:50 ` Scott Wood
0 siblings, 0 replies; 3+ messages in thread
From: Scott Wood @ 2012-09-07 18:50 UTC (permalink / raw)
To: u-boot
On 09/07/2012 07:25 AM, Laurent Joye wrote:
> As explained in the PowerPC e500 Core Family Reference Manual
> (Synchronization Requirements for SPRs), an isync instruction
> is required after a mtspr mmucsr0 instruction.
>
> Signed-off-by: Laurent Joye <laurent.joye@haslerrail.com>
> ---
> arch/powerpc/cpu/mpc85xx/tlb.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c
> b/arch/powerpc/cpu/mpc85xx/tlb.c
> index 929f6a6..c548f67 100644
> --- a/arch/powerpc/cpu/mpc85xx/tlb.c
> +++ b/arch/powerpc/cpu/mpc85xx/tlb.c
> @@ -38,6 +38,7 @@ void invalidate_tlb(u8 tlb)
> mtspr(MMUCSR0, 0x4);
> if (tlb == 1)
> mtspr(MMUCSR0, 0x2);
> + asm volatile("isync");
> }
>
> void init_tlbs(void)
>
We can probably just get rid of that function. It only affects
non-IPROT entries, of which we shouldn't have any. As of "powerpc/85xx:
clear out TLB on boot" we shouldn't have any stale TLB1 entries from
before U-Boot took over.
-Scott
^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH] powerpc mpc85xx: Synchronization Required for mmucsr0 spr
@ 2012-09-07 12:52 Joye Laurent
0 siblings, 0 replies; 3+ messages in thread
From: Joye Laurent @ 2012-09-07 12:52 UTC (permalink / raw)
To: u-boot
As explained in the PowerPC e500 Core Family Reference Manual
(Synchronization Requirements for SPRs), an isync instruction
is required after a mtspr mmucsr0 instruction.
Signed-off-by: Laurent Joye <laurent.joye@haslerrail.com>
---
arch/powerpc/cpu/mpc85xx/tlb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c
b/arch/powerpc/cpu/mpc85xx/tlb.c
index 929f6a6..c548f67 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -38,6 +38,7 @@ void invalidate_tlb(u8 tlb)
mtspr(MMUCSR0, 0x4);
if (tlb == 1)
mtspr(MMUCSR0, 0x2);
+ asm volatile("isync");
}
void init_tlbs(void)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
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2012-09-07 12:25 ` [U-Boot] [PATCH] powerpc mpc85xx: Synchronization Required for mmucsr0 spr Laurent Joye
2012-09-07 18:50 ` Scott Wood
2012-09-07 12:52 Joye Laurent
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