[U-Boot] [PATCH V2 19/21] mx6qsabrelite: add support for mx6 solo/duallite

Troy Kisky
2012-09-22T17:24:45Z

On 9/21/2012 9:12 PM, Vikram Narayanan wrote:
> On 9/22/2012 8:09 AM, Troy Kisky wrote:
>> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
>> ---
>> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 231
>> ++++++-------------------
>> board/freescale/mx6qsabrelite/pads.h | 172
>> ++++++++++++++++++
>> 2 files changed, 226 insertions(+), 177 deletions(-)
>> create mode 100644 board/freescale/mx6qsabrelite/pads.h
>>
>> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> index 4b4e89b..ad2347d 100644
>> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> @@ -26,6 +26,8 @@
>> #include<asm/arch/imx-regs.h>
>> #include<asm/arch/iomux.h>
>> #include<asm/arch/mx6x_pins.h>
>> +#include<asm/arch/mx6dl_pins.h>
>> +#include<asm/arch/sys_proto.h>
>> #include<asm/errno.h>
>> #include<asm/gpio.h>
>> #include<asm/imx-common/iomux-v3.h>
>> @@ -38,163 +40,46 @@
>> #include<netdev.h>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>> - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>> +#include "pads.h"
>> +#define FOR_DL_SOLO
>> +#include "pads.h"
>>
>> -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
>> - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>> +int cpu_is_mx6q(void)
>> +{
>> + return get_cpu_type() == MXC_CPU_MX6Q;
>> +}
>>
>> -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>> - PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
>> +#define IOMUX_SETUP(list) iomux_setup(mx6q_##list,
>> ARRAY_SIZE(mx6q_##list), \
>> + mx6dl_solo_##list, ARRAY_SIZE(mx6dl_solo_##list))
>>
>> -#define SPI_PAD_CTRL (PAD_CTL_HYS | \
>> - PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
>> - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
>> +int iomux_setup(iomux_v3_cfg_t *mx6q_pad_list, int mx6q_pad_cnt,
>> + iomux_v3_cfg_t *mx6dl_solo_pad_list, int mx6dl_solo_pad_cnt)
>> +{
>> + int mx6q = cpu_is_mx6q();
>> + iomux_v3_cfg_t *p = mx6q ? mx6q_pad_list : mx6dl_solo_pad_list;
>> + int cnt = mx6q ? mx6q_pad_cnt : mx6dl_solo_pad_cnt;
>>
>> -#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>> - PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
>> + return imx_iomux_v3_setup_multiple_pads(p, cnt);
>> +}
>>
>> -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>> - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
>> - PAD_CTL_ODE | PAD_CTL_SRE_FAST)
>> +static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
>> +static const unsigned char bank_lookup[] = {3, 2};
>>
>> int dram_init(void)
>> {
>> - gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
>> PHYS_SDRAM_SIZE);
>> -
>> - return 0;
>> + unsigned mdctl = readl(MMDC_P0_BASE_ADDR + 0x000);
>> + unsigned mdmisc = readl(MMDC_P0_BASE_ADDR + 0x018);
>> + int bits = 11 + 0 + 0 + 1; /* row+col+bank+width */
>> +
>> + bits += (mdctl>> 24)& 7; /* row */
>> + bits += col_lookup[(mdctl>> 20)& 7]; /* col */
>> + bits += bank_lookup[(mdmisc>> 5)& 1]; /* bank */
>> + bits += (mdctl>> 16)& 3; /* width */
>> + bits += (mdctl>> 30)& 1; /* cs1 enabled*/
>> + gd->ram_size = 1<< bits;
>> + return 0;
>> }
>>
>
> No magic numbers please. Replace it with macros.

Right, will move to a common file as well so that other may use it.

Troy