[U-Boot] [PATCH V2 09/21] mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants

Troy Kisky
2012-09-22T02:39:06Z

This allows us to generate plugin data or
DCD rom style data simply by defining USE_PLUGIN

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/imx-mkimage.h | 177 ++++++++++++++++++
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 248 +++++++++++++-------------
2 files changed, 304 insertions(+), 121 deletions(-)
create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h

diff --git a/arch/arm/include/asm/arch-mx6/imx-mkimage.h b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
new file mode 100644
index 0000000..be71983
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __ASM_ARCH_IMX_MKIMAGE_H__
+#define __ASM_ARCH_IMX_MKIMAGE_H__
+
+/* mx6 duallite and solo have same offsets */
+/*
+ * Bits 31:30 :
+ * 0 : 29:2 absolute address, 1:0 # of data values,
+ * followed by 0,1,2,4 data values
+ * 0 means repeat last data value
+ * 1 : iomuxc relative address, 9:0 mx6q offset, 19:10 mx6dl/solo offset,
+ * 29:20 mx6_sololite offset, 0 offset means skip if this processor
+ * previous data repeated
+ * 2 : same as 1, but single data value follows
+ * 3 : same as 1, but 4 data values follow
+ *
+ * data order is mx6q, mx6dl, mx6solo, mx6_sololite
+ * if no data given, repeat previous line data
+ * if not all data given, repeat prior value
+ */
+#define MA(mx6q, mx6dl_solo, mx6sololite) ((mx6q / 4 & 0x3ff) | \
+ ((mx6dl_solo / 4 & 0x3ff) * 0x400) | \
+ ((mx6sololite / 4 & 0x3ff) * 0x100000))
+
+#define IOM_DRAM_DQM0 MA(0x5ac, 0x470, 0x0)
+#define IOM_DRAM_DQM1 MA(0x5b4, 0x474, 0x0)
+#define IOM_DRAM_DQM2 MA(0x528, 0x478, 0x0)
+#define IOM_DRAM_DQM3 MA(0x520, 0x47c, 0x0)
+#define IOM_DRAM_DQM4 MA(0x514, 0x480, 0x0)
+#define IOM_DRAM_DQM5 MA(0x510, 0x484, 0x0)
+#define IOM_DRAM_DQM6 MA(0x5bc, 0x488, 0x0)
+#define IOM_DRAM_DQM7 MA(0x5c4, 0x48c, 0x0)
+
+#define IOM_DRAM_CAS MA(0x56c, 0x464, 0x0)
+#define IOM_DRAM_RAS MA(0x578, 0x490, 0x0)
+#define IOM_DRAM_RESET MA(0x57c, 0x494, 0x0)
+#define IOM_DRAM_SDCLK_0 MA(0x588, 0x4ac, 0x0)
+#define IOM_DRAM_SDCLK_1 MA(0x594, 0x4b0, 0x0)
+#define IOM_DRAM_SDBA2 MA(0x58c, 0x4a0, 0x0)
+#define IOM_DRAM_SDCKE0 MA(0x590, 0x4a4, 0x0)
+#define IOM_DRAM_SDCKE1 MA(0x598, 0x4a8, 0x0)
+#define IOM_DRAM_SDODT0 MA(0x59c, 0x4b4, 0x0)
+#define IOM_DRAM_SDODT1 MA(0x5a0, 0x4b8, 0x0)
+
+#define IOM_DRAM_SDQS0 MA(0x5a8, 0x4bc, 0x0)
+#define IOM_DRAM_SDQS1 MA(0x5b0, 0x4c0, 0x0)
+#define IOM_DRAM_SDQS2 MA(0x524, 0x4c4, 0x0)
+#define IOM_DRAM_SDQS3 MA(0x51c, 0x4c8, 0x0)
+#define IOM_DRAM_SDQS4 MA(0x518, 0x4cc, 0x0)
+#define IOM_DRAM_SDQS5 MA(0x50c, 0x4d0, 0x0)
+#define IOM_DRAM_SDQS6 MA(0x5b8, 0x4d4, 0x0)
+#define IOM_DRAM_SDQS7 MA(0x5c0, 0x4d8, 0x0)
+
+#define IOM_GRP_B0DS MA(0x784, 0x764, 0x0)
+#define IOM_GRP_B1DS MA(0x788, 0x770, 0x0)
+#define IOM_GRP_B2DS MA(0x794, 0x778, 0x0)
+#define IOM_GRP_B3DS MA(0x79c, 0x77c, 0x0)
+#define IOM_GRP_B4DS MA(0x7a0, 0x780, 0x0)
+#define IOM_GRP_B5DS MA(0x7a4, 0x784, 0x0)
+#define IOM_GRP_B6DS MA(0x7a8, 0x78c, 0x0)
+#define IOM_GRP_B7DS MA(0x748, 0x748, 0x0)
+#define IOM_GRP_ADDDS MA(0x74c, 0x74c, 0x0)
+#define IOM_DDRMODE_CTL MA(0x750, 0x750, 0x0)
+#define IOM_GRP_DDRPKE MA(0x758, 0x754, 0x0)
+#define IOM_GRP_DDRMODE MA(0x774, 0x760, 0x0)
+#define IOM_GRP_CTLDS MA(0x78c, 0x76c, 0x0)
+#define IOM_GRP_DDR_TYPE MA(0x798, 0x774, 0x0)
+
+#define MMDC_P0 0x021b0000
+#define MMDC_P1 0x021b4000
+#define IOMUXC_BASE_ADDR 0x020e0000
+#define CCM_BASE 0x020C4000
+#define IRAM_FREE_START 0x00907000
+
+#define IOMUXC_GPR4 (IOMUXC_BASE_ADDR + 0x010)
+#define IOMUXC_GPR6 (IOMUXC_BASE_ADDR + 0x018)
+#define IOMUXC_GPR7 (IOMUXC_BASE_ADDR + 0x01c)
+
+#define MMDC_MDCTL 0x000
+#define MMDC_MDPDC 0x004
+#define MMDC_MDOTC 0x008
+#define MMDC_MDCFG0 0x00c
+#define MMDC_MDCFG1 0x010
+#define MMDC_MDCFG2 0x014
+#define MMDC_MDMISC 0x018
+#define MMDC_MDSCR 0x01c
+#define MMDC_MDREF 0x020
+#define MMDC_MDRWD 0x02c
+#define MMDC_MDOR 0x030
+#define MMDC_MDASP 0x040
+#define MMDC_MAPSR 0x404
+#define MMDC_MPZQHWCTRL 0x800
+#define MMDC_MPWLDECTRL0 0x80c
+#define MMDC_MPWLDECTRL1 0x810
+#define MMDC_MPODTCTRL 0x818
+#define MMDC_MPRDDQBY0DL 0x81c
+#define MMDC_MPRDDQBY1DL 0x820
+#define MMDC_MPRDDQBY2DL 0x824
+#define MMDC_MPRDDQBY3DL 0x828
+#define MMDC_MPDGCTRL0 0x83c
+#define MMDC_MPDGCTRL1 0x840
+#define MMDC_MPRDDLCTL 0x848
+#define MMDC_MPWRDLCTL 0x850
+#define MMDC_MPMUR0 0x8b8
+
+#define CCM_CCGR0 0x068
+#define CCM_CCGR1 0x06c
+#define CCM_CCGR2 0x070
+#define CCM_CCGR3 0x074
+#define CCM_CCGR4 0x078
+#define CCM_CCGR5 0x07c
+#define CCM_CCGR6 0x080
+
+
+#ifdef USE_PLUGIN
+#define IOMUX_ENTRY(addr, args...) iomux_entry addr, args
+#define IOMUX_ENTRY1(addr, q) IOMUX_ENTRY(addr, q)
+#define IOMUX_ENTRY2(addr, q, dl) IOMUX_ENTRY(addr, q, dl)
+#define IOMUX_ENTRY3(addr, q, dl, solo) IOMUX_ENTRY(addr, q, dl, solo)
+#define IOMUX_ENTRY4(addr, q, dl, solo, sl) IOMUX_ENTRY(addr, q, dl, solo, sl)
+#define WRITE_ENTRY(addr, args...) write_entry addr, args
+#define WRITE_ENTRY1(addr, q) WRITE_ENTRY(addr, q)
+#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY(addr, q, dl)
+#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY(addr, q, dl, solo)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY(addr, q, dl, solo, sl)
+#else
+
+#define IOMUX_ADDR(addr, div) (IOMUXC_BASE_ADDR + \
+ ((((addr) / (div)) & 0x3ff) * 4))
+#define IOMUX_ENTRY1(addr, q) DATA 4, IOMUX_ADDR(addr, _FOR_DIV), q
+#define WRITE_ENTRY1(addr, q) DATA 4, addr, q
+#ifdef FOR_MX6Q
+#define _FOR_DIV 1
+#define IOMUX_ENTRY2(addr, q, dl) IOMUX_ENTRY1(addr, q)
+#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY1(addr, q)
+#define IOMUX_ENTRY3(addr, q, dl, solo) IOMUX_ENTRY1(addr, q)
+#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, q)
+#define IOMUX_ENTRY4(addr, q, dl, solo, sl) IOMUX_ENTRY1(addr, q)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, q)
+#else
+
+#define IOMUX_ENTRY2(addr, q, dl) IOMUX_ENTRY1(addr, dl)
+#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY1(addr, dl)
+#ifdef FOR_MX6DL
+#define _FOR_DIV 0x400
+#define IOMUX_ENTRY3(addr, q, dl, solo) IOMUX_ENTRY1(addr, dl)
+#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, dl)
+#define IOMUX_ENTRY4(addr, q, dl, solo, sl) IOMUX_ENTRY1(addr, dl)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, dl)
+#else
+
+#define IOMUX_ENTRY3(addr, q, dl, solo) IOMUX_ENTRY1(addr, solo)
+#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, solo)
+#ifdef FOR_MX6SOLO
+#define _FOR_DIV 0x400
+#define IOMUX_ENTRY4(addr, q, dl, solo, sl) IOMUX_ENTRY1(addr, solo)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, solo)
+#else
+
+#define IOMUX_ENTRY4(addr, q, dl, solo, sl) IOMUX_ENTRY1(addr, sl)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, sl)
+#ifdef FOR_MX6SOLOLITE
+#define _FOR_DIV 0x100000
+#else
+
+#error "Please select cpu"
+#endif /* FOR_MX6SOLOLITE */
+#endif /* FOR_MX6SOLO */
+#endif /* FOR_MX6DL */
+#endif /* FOR_MX6Q */
+#endif /* USE_PLUGIN */
+
+#endif /*__ASM_ARCH_IMX_MKIMAGE_H__ */
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index c86cd40..a95831f 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -25,6 +25,9 @@
*
* The syntax is taken as close as possible with the kwbimage
*/
+#define FOR_MX6Q
+
+#include <asm/arch/imx-mkimage.h>

/* image version */
IMAGE_VERSION 2
@@ -35,6 +38,9 @@ IMAGE_VERSION 2
*/
BOOT_FROM sd

+#ifdef USE_PLUGIN
+ plugin IRAM_FREE_START+0x42c arch/arm/cpu/armv7/mx6/plugin.bin
+#endif
/*
* Device Configuration Data (DCD)
*
@@ -46,129 +52,129 @@ BOOT_FROM sd
* Address absolute address of the register
* value value to be stored in the register
*/
-DATA 4 0x020e05a8 0x00000030
-DATA 4 0x020e05b0 0x00000030
-DATA 4 0x020e0524 0x00000030
-DATA 4 0x020e051c 0x00000030
-
-DATA 4 0x020e0518 0x00000030
-DATA 4 0x020e050c 0x00000030
-DATA 4 0x020e05b8 0x00000030
-DATA 4 0x020e05c0 0x00000030
-
-DATA 4 0x020e05ac 0x00020030
-DATA 4 0x020e05b4 0x00020030
-DATA 4 0x020e0528 0x00020030
-DATA 4 0x020e0520 0x00020030
-
-DATA 4 0x020e0514 0x00020030
-DATA 4 0x020e0510 0x00020030
-DATA 4 0x020e05bc 0x00020030
-DATA 4 0x020e05c4 0x00020030
-
-DATA 4 0x020e056c 0x00020030
-DATA 4 0x020e0578 0x00020030
-DATA 4 0x020e0588 0x00020030
-DATA 4 0x020e0594 0x00020030
-
-DATA 4 0x020e057c 0x00020030
-DATA 4 0x020e0590 0x00003000
-DATA 4 0x020e0598 0x00003000
-DATA 4 0x020e058c 0x00000000
-
-DATA 4 0x020e059c 0x00003030
-DATA 4 0x020e05a0 0x00003030
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e0788 0x00000030
-
-DATA 4 0x020e0794 0x00000030
-DATA 4 0x020e079c 0x00000030
-DATA 4 0x020e07a0 0x00000030
-DATA 4 0x020e07a4 0x00000030
-
-DATA 4 0x020e07a8 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0750 0x00020000
-
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0798 0x000C0000
-
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-
-DATA 4 0x021b0018 0x00081740
-
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538E64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b002c 0x000026D2
-
-DATA 4 0x021b0030 0x005B0E21
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0040 0x00000027
-DATA 4 0x021b0000 0x831A0000
-
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x0408803A
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x0000803B
-DATA 4 0x021b001c 0x00428031
-DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x09408038
-
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b001c 0x04008048
-DATA 4 0x021b0800 0xA1380003
-DATA 4 0x021b4800 0xA1380003
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00022227
-DATA 4 0x021b4818 0x00022227
-
-DATA 4 0x021b083c 0x434B0350
-DATA 4 0x021b0840 0x034C0359
-DATA 4 0x021b483c 0x434B0350
-DATA 4 0x021b4840 0x03650348
-DATA 4 0x021b0848 0x4436383B
-DATA 4 0x021b4848 0x39393341
-DATA 4 0x021b0850 0x35373933
-DATA 4 0x021b4850 0x48254A36
-
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-
-DATA 4 0x021b480c 0x00440044
-DATA 4 0x021b4810 0x00440044
-
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-
-DATA 4 0x021b001c 0x00000000
-DATA 4 0x021b0404 0x00011006
+IOMUX_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS3, 0x00000030)
+
+IOMUX_ENTRY1(IOM_DRAM_SDQS4, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS5, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS6, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS7, 0x00000030)
+
+IOMUX_ENTRY1(IOM_DRAM_DQM0, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM1, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM2, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM3, 0x00020030)
+
+IOMUX_ENTRY1(IOM_DRAM_DQM4, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM5, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM6, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM7, 0x00020030)
+
+IOMUX_ENTRY1(IOM_DRAM_CAS, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_RAS, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
+
+IOMUX_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
+IOMUX_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
+IOMUX_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
+
+IOMUX_ENTRY1(IOM_DRAM_SDODT0, 0x00003030)
+IOMUX_ENTRY1(IOM_DRAM_SDODT1, 0x00003030)
+IOMUX_ENTRY1(IOM_GRP_B0DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B1DS, 0x00000030)
+
+IOMUX_ENTRY1(IOM_GRP_B2DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B3DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B4DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B5DS, 0x00000030)
+
+IOMUX_ENTRY1(IOM_GRP_B6DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B7DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+IOMUX_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
+
+IOMUX_ENTRY1(IOM_GRP_DDRPKE, 0x00000000)
+IOMUX_ENTRY1(IOM_GRP_DDRMODE, 0x00020000)
+IOMUX_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY3DL, 0x33333333)
+
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY3DL, 0x33333333)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDMISC, 0x00081740)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008000)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG0, 0x555A7975)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG1, 0xFF538E64)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG2, 0x01FF00DB)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDRWD, 0x000026D2)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDOR, 0x005B0E21)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDOTC, 0x09444040)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDPDC, 0x00025576)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDASP, 0x00000027)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCTL, 0x831A0000)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04088032)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0408803A)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008033)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0000803B)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428031)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428039)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408030)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408038)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008040)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008048)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPZQHWCTRL, 0xA1380003)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPZQHWCTRL, 0xA1380003)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDREF, 0x00005800)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPODTCTRL, 0x00022227)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPODTCTRL, 0x00022227)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL0, 0x434B0350)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL0, 0x434B0350)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL1, 0x03650348)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDLCTL, 0x4436383B)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDLCTL, 0x39393341)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPWRDLCTL, 0x35373933)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPWRDLCTL, 0x48254A36)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL0, 0x001F001F)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL1, 0x001F001F)
+
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL0, 0x00440044)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL1, 0x00440044)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPMUR0, 0x00000800)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPMUR0, 0x00000800)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00000000)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MAPSR, 0x00011006)

/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR0, 0x00C03F3F)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR1, 0x0030FC03)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR2, 0x0FFFC000)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR3, 0x3FF00000)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR4, 0x00FFF300)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR5, 0x0F0000C3)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR6, 0x000003FF)

/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
+WRITE_ENTRY1(IOMUXC_GPR4, 0xF00000CF)
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
+WRITE_ENTRY1(IOMUXC_GPR6, 0x007F007F)
+WRITE_ENTRY1(IOMUXC_GPR7, 0x007F007F)
--
1.7.9.5