[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Eric Nelson]

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
 drivers/video/mxc_ipuv3_fb.c |   20 ++++++++++++++++++++
 include/ipu_pixfmt.h         |    1 +
 2 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c
index c38e22d..47b336e 100644
--- a/drivers/video/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc_ipuv3_fb.c
@@ -38,6 +38,7 @@
 #include "videomodes.h"
 #include "ipu.h"
 #include "mxcfb.h"
+#include "ipu_regs.h"
 
 static int mxcfb_map_video_memory(struct fb_info *fbi);
 static int mxcfb_unmap_video_memory(struct fb_info *fbi);
@@ -576,6 +577,25 @@ err0:
 	return ret;
 }
 
+void ipuv3_fb_shutdown(void)
+{
+	int i;
+	struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT;
+
+	for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) {
+		struct fb_info *fbi = mxcfb_info[i];
+		if (fbi) {
+			struct mxcfb_info *mxc_fbi = fbi->par;
+			ipu_disable_channel(mxc_fbi->ipu_ch);
+			ipu_uninit_channel(mxc_fbi->ipu_ch);
+		}
+	}
+	for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) {
+		__raw_writel(__raw_readl(&stat->int_stat[i]),
+			     &stat->int_stat[i]);
+	}
+}
+
 void *video_hw_init(void)
 {
 	int ret;
diff --git a/include/ipu_pixfmt.h b/include/ipu_pixfmt.h
index 0019898..4baa711 100644
--- a/include/ipu_pixfmt.h
+++ b/include/ipu_pixfmt.h
@@ -77,5 +77,6 @@
 #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P')	/*< 16 YUV 4:2:2 */
 
 int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
+void ipuv3_fb_shutdown(void);
 
 #endif
-- 
1.7.9

[U-Boot] [PATCH] i.MX6: set drive strength for parallel RGB pads

[Eric Nelson]

Default drive strength is disabled and won't function.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
 arch/arm/include/asm/arch-mx6/mx6x_pins.h |   58 ++++++++++++++--------------
 1 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/mx6x_pins.h b/arch/arm/include/asm/arch-mx6/mx6x_pins.h
index 3d66d64..3ade8dc 100644
--- a/arch/arm/include/asm/arch-mx6/mx6x_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6x_pins.h
@@ -530,20 +530,20 @@ enum {
 	MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16	= IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_BCLK__GPIO_6_31		= IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31	= IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
-	MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16	= IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0	= IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
-	MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15	= IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15	= IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15	= IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC	= IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN15__GPIO_4_17		= IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1	= IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
-	MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2	= IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2	= IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2	= IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD	= IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30	= IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
@@ -551,7 +551,7 @@ enum {
 	MX6Q_PAD_DI0_PIN2__GPIO_4_18		= IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2		= IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9	= IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3	= IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3	= IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3	= IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS	= IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
@@ -564,17 +564,17 @@ enum {
 	MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD	= IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN4__USDHC1_WP		= IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0),
 	MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD	= IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0),
-	MX6Q_PAD_DI0_PIN4__GPIO_4_20		= IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0),
+	MX6Q_PAD_DI0_PIN4__GPIO_4_20		= IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4	= IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11  = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0	= IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0	= IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0	= IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK	= IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN	= IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT0__GPIO_4_21		= IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5	= IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1	= IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1	= IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1	= IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI	= IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
@@ -582,7 +582,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT1__GPIO_4_22		= IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6	= IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2	= IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2	= IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2	= IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO	= IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
@@ -590,7 +590,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT2__GPIO_4_23		= IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7	= IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3	= IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3	= IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3	= IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0		= IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
@@ -598,7 +598,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT3__GPIO_4_24		= IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8	= IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4	= IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4	= IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4	= IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1		= IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4	= IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
@@ -606,7 +606,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT4__GPIO_4_25		= IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9	= IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15	= IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5	= IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5	= IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5	= IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2		= IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS	= IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
@@ -614,7 +614,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT5__GPIO_4_26		= IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10	= IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6	= IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6	= IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6	= IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3		= IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC	= IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
@@ -622,7 +622,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT6__GPIO_4_27		= IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11	= IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7	= IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7	= IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7	= IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY		= IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
@@ -630,7 +630,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT7__GPIO_4_28		= IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12	= IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8	= IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8	= IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8	= IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT8__PWM1_PWMO		= IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B	= IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
@@ -638,7 +638,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT8__GPIO_4_29		= IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13	= IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9	= IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9	= IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9	= IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT9__PWM2_PWMO		= IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B	= IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
@@ -646,41 +646,41 @@ enum {
 	MX6Q_PAD_DISP0_DAT9__GPIO_4_30		= IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14	= IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10	= IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10	= IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10	= IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6	= IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT10__GPIO_4_31		= IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15	= IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11	= IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11	= IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11	= IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT11__GPIO_5_5		= IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16	= IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12	= IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12	= IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12	= IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED	= IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT12__GPIO_5_6		= IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17	= IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13	= IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13	= IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13	= IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS	= IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
 	MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT13__GPIO_5_7		= IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18	= IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14	= IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14	= IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14	= IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC	= IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
 	MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT14__GPIO_5_8		= IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19	= IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15	= IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15	= IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15	= IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1	= IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
 	MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1	= IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
@@ -688,7 +688,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT15__GPIO_5_9		= IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20	= IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16	= IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16	= IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16	= IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI	= IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
 	MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC	= IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
@@ -696,7 +696,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT16__GPIO_5_10		= IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21	= IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17	= IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17	= IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17	= IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO	= IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
 	MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD	= IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
@@ -704,7 +704,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT17__GPIO_5_11		= IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22	= IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27	= IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18	= IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18	= IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18	= IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0	= IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0),
 	MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS	= IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0),
@@ -712,7 +712,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT18__GPIO_5_12		= IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23	= IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2	= IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19	= IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19	= IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19	= IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK	= IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0),
 	MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD	= IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0),
@@ -720,7 +720,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT19__GPIO_5_13		= IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24	= IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3	= IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20	= IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20	= IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20	= IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK	= IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0),
 	MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC	= IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
@@ -728,7 +728,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT20__GPIO_5_14		= IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25	= IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21	= IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21	= IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21	= IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI	= IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
 	MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD	= IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
@@ -736,7 +736,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT21__GPIO_5_15		= IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26	= IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22	= IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22	= IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22	= IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO	= IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
 	MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS	= IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
@@ -744,7 +744,7 @@ enum {
 	MX6Q_PAD_DISP0_DAT22__GPIO_5_16		= IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27	= IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
-	MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23	= IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23	= IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23	= IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0	= IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
 	MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD	= IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
-- 
1.7.9

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Eric Nelson]

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
 drivers/video/mxc_ipuv3_fb.c |   20 ++++++++++++++++++++
 include/ipu_pixfmt.h         |    1 +
 2 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c
index c38e22d..47b336e 100644
--- a/drivers/video/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc_ipuv3_fb.c
@@ -38,6 +38,7 @@
 #include "videomodes.h"
 #include "ipu.h"
 #include "mxcfb.h"
+#include "ipu_regs.h"
 
 static int mxcfb_map_video_memory(struct fb_info *fbi);
 static int mxcfb_unmap_video_memory(struct fb_info *fbi);
@@ -576,6 +577,25 @@ err0:
 	return ret;
 }
 
+void ipuv3_fb_shutdown(void)
+{
+	int i;
+	struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT;
+
+	for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) {
+		struct fb_info *fbi = mxcfb_info[i];
+		if (fbi) {
+			struct mxcfb_info *mxc_fbi = fbi->par;
+			ipu_disable_channel(mxc_fbi->ipu_ch);
+			ipu_uninit_channel(mxc_fbi->ipu_ch);
+		}
+	}
+	for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) {
+		__raw_writel(__raw_readl(&stat->int_stat[i]),
+			     &stat->int_stat[i]);
+	}
+}
+
 void *video_hw_init(void)
 {
 	int ret;
diff --git a/include/ipu_pixfmt.h b/include/ipu_pixfmt.h
index 0019898..4baa711 100644
--- a/include/ipu_pixfmt.h
+++ b/include/ipu_pixfmt.h
@@ -77,5 +77,6 @@
 #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P')	/*< 16 YUV 4:2:2 */
 
 int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
+void ipuv3_fb_shutdown(void);
 
 #endif
-- 
1.7.9

[U-Boot] [PATCH 2/2] i.MX: shut down video before launch of O/S

[Eric Nelson]

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
 arch/arm/imx-common/Makefile     |    1 +
 arch/arm/imx-common/preboot_os.c |   34 ++++++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/imx-common/preboot_os.c

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index b3e608e..31dc52e 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -32,6 +32,7 @@ COBJS-y	= iomux-v3.o timer.o cpu.o speed.o
 COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
 endif
 COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
+COBJS-y += preboot_os.o
 COBJS	:= $(sort $(COBJS-y))
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/imx-common/preboot_os.c b/arch/arm/imx-common/preboot_os.c
new file mode 100644
index 0000000..ed7a9e0
--- /dev/null
+++ b/arch/arm/imx-common/preboot_os.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#if defined(CONFIG_VIDEO_IPUV3)
+#include <ipu_pixfmt.h>
+#endif
+
+void arch_preboot_os(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+	/* disable video before launching O/S */
+	ipuv3_fb_shutdown();
+#endif
+}
-- 
1.7.9

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Eric Nelson]

On 09/21/2012 01:56 PM, Eric Nelson wrote:
> Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com>
> ---
>   drivers/video/mxc_ipuv3_fb.c |   20 ++++++++++++++++++++
>   include/ipu_pixfmt.h         |    1 +
>   2 files changed, 21 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c
> index c38e22d..47b336e 100644
> --- a/drivers/video/mxc_ipuv3_fb.c
> +++ b/drivers/video/mxc_ipuv3_fb.c
> @@ -38,6 +38,7 @@
>   #include "videomodes.h"
>   #include "ipu.h"
>   #include "mxcfb.h"
> +#include "ipu_regs.h"
>
>   static int mxcfb_map_video_memory(struct fb_info *fbi);
>   static int mxcfb_unmap_video_memory(struct fb_info *fbi);
> @@ -576,6 +577,25 @@ err0:
>   	return ret;
>   }
>
> +void ipuv3_fb_shutdown(void)
> +{
> +	int i;
> +	struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT;
> +
> +	for (i = 0; i<  ARRAY_SIZE(mxcfb_info); i++) {
> +		struct fb_info *fbi = mxcfb_info[i];
> +		if (fbi) {
> +			struct mxcfb_info *mxc_fbi = fbi->par;
> +			ipu_disable_channel(mxc_fbi->ipu_ch);
> +			ipu_uninit_channel(mxc_fbi->ipu_ch);
> +		}
> +	}
> +	for (i = 0; i<  ARRAY_SIZE(stat->int_stat); i++) {
> +		__raw_writel(__raw_readl(&stat->int_stat[i]),
> +			&stat->int_stat[i]);
> +	}
> +}
> +
>   void *video_hw_init(void)
>   {
>   	int ret;
> diff --git a/include/ipu_pixfmt.h b/include/ipu_pixfmt.h
> index 0019898..4baa711 100644
> --- a/include/ipu_pixfmt.h
> +++ b/include/ipu_pixfmt.h
> @@ -77,5 +77,6 @@
>   #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P')	/*<  16 YUV 4:2:2 */
>
>   int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
> +void ipuv3_fb_shutdown(void);
>
>   #endif

Sorry. This is a duplicate of a prior e-mail.

[U-Boot] [PATCH 2/2] i.MX: shut down video before launch of O/S

[Eric Nelson]

On 09/21/2012 01:56 PM, Eric Nelson wrote:
> Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com>
> ---
>   arch/arm/imx-common/Makefile     |    1 +
>   arch/arm/imx-common/preboot_os.c |   34 ++++++++++++++++++++++++++++++++++
>   2 files changed, 35 insertions(+), 0 deletions(-)
>   create mode 100644 arch/arm/imx-common/preboot_os.c
>
> diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
> index b3e608e..31dc52e 100644
> --- a/arch/arm/imx-common/Makefile
> +++ b/arch/arm/imx-common/Makefile
> @@ -32,6 +32,7 @@ COBJS-y	= iomux-v3.o timer.o cpu.o speed.o
>   COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
>   endif
>   COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
> +COBJS-y += preboot_os.o
>   COBJS	:= $(sort $(COBJS-y))
>
>   SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
> diff --git a/arch/arm/imx-common/preboot_os.c b/arch/arm/imx-common/preboot_os.c
> new file mode 100644
> index 0000000..ed7a9e0
> --- /dev/null
> +++ b/arch/arm/imx-common/preboot_os.c
> @@ -0,0 +1,34 @@
> +/*
> + * Copyright (C) 2012 Boundary Devices Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include<common.h>
> +
> +#if defined(CONFIG_VIDEO_IPUV3)
> +#include<ipu_pixfmt.h>
> +#endif
> +
> +void arch_preboot_os(void)
> +{
> +#if defined(CONFIG_VIDEO_IPUV3)
> +	/* disable video before launching O/S */
> +	ipuv3_fb_shutdown();
> +#endif
> +}

Sorry. This is also a duplicate of a prior e-mail.

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Otavio Salvador]

Hello Eric,

On Fri, Sep 21, 2012 at 5:36 PM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

Did you test it in mx5 too? We seem to need to handle it in mx5 too as
we had hungs in FSL kernel when using framebuffer in U-Boot. We're
using a patch in kernel for workaround it but it seems your fix does
what is need.

Fabio did the workaround patch and knows the details. Added him in CC.

-- 
Otavio Salvador                             O.S. Systems
E-mail: otavio at ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Fabio Estevam]

On Sat, Sep 22, 2012 at 10:42 AM, Otavio Salvador
<otavio@ossystems.com.br> wrote:
> Hello Eric,
>
> On Fri, Sep 21, 2012 at 5:36 PM, Eric Nelson
> <eric.nelson@boundarydevices.com> wrote:
>> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
>
> Did you test it in mx5 too? We seem to need to handle it in mx5 too as
> we had hungs in FSL kernel when using framebuffer in U-Boot. We're
> using a patch in kernel for workaround it but it seems your fix does
> what is need.

I have just tested Eric's series on a mx53loco and it does fix the
kernel hang issue.

I made some comments on this series and hopefully Eric's v2 can get
into 2012.10, since this is a bug fix.

Regards,

Fabio Estevam

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Otavio Salvador]

On Sat, Sep 22, 2012 at 11:37 AM, Fabio Estevam <festevam@gmail.com> wrote:
> On Sat, Sep 22, 2012 at 10:42 AM, Otavio Salvador
> <otavio@ossystems.com.br> wrote:
>> Hello Eric,
>>
>> On Fri, Sep 21, 2012 at 5:36 PM, Eric Nelson
>> <eric.nelson@boundarydevices.com> wrote:
>>> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
>>
>> Did you test it in mx5 too? We seem to need to handle it in mx5 too as
>> we had hungs in FSL kernel when using framebuffer in U-Boot. We're
>> using a patch in kernel for workaround it but it seems your fix does
>> what is need.
>
> I have just tested Eric's series on a mx53loco and it does fix the
> kernel hang issue.
>
> I made some comments on this series and hopefully Eric's v2 can get
> into 2012.10, since this is a bug fix.

Neat.

:-)

-- 
Otavio Salvador                             O.S. Systems
E-mail: otavio at ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Stefano Babic]

On 22/09/2012 16:37, Fabio Estevam wrote:
> On Sat, Sep 22, 2012 at 10:42 AM, Otavio Salvador
> <otavio@ossystems.com.br> wrote:
>> Hello Eric,
>>
>> On Fri, Sep 21, 2012 at 5:36 PM, Eric Nelson
>> <eric.nelson@boundarydevices.com> wrote:
>>> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
>>
>> Did you test it in mx5 too? We seem to need to handle it in mx5 too as
>> we had hungs in FSL kernel when using framebuffer in U-Boot. We're
>> using a patch in kernel for workaround it but it seems your fix does
>> what is need.
> 
> I have just tested Eric's series on a mx53loco and it does fix the
> kernel hang issue.
> 
> I made some comments on this series and hopefully Eric's v2 can get
> into 2012.10, since this is a bug fix.

Ok, I am waiting for V2 and I will push it.

Anyway, a question about the issue. It seems to me that it is not
possible with IPUV3 (I have not tested myself, so my question) to get
the u-boot splashscreen displayed on the LCD until the kernel has
finished to boot. This could be possible (and it is possible on other
SOC) if the IPU is loaded as module instead of statically linked to the
kernel, and if the kernel does not touch the IPU setup. This means also
that it should not disable the clocks used by U-Boot for the IPU.

But I understand from your patch that this way is not possible on
iMX53/MX6, and IPU must be always disabled. Is this correct ?


Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Dirk Behme]

On 23.09.2012 17:56, Stefano Babic wrote:
> On 22/09/2012 16:37, Fabio Estevam wrote:
>> On Sat, Sep 22, 2012 at 10:42 AM, Otavio Salvador
>> <otavio@ossystems.com.br>  wrote:
>>> Hello Eric,
>>>
>>> On Fri, Sep 21, 2012 at 5:36 PM, Eric Nelson
>>> <eric.nelson@boundarydevices.com>  wrote:
>>>> Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com>
>>>
>>> Did you test it in mx5 too? We seem to need to handle it in mx5 too as
>>> we had hungs in FSL kernel when using framebuffer in U-Boot. We're
>>> using a patch in kernel for workaround it but it seems your fix does
>>> what is need.
>>
>> I have just tested Eric's series on a mx53loco and it does fix the
>> kernel hang issue.
>>
>> I made some comments on this series and hopefully Eric's v2 can get
>> into 2012.10, since this is a bug fix.
>
> Ok, I am waiting for V2 and I will push it.
>
> Anyway, a question about the issue. It seems to me that it is not
> possible with IPUV3 (I have not tested myself, so my question) to get
> the u-boot splashscreen displayed on the LCD until the kernel has
> finished to boot. This could be possible (and it is possible on other
> SOC) if the IPU is loaded as module instead of statically linked to the
> kernel, and if the kernel does not touch the IPU setup. This means also
> that it should not disable the clocks used by U-Boot for the IPU.
>
> But I understand from your patch that this way is not possible on
> iMX53/MX6, and IPU must be always disabled. Is this correct ?

I'm no expert on this, so I might be wrong and people will correct me:

No, not always. It's my understanding that at the *moment* we have to 
disable the IPU in U-Boot before jumping into the kernel due to a bug 
in Sascha's kernel IPU driver:

http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/121980.html

http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/122100.html

So from my understanding, this isn't a SOC limitation. But we have to 
do it as long as the kernel's IPU driver isn't fixed.

Sorry if this is wrong ;)

Best regards

Dirk

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Eric Nelson]

Hi Stefano,

On 09/23/2012 08:56 AM, Stefano Babic wrote:
> On 22/09/2012 16:37, Fabio Estevam wrote:
>> On Sat, Sep 22, 2012 at 10:42 AM, Otavio Salvador
>> <otavio@ossystems.com.br>  wrote:
>>> Hello Eric,
>>>
>>> On Fri, Sep 21, 2012 at 5:36 PM, Eric Nelson
>>> <eric.nelson@boundarydevices.com>  wrote:
>>>> Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com>
>>>
>>> Did you test it in mx5 too? We seem to need to handle it in mx5 too as
>>> we had hungs in FSL kernel when using framebuffer in U-Boot. We're
>>> using a patch in kernel for workaround it but it seems your fix does
>>> what is need.
>>
>> I have just tested Eric's series on a mx53loco and it does fix the
>> kernel hang issue.
>>
>> I made some comments on this series and hopefully Eric's v2 can get
>> into 2012.10, since this is a bug fix.
>
> Ok, I am waiting for V2 and I will push it.
>

I'll forward this later today.

> Anyway, a question about the issue. It seems to me that it is not
> possible with IPUV3 (I have not tested myself, so my question) to get
> the u-boot splashscreen displayed on the LCD until the kernel has
> finished to boot. This could be possible (and it is possible on other
> SOC) if the IPU is loaded as module instead of statically linked to the
> kernel, and if the kernel does not touch the IPU setup. This means also
> that it should not disable the clocks used by U-Boot for the IPU.
>

I'm not sure I understand. The splash screen comes up as soon as
the call to ipuv3_fb_init() is made (in board_video_skip() in my
implementation for SABRE Lite).

As it stands, if we leave the IPU running, we'll see garbage on
the display as the kernel re-purposes the RAM used by U-Boot's
frame buffer.

> But I understand from your patch that this way is not possible on
> iMX53/MX6, and IPU must be always disabled. Is this correct ?
>

Sascha responded to a note about this on AKML that the hand-over of
a live FB isn't a supported kernel use case and it's definitely
tricky.

I don't know about the policy, but from a practical matter, the
IPU frame buffer implementation in U-Boot isn't currently up to
that task, since:
	it only supports a single display (i.MX6 can handle 4)
	it only supports 16bpp

Additional functionality would be helpful here.

I would like to see a handoff of display settings from U-Boot to
the kernel, but that's also a tricky thing as long as we're supporting
different mechanisms (DT in main-line and kernel parameters in
older kernels).

Regards,


Eric

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Fabio Estevam]

On Sun, Sep 23, 2012 at 1:46 PM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:

> As it stands, if we leave the IPU running, we'll see garbage on
> the display as the kernel re-purposes the RAM used by U-Boot's
> frame buffer.

And on mx53qsb we get kernel hangs at about half of the boots (tested
on 2.6.35 FSL kernel).

So turning off the IPU in U-boot, as Eric did in this series is an
important fix.

Regards,

Fabio Estevam

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Stefano Babic]

On 23/09/2012 18:46, Eric Nelson wrote:
> Hi Stefano,
> 
> On 09/23/2012 08:56 AM, Stefano Babic wrote:
>> On 22/09/2012 16:37, Fabio Estevam wrote:
>>> On Sat, Sep 22, 2012 at 10:42 AM, Otavio Salvador
>>> <otavio@ossystems.com.br>  wrote:
>>>> Hello Eric,
>>>>
>>>> On Fri, Sep 21, 2012 at 5:36 PM, Eric Nelson
>>>> <eric.nelson@boundarydevices.com>  wrote:
>>>>> Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com>
>>>>
>>>> Did you test it in mx5 too? We seem to need to handle it in mx5 too as
>>>> we had hungs in FSL kernel when using framebuffer in U-Boot. We're
>>>> using a patch in kernel for workaround it but it seems your fix does
>>>> what is need.
>>>
>>> I have just tested Eric's series on a mx53loco and it does fix the
>>> kernel hang issue.
>>>
>>> I made some comments on this series and hopefully Eric's v2 can get
>>> into 2012.10, since this is a bug fix.
>>
>> Ok, I am waiting for V2 and I will push it.
>>
> 
> I'll forward this later today.

Ok

> 
>> Anyway, a question about the issue. It seems to me that it is not
>> possible with IPUV3 (I have not tested myself, so my question) to get
>> the u-boot splashscreen displayed on the LCD until the kernel has
>> finished to boot. This could be possible (and it is possible on other
>> SOC) if the IPU is loaded as module instead of statically linked to the
>> kernel, and if the kernel does not touch the IPU setup. This means also
>> that it should not disable the clocks used by U-Boot for the IPU.
>>
> 
> I'm not sure I understand. The splash screen comes up as soon as
> the call to ipuv3_fb_init() is made (in board_video_skip() in my
> implementation for SABRE Lite).
> 
> As it stands, if we leave the IPU running, we'll see garbage on
> the display as the kernel re-purposes the RAM used by U-Boot's
> frame buffer.

Right, if the kernel reuse the same memory. I am aware that it is not
implemented, I am asking if there some reason to make it impossible.

Some customers want to have a picture shown on the LCD until their
application is running. This makes sense, because the application can
take a lot of time before displaying something on the LCD.

If we reserve some memory for this scope, that is not used by the kernel
later (passing the mem= parameter, for example, or using a .reserve
entry in the board initialization code), we can reach the goal. In
U-Boot we have a single display with 16bit, that means that the memory
consumption is not very high.

> 
>> But I understand from your patch that this way is not possible on
>> iMX53/MX6, and IPU must be always disabled. Is this correct ?
>>
> 
> Sascha responded to a note about this on AKML that the hand-over of
> a live FB isn't a supported kernel use case and it's definitely
> tricky.

And I agree with him, the handover is tricky and not easy, I mean, it
can work with a SOC (it remains tricky..) but not with another one. What
I am saying is not this, but what happens if the IPU is not touched
until the IPU modules are loaded.

> 
> I don't know about the policy, but from a practical matter, the
> IPU frame buffer implementation in U-Boot isn't currently up to
> that task, since:
>     it only supports a single display (i.MX6 can handle 4)
>     it only supports 16bpp
> 
> Additional functionality would be helpful here.

Agree with you. And this is the reason I am not supposing that the
kernel takes the IPU setup made by U-Boot. It could be a nightmare.

> 
> I would like to see a handoff of display settings from U-Boot to
> the kernel, but that's also a tricky thing as long as we're supporting
> different mechanisms (DT in main-line and kernel parameters in
> older kernels).

Yes, and a lot of other things. I know Anatolji implemented this
behavior for a PPC5121, but we cannot generalize. I agree that the
handoff is difficult and not maintainable. My question is different: if
the IPU drivers in kernel are compiled as modules, and I will load them
only after booting, and the framebuffer's memory is reserved so that the
kernel does not touch it, is there still a known reason because the IPU
should not run when we boot the kernel? I know this issue with USB,
maybe we have now the same with the IPU.

Note: this has nothing to do with this patch ;-). I will merge it into
the current release when you push V2.

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 1/2] i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU before bootm

[Sascha Hauer]

On Sun, Sep 23, 2012 at 07:27:41PM +0200, Stefano Babic wrote:
> 
> > 
> > I would like to see a handoff of display settings from U-Boot to
> > the kernel, but that's also a tricky thing as long as we're supporting
> > different mechanisms (DT in main-line and kernel parameters in
> > older kernels).
> 
> Yes, and a lot of other things. I know Anatolji implemented this
> behavior for a PPC5121, but we cannot generalize. I agree that the
> handoff is difficult and not maintainable. My question is different: if
> the IPU drivers in kernel are compiled as modules, and I will load them
> only after booting, and the framebuffer's memory is reserved so that the
> kernel does not touch it, is there still a known reason because the IPU
> should not run when we boot the kernel? I know this issue with USB,
> maybe we have now the same with the IPU.

The clock framework disables all unused clocks in a late_initcall. when
the IPU is compiled as a module, the IPU clock will be one of those.

Sascha


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