[U-Boot] R: Configure a MICRON DDR2 SDRAM MT47H512M4 - 64 Meg x 4 x 8 on MPC8323 custom board

SETTE AGOSTINO - technolabs
2012-10-15T07:52:23Z

Hi all,

first of all I made a mistake: I have two devices DDR2 128Mbitsx16 (2Gbits * 2 devices) on my own hw. I solved the problem changing these in the MPC8323TL.h file under u-boot/include/configs

>> diff MPC8323TL.h u-boot/include/configs/MPC8323TL.h
84a85
> #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)512 << 20)
466a468,472
> #define CONFIG_SYS_IBAT7L ( (CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10 | BATL_MEMCOHERENCE)
> #define CONFIG_SYS_IBAT7U ( (CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
> #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
> #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
>
516,521d521
< /* Nothing in BAT7 */
< #define CONFIG_SYS_IBAT7L (0)
< #define CONFIG_SYS_IBAT7U (0)
< #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
< #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
<
and modifing the file board/TL/mpc8323tl/mpc8323tl.c as follows

>> diff -r board/TL/mpc8323tl/mpc8323tl.c new/board/TL/mpc8323tl/mpc8323tl.c
180a181,182
> im->sysconf.ddrlaw[1].bar = (CONFIG_SYS_DDR_BASE + 0x10000000) & LAWBAR_BAR;
>
206,208c208,210
< im->sysconf.ddrlaw[0].ar =
< LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
< im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
---
> im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
> im->sysconf.ddrlaw[1].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
> im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;

I hope this will help

Best Regards

Agostino Sette

-----Messaggio originale-----
Da: SETTE AGOSTINO - technolabs
Inviato: venerd? 5 ottobre 2012 10.34
Cc: 'u-boot at lists.denx.de'
Oggetto: Configure a MICRON DDR2 SDRAM MT47H512M4 - 64 Meg x 4 x 8 on MPC8323 custom board

Hi all,

I have a problem with MICRON DDR2 SDRAM MT47H512M4 - 64 Meg x 4 x 8 on a MPC8323 custom board.
The size of the DDR causes a hang of the board. If I set the CONFIG_SYS_DDR_SIZE to 512 the u-boot hangs as follows

U-Boot 2012.10-rc1 (Oct 05 2012 - 10:06:41)MPC83XX

Reset Status:

CPU: e300c2, MPC8323E, Rev: 1.1 at 266.667 MHz, CSB: 133.333 MHz
Board: MPC8323_TL
RCWHR 0xa0600000 RCWLR 0x42040083
I2C: ready
DRAM: 512 MiB (DDR2, 32-bit, ECC off, 266.667 MHz)

but if I resize the DDR to 256 everything works properly. Here is the include/configs/MPC8323_TL.h file

#ifndef __CONFIG_H
#define __CONFIG_H

/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC832x 1 /* MPC832x CPU specific */

#define CONFIG_SYS_TEXT_BASE 0xE0000000

#define CONFIG_PCI 1
#define CONFIG_MPC8323_TL 1

/*
* System Clock Setup
*/
#define CONFIG_83XX_CLKIN 66666667 /* in Hz */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
#endif

/*
* Hardware Reset Configuration Word
*/

#define HRCWL_RESERVED 0x20000000

#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_2X1 |\
HRCWL_VCO_1X2 |\
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_2X1 |\
HRCWL_CE_PLL_VCO_DIV_2 |\
HRCWL_CE_PLL_DIV_1X1 |\
HRCWL_CE_TO_PLL_1X3)

#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)

/*
* System IO Config
*/
#define CONFIG_SYS_SICRL 0x00000000

/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xD0000000

/*
* System performance
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
#define CONFIG_SYS_SPCR_OPT 1

/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM 1
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */

#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
/* Determine DDR configuration from I2C interface */
#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
#else
/* Manually set up DDR parameters
*/
#define CONFIG_SYS_DDR_SIZE 512
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80844202 // 1000 0000 0000 0100 0100 0010 0000 0010 OK
#define CONFIG_SYS_DDR_TIMING_0 0x00220802
#define CONFIG_SYS_DDR_TIMING_1 0x3C75F322
#define CONFIG_SYS_DDR_TIMING_2 0x0f9048ca
#define CONFIG_SYS_DDR_TIMING_3 0x00020000 // 1111 1100 0000 0000 0000
#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 // 5431 1098 7654 3210
#define CONFIG_SYS_DDR_MODE 0x44400232 // 0100 0100 0100 0000 0000 0010 0011 0010
#define CONFIG_SYS_DDR_MODE2 0x8000c000 // 1000 0000 0000 1100 0000 000
#define CONFIG_SYS_DDR_INTERVAL 0x03200064
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F // OK
#define CONFIG_SYS_DDR_SDRAM_CFG 0xC3080000 // 0100 0011 0000 1000 0000 0000 0000 0000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 // 0000 0000 0100 0000 0001 0000 0000 0000
#endif

/*
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x03f00000

/*
* The reserved memory
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_RAMBOOT #else #undef CONFIG_SYS_RAMBOOT #endif

#define CONFIG_MISC_INIT_R

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */

/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xD6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
* Local Bus Configuration & Clock Setup */
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00000000

/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xE0000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_BASE_1 0xF0000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */

#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) /* 64 MB window size */

#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FLASH_BASE_1 /* Window base@flash base */
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) /* 64 MB window size */

#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX_SET \
| OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
/* 0xFC006FF7 */

#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE_1 \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX_SET \
| OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
/* 0xFC006FF7 */

#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_FLASH_BASE_1 }
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 2053 /* sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM

/*
* SDRAM on the Local Bus
*/
#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */

#ifdef CONFIG_SYS_LB_SDRAM
#define CONFIG_SYS_LBC_SDRAM_BASE 0xE0000000 /* SDRAM base address */
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */

#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */

/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
/*
* Base Register 2 and Option Register 2 configure SDRAM.
* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
*
* For BR2, need:
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
* port size = 32-bits = BR2[19:20] = 11
* no parity checking = BR2[21:22] = 00
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
* CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
* the top 17 bits of BR2.
*/

/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR2, need:
* 64MB mask for AM, OR2[0:7] = 1111 1100
* XAM, OR2[17:18] = 11
* 9 columns OR2[19-21] = 010
* 13 rows OR2[23-25] = 100
* EAD set for extra time OR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */

#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */

#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723

#endif

/*
* Windows to access PIB via local bus
*/
#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000

/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)

#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1

/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000

/*
* Config on-board EEPROM
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 2 //0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE 0xc0000000
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SKIP_HOST_BRIDGE
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */

#endif /* CONFIG_PCI */

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif

/*
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH

#define CONFIG_ETHPRIME "UEC0"

#define CONFIG_UEC_ETH1 /* ETH3 */

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 88E3018 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 1
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif

#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 Prestera 98DX107 */
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 0
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
#endif
/*
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif

#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */

/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
* Command line configuration.
*/
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ASKENV
#define CONFIG_MII 1
//#define CONFIG_MII_INIT 1
#define CONFIG_CMD_MII

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

#undef CONFIG_WATCHDOG /* watchdog disabled */

/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "MPC8323_TL=> " /* Monitor Command Prompt */

#if (CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */

/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */

/*
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE

/*
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U

/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U

#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE_1 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE_1 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE_1 | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U

#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#else
#define CONFIG_SYS_IBAT5L (0)
#define CONFIG_SYS_IBAT5U (0)
#define CONFIG_SYS_IBAT6L (0)
#define CONFIG_SYS_IBAT6U (0)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#endif

/* Nothing in BAT7 */
#define CONFIG_SYS_IBAT7L (0)
#define CONFIG_SYS_IBAT7U (0)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U

#if (CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif

/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE

#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */

/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */

#define CONFIG_NETDEV "eth1"

#define CONFIG_HOSTNAME mpc8323_tl
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
#define CONFIG_FDTFILE "mpc8323_tl.dtb"

#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200

#define CONFIG_BOOTCOUNT_LIMIT

#define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x)

#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
"ramdiskaddr=1000000\0" \
"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
"console=ttyS0\0" \
"setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"

#define CONFIG_NFSBOOTCOMMAND \
"setenv rootdev /dev/nfs;" \
"run setbootargs;" \
"run setipargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
"setenv rootdev /dev/ram;" \
"run setbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"

#undef MK_STR
#undef XMK_STR

#endif /* __CONFIG_H */

Any help would be appreciated.
Thanks in advance.