From mboxrd@z Thu Jan  1 00:00:00 1970
From: Helmut Raiger <helmut.raiger@hale.at>
Date: Thu, 04 Oct 2012 11:02:24 +0200
Subject: [U-Boot] [u-boot] Adding missing CONFIG_SYS_CACHELINE_SIZE to
	boards definitions
In-Reply-To: <20121004091805.51060cac@amdc308.digital.local>
References: <1345795995-24656-5-git-send-email-l.majewski@samsung.com>
	<20121003230030.GC7623@bill-the-cat>
	<20121004091805.51060cac@amdc308.digital.local>
Message-ID: <506D50A0.4030205@hale.at>
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To: u-boot@lists.denx.de

On 10/04/2012 09:18 AM, Lukasz Majewski wrote:
> Hi Jens and Helmut,
>
>> On Thu, Aug 23, 2012 at 10:13:13PM -0000, Lukasz Majewski wrote:
>>
>>> The restoration of GPT table (both primary and secondary) is now
>>> possible. Simple GUID generation is supported.
>>>
>>> Signed-off-by: Lukasz Majewski<l.majewski@samsung.com>
>>> Signed-off-by: Kyungmin Park<kyungmin.park@samsung.com>
>> While the changes are fine, tt01 and eb_cpux9k2 use CONFIG_PART_EFI
>> and do not set CONFIG_SYS_CACHELINE_SIZE and so fail to build after
>> this patch.  tt01 is easily fixable (it relies on a non-exported
>> define elsewhere to 32) but the eb_cpu9k2 please contact the listed
>> board maintainer to get the define added.
>>
> Would it be possible to add the CONFIG_SYS_CACHELINE_SIZE
> definition to ./include/configs/{tty01|eb_cpux9k2} boards definition?
>
> It would help improving cache alignment and GPT development.
>
> Thanks in advance

Hi Lukasz,

   feel free to do the appropriate changes in the TT-01 platform code 
(explicitly setting CACHELINE_SIZE), I'm currently too busy to do any 
rebasing and testing on the board, we'll have to give it a time slice in 
the near future (to have a few platform things changed) anyway.

Helmut


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