* [U-Boot] [PATCH 1/5] am33xx: move ti i2c baseboard header handling to board/ti/am335x/evm.{c, h}
2012-10-16 15:15 [U-Boot] [PATCH 0/5] am33xx: support non-ti boards Peter Korsgaard
@ 2012-10-16 15:15 ` Peter Korsgaard
2012-10-16 15:35 ` Tom Rini
2012-10-16 15:15 ` [U-Boot] [PATCH 2/5] am335x/evm.c: don't make wdtimer/uart_base global Peter Korsgaard
` (3 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Peter Korsgaard @ 2012-10-16 15:15 UTC (permalink / raw)
To: u-boot
The i2c header is specific to ti(-derived) boards, and not generic for all
am335x boards.
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
---
arch/arm/cpu/armv7/am33xx/board.c | 235 --------------------
arch/arm/include/asm/arch-am33xx/sys_proto.h | 27 ---
board/ti/am335x/Makefile | 1 +
.../armv7/am33xx/board.c => board/ti/am335x/evm.c | 33 +--
.../sys_proto.h => board/ti/am335x/evm.h | 24 +-
board/ti/am335x/mux.c | 1 +
6 files changed, 10 insertions(+), 311 deletions(-)
copy arch/arm/cpu/armv7/am33xx/board.c => board/ti/am335x/evm.c (90%)
copy arch/arm/include/asm/arch-am33xx/sys_proto.h => board/ti/am335x/evm.h (75%)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 978b184..8280b35 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -36,9 +36,6 @@
DECLARE_GLOBAL_DATA_PTR;
-struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-
static const struct gpio_bank gpio_bank_am33xx[4] = {
{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -48,148 +45,6 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
-/* MII mode defines */
-#define MII_MODE_ENABLE 0x0
-#define RGMII_MODE_ENABLE 0xA
-
-/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN 7
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-static struct am335x_baseboard_id __attribute__((section (".data"))) header;
-
-static inline int board_is_bone(void)
-{
- return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_sk(void)
-{
- return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
-}
-
-/*
- * Read header information from EEPROM into global structure.
- */
-static int read_eeprom(void)
-{
- /* Check if baseboard eeprom is available */
- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
- puts("Could not probe the EEPROM; something fundamentally "
- "wrong on the I2C bus.\n");
- return -ENODEV;
- }
-
- /* read the eeprom using i2c */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
- sizeof(header))) {
- puts("Could not read the EEPROM; something fundamentally"
- " wrong on the I2C bus.\n");
- return -EIO;
- }
-
- if (header.magic != 0xEE3355AA) {
- /*
- * read the eeprom using i2c again,
- * but use only a 1 byte address
- */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
- (uchar *)&header, sizeof(header))) {
- puts("Could not read the EEPROM; something "
- "fundamentally wrong on the I2C bus.\n");
- return -EIO;
- }
-
- if (header.magic != 0xEE3355AA) {
- printf("Incorrect magic number (0x%x) in EEPROM\n",
- header.magic);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-/* UART Defines */
-#ifdef CONFIG_SPL_BUILD
-#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
-#endif
-
-/*
- * Determine what type of DDR we have.
- */
-static short inline board_memory_type(void)
-{
- /* The following boards are known to use DDR3. */
- if (board_is_evm_sk())
- return EMIF_REG_SDRAM_TYPE_DDR3;
-
- return EMIF_REG_SDRAM_TYPE_DDR2;
-}
-
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
-{
- /* WDT1 is already running when the bootloader gets control
- * Disable it to avoid "random" resets
- */
- writel(0xAAAA, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
- writel(0x5555, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
-
-#ifdef CONFIG_SPL_BUILD
- /* Setup the PLLs and the clocks for the peripherals */
- pll_init();
-
- /* UART softreset */
- u32 regVal;
-
- enable_uart0_pin_mux();
-
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_RESET;
- writel(regVal, &uart_base->uartsyscfg);
- while ((readl(&uart_base->uartsyssts) &
- UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
- ;
-
- /* Disable smart idle */
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_SMART_IDLE_EN;
- writel(regVal, &uart_base->uartsyscfg);
-
- gd = &gdata;
-
- preloader_console_init();
-
- /* Initalize the board header */
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
-
- enable_board_pin_mux(&header);
- if (board_is_evm_sk()) {
- /*
- * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
- * This is safe enough to do on older revs.
- */
- gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
- gpio_direction_output(GPIO_DDR_VTT_EN, 1);
- }
-
- config_ddr(board_memory_type());
-#endif
-}
-
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
@@ -208,93 +63,3 @@ void setup_clocks_for_console(void)
/* Not yet implemented */
return;
}
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
-
- gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_id = 0,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_id = 1,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = AM335X_CPSW_MDIO_BASE,
- .cpsw_base = AM335X_CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
- debug("<ethaddr> not set. Reading from E-fuse\n");
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (is_valid_ether_addr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
- else
- return -1;
- }
-
- if (board_is_bone()) {
- writel(MII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
- PHY_INTERFACE_MODE_MII;
- } else {
- writel(RGMII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
- PHY_INTERFACE_MODE_RGMII;
- }
-
- return cpsw_register(&cpsw_data);
-}
-#endif
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 819ea65..9cf35e0 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -19,24 +19,6 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-/*
- * AM335x parts define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR 3
-#define HDR_ETH_ALEN 6
-#define HDR_NAME_LEN 8
-
-struct am335x_baseboard_id {
- unsigned int magic;
- char name[HDR_NAME_LEN];
- char version[4];
- char serial[12];
- char config[32];
- char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
-
#define BOARD_REV_ID 0x0
u32 get_cpu_rev(void);
@@ -51,13 +33,4 @@ u32 get_device_type(void);
void setup_clocks_for_console(void);
void ddr_pll_config(unsigned int ddrpll_M);
-/*
- * We have three pin mux functions that must exist. We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(struct am335x_baseboard_id *header);
#endif
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
index ca50eef..add3bec 100644
--- a/board/ti/am335x/Makefile
+++ b/board/ti/am335x/Makefile
@@ -22,6 +22,7 @@ ifdef CONFIG_SPL_BUILD
COBJS := mux.o
endif
+COBJS += evm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/board/ti/am335x/evm.c
similarity index 90%
copy from arch/arm/cpu/armv7/am33xx/board.c
copy to board/ti/am335x/evm.c
index 978b184..a1fa443 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/board/ti/am335x/evm.c
@@ -1,7 +1,7 @@
/*
- * board.c
+ * evm.c
*
- * Common board functions for AM33XX based boards
+ * Board functions for TI AM33XX boards
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
@@ -33,21 +33,13 @@
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
+#include "evm.h"
DECLARE_GLOBAL_DATA_PTR;
struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-static const struct gpio_bank gpio_bank_am33xx[4] = {
- { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
- { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
-
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
#define RGMII_MODE_ENABLE 0xA
@@ -190,25 +182,6 @@ void s_init(void)
#endif
}
-#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
- int ret;
-
- ret = omap_mmc_init(0, 0, 0);
- if (ret)
- return ret;
-
- return omap_mmc_init(1, 0, 0);
-}
-#endif
-
-void setup_clocks_for_console(void)
-{
- /* Not yet implemented */
- return;
-}
-
/*
* Basic board specific setup. Pinmux has been handled already.
*/
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/board/ti/am335x/evm.h
similarity index 75%
copy from arch/arm/include/asm/arch-am33xx/sys_proto.h
copy to board/ti/am335x/evm.h
index 819ea65..c4cfb85 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/board/ti/am335x/evm.h
@@ -1,7 +1,7 @@
/*
- * sys_proto.h
+ * evm.h
*
- * System information header
+ * TI AM33XX boards information header
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
@@ -16,11 +16,11 @@
* GNU General Public License for more details.
*/
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
+#ifndef _AM335X_EVM_H_
+#define _AM335X_EVM_H_
/*
- * AM335x parts define a system EEPROM that defines certain sub-fields.
+ * TI AM335x parts define a system EEPROM that defines certain sub-fields.
* We use these fields to in turn see what board we are on, and what
* that might require us to set or not set.
*/
@@ -37,20 +37,6 @@ struct am335x_baseboard_id {
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
};
-#define BOARD_REV_ID 0x0
-
-u32 get_cpu_rev(void);
-u32 get_sysboot_value(void);
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void);
-#endif
-
-extern struct ctrl_stat *cstat;
-u32 get_device_type(void);
-void setup_clocks_for_console(void);
-void ddr_pll_config(unsigned int ddrpll_M);
-
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 80becd5..06d4384 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -18,6 +18,7 @@
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <i2c.h>
+#include "evm.h"
#define MUX_CFG(value, offset) \
__raw_writel(value, (CTRL_BASE + offset));
--
1.7.10.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH 1/5] am33xx: move ti i2c baseboard header handling to board/ti/am335x/evm.{c, h}
2012-10-16 15:15 ` [U-Boot] [PATCH 1/5] am33xx: move ti i2c baseboard header handling to board/ti/am335x/evm.{c, h} Peter Korsgaard
@ 2012-10-16 15:35 ` Tom Rini
2012-10-17 15:46 ` Peter Korsgaard
0 siblings, 1 reply; 15+ messages in thread
From: Tom Rini @ 2012-10-16 15:35 UTC (permalink / raw)
To: u-boot
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 10/16/12 08:15, Peter Korsgaard wrote:
> The i2c header is specific to ti(-derived) boards, and not generic
> for all am335x boards.
>
> Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> ---
> arch/arm/cpu/armv7/am33xx/board.c | 235
> -------------------- arch/arm/include/asm/arch-am33xx/sys_proto.h
> | 27 --- board/ti/am335x/Makefile |
> 1 + .../armv7/am33xx/board.c => board/ti/am335x/evm.c | 33 +--
> .../sys_proto.h => board/ti/am335x/evm.h | 24 +-
> board/ti/am335x/mux.c | 1 + 6 files
> changed, 10 insertions(+), 311 deletions(-) copy
> arch/arm/cpu/armv7/am33xx/board.c => board/ti/am335x/evm.c (90%)
> copy arch/arm/include/asm/arch-am33xx/sys_proto.h =>
> board/ti/am335x/evm.h (75%)
I'd like to see it as board/ti/am33xx/board.[ch] but other than that I
can see where you're coming from. Can you post a WIP version of your
s_init / board_init? I'd like to see what maybe we should call __weak
or try and restructure a bit more. Thanks!
- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://www.enigmail.net/
iQIcBAEBAgAGBQJQfX6vAAoJENk4IS6UOR1W6h0QAIhAoLVANPWvrtH+MP5S6WBD
G4kqyaefd0AJmCNX9CXMT+Qx/rjMqM/bPr047K80xj0XpC3GLaGMiZJbnjXoFwcg
bm0hd3ogK9AeSReONsMjk5qndLtBEfVniGDPi33atzimEUjsHYZdc9zR0SbP7+il
7n8YlZQoCH6KytZNn1/REXQQfs1ZY+zRA5uUxgqIpejCBTjoQXItQ1zURXUftD76
Rufk4vzEEvSVeQ/RIW3xhSLPzUTLjI1dBfZOgK5tzCb5ltxE9C8bOpIqt+ISuh73
1nLsJnxDQF5TR1WHyyX8yIN8FVow/eglaHCfi3y0NZdkRiFWlkN+rhL+XqNIOfiP
/ddZ41Vo5oA5t4wxWktd+GN6gSEivfjPw8m8EoJCSNdBgZi1yDD8YPshVcVQm29f
EiHOi1ZOzCkWk5m12XVRl32LxtikEOjb2Icw2tjZ187s4Ow3S3H6+dseRKkgqxk8
WrnVt64mr8LimdeEZShWOcm+0iFMAdYzmmHmtGL+8lqyeAPoHIQ0LGRnjNarbtXJ
EAcremyRzIgtnMGMDwDpWczXoH+sYfPaNSzT9tJ39quWkn5f7KLU5zC40BnxkAjh
0fxmdec6TN2a29sfPL3fXiD1e7Nvirem8jJrOcNyP90fGx3cwfRkNrQgLitYpY/w
VtncBdacDWaqaTtSGDlR
=4apt
-----END PGP SIGNATURE-----
^ permalink raw reply [flat|nested] 15+ messages in thread* [U-Boot] [PATCH 1/5] am33xx: move ti i2c baseboard header handling to board/ti/am335x/evm.{c, h}
2012-10-16 15:35 ` Tom Rini
@ 2012-10-17 15:46 ` Peter Korsgaard
2012-10-17 15:55 ` Tom Rini
0 siblings, 1 reply; 15+ messages in thread
From: Peter Korsgaard @ 2012-10-17 15:46 UTC (permalink / raw)
To: u-boot
>>>>> "Tom" == Tom Rini <trini@ti.com> writes:
Tom> I'd like to see it as board/ti/am33xx/board.[ch] but other than that I
Tom> can see where you're coming from.
Ok, fine - Will use board.{c,h} in next version.
Tom> Can you post a WIP version of your s_init / board_init? I'd like
Tom> to see what maybe we should call __weak or try and restructure a
Tom> bit more. Thanks!
Sorry, I only just started the mainline porting work last Friday next to
other tasks, so right now it basically looks like the ti ones except for
the eeprom handling, but I'll need to add fpga configuration handling
and a redundant boot setup using the watchdog (E.G. fallback to backup
u-boot/linux/rootfs if the system didn't start before watchdog fired).
Again, I haven't been able to do any real tests on this board because of
missing nand support. Are you aware of any in progress effort on this
within TI?
--
Bye, Peter Korsgaard
^ permalink raw reply [flat|nested] 15+ messages in thread* [U-Boot] [PATCH 1/5] am33xx: move ti i2c baseboard header handling to board/ti/am335x/evm.{c, h}
2012-10-17 15:46 ` Peter Korsgaard
@ 2012-10-17 15:55 ` Tom Rini
2012-10-17 19:24 ` Peter Korsgaard
0 siblings, 1 reply; 15+ messages in thread
From: Tom Rini @ 2012-10-17 15:55 UTC (permalink / raw)
To: u-boot
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 10/17/12 08:46, Peter Korsgaard wrote:
>>>>>> "Tom" == Tom Rini <trini@ti.com> writes:
>
>
> Tom> I'd like to see it as board/ti/am33xx/board.[ch] but other
> than that I Tom> can see where you're coming from.
>
> Ok, fine - Will use board.{c,h} in next version.
>
> Tom> Can you post a WIP version of your s_init / board_init? I'd
> like Tom> to see what maybe we should call __weak or try and
> restructure a Tom> bit more. Thanks!
>
> Sorry, I only just started the mainline porting work last Friday
> next to other tasks, so right now it basically looks like the ti
> ones except for the eeprom handling, but I'll need to add fpga
> configuration handling and a redundant boot setup using the
> watchdog (E.G. fallback to backup u-boot/linux/rootfs if the system
> didn't start before watchdog fired).
Sounds good.
> Again, I haven't been able to do any real tests on this board
> because of missing nand support. Are you aware of any in progress
> effort on this within TI?
Yes, Ilya Yanok is working on that, as well as finishing MUSB support
currently.
- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://www.enigmail.net/
iQIcBAEBAgAGBQJQftT0AAoJENk4IS6UOR1WcU4QAIiIrVc4kAfIucvXSbIjhLXp
aXNvDM3ulopIm6jRW5rXkcSpRrkCRVpOC4waqncR3Wj4RS7AMdPqE4VBmBHtLhLK
hcoSkn5G2VFVmAArsNrnp070OqlGWApyfaM47TEkNdV93ah/ZXpuyd2y+AUFpOoC
uTgU4Y0DWgDQx2+PBGPTzCVo5TVdEtGEnkYWcTtnOOx7dB+QumF2Vy/HDPmUFnmo
BYD+D9t5XX1xOUL9aiKGCthuwa+F22/CNUwOjRkS1h4LnoGBHC8Zy+kEMs+uvXR/
Mn8t5GFL8zi3wh7sOw0MvcyoLrcdV/9OOf32uVobL9IXMIFVUjv+7YXrlxLYUmmN
M9flwEddKnzs92a7KGAY9LZPL/4nqZqqGHRyMewDlJaRMGMrgudI50NxKP5yHdP1
O/m9W4COk9GLw4Cwg3o0/ATjwjT6MvKziV74yih24Qjh5Ti08e5c9fDBeoFnUBsF
PwnSZRcyFkThJBJxJ6jFdb/mbMNNG0Fm/a0IYn1WQk2misOwKfDzVIBdYI4Ej+BP
IAuEXppsNOS1lO4L8JEG/PNo8g8XxJb+TjK5qowGCXrdNIJpB2X/k6vf1ayAZgat
Gu7YYoU+XzzFe4VPK4RCV9ppj7fpd+Jf42+FMOCyjuzc38sprWienBhPJ9JCfN9e
1BK0VkitJBLWhwjtlThH
=7CTb
-----END PGP SIGNATURE-----
^ permalink raw reply [flat|nested] 15+ messages in thread* [U-Boot] [PATCH 1/5] am33xx: move ti i2c baseboard header handling to board/ti/am335x/evm.{c, h}
2012-10-17 15:55 ` Tom Rini
@ 2012-10-17 19:24 ` Peter Korsgaard
0 siblings, 0 replies; 15+ messages in thread
From: Peter Korsgaard @ 2012-10-17 19:24 UTC (permalink / raw)
To: u-boot
>>>>> "Tom" == Tom Rini <trini@ti.com> writes:
Hi,
>> Again, I haven't been able to do any real tests on this board
>> because of missing nand support. Are you aware of any in progress
>> effort on this within TI?
Tom> Yes, Ilya Yanok is working on that, as well as finishing MUSB
Tom> support currently.
Great! Ilya, what is current status of this? Could you post your changes
then I will be happy to test it.
--
Bye, Peter Korsgaard
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/5] am335x/evm.c: don't make wdtimer/uart_base global
2012-10-16 15:15 [U-Boot] [PATCH 0/5] am33xx: support non-ti boards Peter Korsgaard
2012-10-16 15:15 ` [U-Boot] [PATCH 1/5] am33xx: move ti i2c baseboard header handling to board/ti/am335x/evm.{c, h} Peter Korsgaard
@ 2012-10-16 15:15 ` Peter Korsgaard
2012-10-16 15:15 ` [U-Boot] [PATCH 3/5] am33xx/board: use cpu_mmc_init() for default mmc initialization Peter Korsgaard
` (2 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Peter Korsgaard @ 2012-10-16 15:15 UTC (permalink / raw)
To: u-boot
Only used here (and for SPL).
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
---
board/ti/am335x/evm.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/ti/am335x/evm.c b/board/ti/am335x/evm.c
index a1fa443..9dd372c 100644
--- a/board/ti/am335x/evm.c
+++ b/board/ti/am335x/evm.c
@@ -37,8 +37,10 @@
DECLARE_GLOBAL_DATA_PTR;
-struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+#ifdef CONFIG_SPL_BUILD
+static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+#endif
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
--
1.7.10.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH 3/5] am33xx/board: use cpu_mmc_init() for default mmc initialization
2012-10-16 15:15 [U-Boot] [PATCH 0/5] am33xx: support non-ti boards Peter Korsgaard
2012-10-16 15:15 ` [U-Boot] [PATCH 1/5] am33xx: move ti i2c baseboard header handling to board/ti/am335x/evm.{c, h} Peter Korsgaard
2012-10-16 15:15 ` [U-Boot] [PATCH 2/5] am335x/evm.c: don't make wdtimer/uart_base global Peter Korsgaard
@ 2012-10-16 15:15 ` Peter Korsgaard
2012-10-16 15:36 ` Tom Rini
2012-10-16 15:15 ` [U-Boot] [PATCH 4/5] am33xx: move generic parts of pinmux handling out from board/ti/am335x Peter Korsgaard
2012-10-16 15:15 ` [U-Boot] [PATCH 5/5] am33xx: support board specific ddr settings Peter Korsgaard
4 siblings, 1 reply; 15+ messages in thread
From: Peter Korsgaard @ 2012-10-16 15:15 UTC (permalink / raw)
To: u-boot
So platforms can override it with board_mmc_init().
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
---
arch/arm/cpu/armv7/am33xx/board.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 8280b35..e4c123c 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -46,10 +46,10 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
+int cpu_mmc_init(bd_t *bis)
{
int ret;
-
+
ret = omap_mmc_init(0, 0, 0);
if (ret)
return ret;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH 3/5] am33xx/board: use cpu_mmc_init() for default mmc initialization
2012-10-16 15:15 ` [U-Boot] [PATCH 3/5] am33xx/board: use cpu_mmc_init() for default mmc initialization Peter Korsgaard
@ 2012-10-16 15:36 ` Tom Rini
2012-10-16 17:37 ` Peter Korsgaard
0 siblings, 1 reply; 15+ messages in thread
From: Tom Rini @ 2012-10-16 15:36 UTC (permalink / raw)
To: u-boot
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 10/16/12 08:15, Peter Korsgaard wrote:
> So platforms can override it with board_mmc_init().
>
> Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> ---
> arch/arm/cpu/armv7/am33xx/board.c | 4 ++-- 1 file changed, 2
> insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/am33xx/board.c
> b/arch/arm/cpu/armv7/am33xx/board.c index 8280b35..e4c123c 100644
> --- a/arch/arm/cpu/armv7/am33xx/board.c +++
> b/arch/arm/cpu/armv7/am33xx/board.c @@ -46,10 +46,10 @@ static
> const struct gpio_bank gpio_bank_am33xx[4] = { const struct
> gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
>
> #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) -int
> board_mmc_init(bd_t *bis) +int cpu_mmc_init(bd_t *bis) { int ret; -
> + ret = omap_mmc_init(0, 0, 0); if (ret) return ret;
>
What does this look like on your port?
- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://www.enigmail.net/
iQIcBAEBAgAGBQJQfX8YAAoJENk4IS6UOR1WuekP/R464jzIEVy/EhAT8tqtVKwn
S0F7657nKauMO1ojsUN6xVE32efEIKRosE3Q5T5VROgqtoOn8HPs00zIRxvQj9Ar
wQloaIc2W+57+oLuV5y3wsD/XN+XMWt3/XUap2BM6dEy+vzb8TEDml2Yfq4TJXxz
RXFb2MlGuhEOkklT0q1Kt3S6oRYmNEq84ccfVps3+S+WqEOuAAcHHEFx6BtUDTrR
aiXHknsGRcOm5cLLC8umrrf6+3mzsEcIPrkXrh8Ep+rkXKG4lKCqzBjbQm5tNeDh
TX46Rz1cLGA433DyJFRbv6irVs4hQK0H+Hyxq8pHEsKBRK2UVBWbG9X424c7EG3E
77ceKzaEeZiY3CNjUSf9KnJ+f7aC8e3s6InqO+qATTcUd3QJtLWEiqNHlfowm9q+
3y1GHzjQM1vHBpb3KP21qvg/MoB6J85Snmv5aENFSuWb9/lM0qyH/EBUZS6eS9u/
W+7N8nuT3DWX3KapPiTi2a8X97qbLmKK99lcycjaGAxj1a01/ltkLAs88k4c6Jwz
w9JeG7TX8QevKGnYocoRyTcORVF0+Sh2ejRDWcFW2tbRLQwrCX58NoTKTUIWMxjT
tqYojRTLlD1gvZTuVNvi6bM1QTpMNWpwppXVSYlKPFBAAgaF2/9N+0mWrRbpcoZR
A40pv5+ojvxFWbcyScmA
=/8cX
-----END PGP SIGNATURE-----
^ permalink raw reply [flat|nested] 15+ messages in thread* [U-Boot] [PATCH 3/5] am33xx/board: use cpu_mmc_init() for default mmc initialization
2012-10-16 15:36 ` Tom Rini
@ 2012-10-16 17:37 ` Peter Korsgaard
0 siblings, 0 replies; 15+ messages in thread
From: Peter Korsgaard @ 2012-10-16 17:37 UTC (permalink / raw)
To: u-boot
>>>>> "Tom" == Tom Rini <trini@ti.com> writes:
Hi,
>> #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) -int
>> board_mmc_init(bd_t *bis) +int cpu_mmc_init(bd_t *bis) { int ret; -
>> + ret = omap_mmc_init(0, 0, 0); if (ret) return ret;
>>
Tom> What does this look like on your port?
I don't have any, the board doesn't have mmc ;)
This is purely cleanup to better match the other (sub-)archs and make it
possible to provide a board override. I don't particular know if anyone
will ever need it on am33xx, but it doesn't cost anything and
historically various boards have used these for pinmux / regulator
handling / card detect gpio / ..
--
Bye, Peter Korsgaard
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 4/5] am33xx: move generic parts of pinmux handling out from board/ti/am335x
2012-10-16 15:15 [U-Boot] [PATCH 0/5] am33xx: support non-ti boards Peter Korsgaard
` (2 preceding siblings ...)
2012-10-16 15:15 ` [U-Boot] [PATCH 3/5] am33xx/board: use cpu_mmc_init() for default mmc initialization Peter Korsgaard
@ 2012-10-16 15:15 ` Peter Korsgaard
2012-10-16 15:15 ` [U-Boot] [PATCH 5/5] am33xx: support board specific ddr settings Peter Korsgaard
4 siblings, 0 replies; 15+ messages in thread
From: Peter Korsgaard @ 2012-10-16 15:15 UTC (permalink / raw)
To: u-boot
So they are available for other boards.
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
---
arch/arm/cpu/armv7/am33xx/Makefile | 1 +
arch/arm/cpu/armv7/am33xx/mux.c | 33 ++++
arch/arm/include/asm/arch-am33xx/mux.h | 261 ++++++++++++++++++++++++++++++++
board/ti/am335x/mux.c | 249 +-----------------------------
4 files changed, 296 insertions(+), 248 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/mux.c
create mode 100644 arch/arm/include/asm/arch-am33xx/mux.h
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index 7768912..74875b3 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -21,6 +21,7 @@ COBJS += sys_info.o
COBJS += ddr.o
COBJS += emif4.o
COBJS += board.o
+COBJS += mux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/am33xx/mux.c b/arch/arm/cpu/armv7/am33xx/mux.c
new file mode 100644
index 0000000..2ded472
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/mux.c
@@ -0,0 +1,33 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
+{
+ int i;
+
+ if (!mod_pin_mux)
+ return;
+
+ for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
+ MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+}
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
new file mode 100644
index 0000000..aed6b00
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -0,0 +1,261 @@
+/*
+ * mux.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_H_
+#define _MUX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset) \
+ __raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL (0x1 << 6)
+#define RXACTIVE (0x1 << 5)
+#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
+#define PULLUDEN (0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
+#define MODE(val) val /* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+ int gpmc_ad0;
+ int gpmc_ad1;
+ int gpmc_ad2;
+ int gpmc_ad3;
+ int gpmc_ad4;
+ int gpmc_ad5;
+ int gpmc_ad6;
+ int gpmc_ad7;
+ int gpmc_ad8;
+ int gpmc_ad9;
+ int gpmc_ad10;
+ int gpmc_ad11;
+ int gpmc_ad12;
+ int gpmc_ad13;
+ int gpmc_ad14;
+ int gpmc_ad15;
+ int gpmc_a0;
+ int gpmc_a1;
+ int gpmc_a2;
+ int gpmc_a3;
+ int gpmc_a4;
+ int gpmc_a5;
+ int gpmc_a6;
+ int gpmc_a7;
+ int gpmc_a8;
+ int gpmc_a9;
+ int gpmc_a10;
+ int gpmc_a11;
+ int gpmc_wait0;
+ int gpmc_wpn;
+ int gpmc_be1n;
+ int gpmc_csn0;
+ int gpmc_csn1;
+ int gpmc_csn2;
+ int gpmc_csn3;
+ int gpmc_clk;
+ int gpmc_advn_ale;
+ int gpmc_oen_ren;
+ int gpmc_wen;
+ int gpmc_be0n_cle;
+ int lcd_data0;
+ int lcd_data1;
+ int lcd_data2;
+ int lcd_data3;
+ int lcd_data4;
+ int lcd_data5;
+ int lcd_data6;
+ int lcd_data7;
+ int lcd_data8;
+ int lcd_data9;
+ int lcd_data10;
+ int lcd_data11;
+ int lcd_data12;
+ int lcd_data13;
+ int lcd_data14;
+ int lcd_data15;
+ int lcd_vsync;
+ int lcd_hsync;
+ int lcd_pclk;
+ int lcd_ac_bias_en;
+ int mmc0_dat3;
+ int mmc0_dat2;
+ int mmc0_dat1;
+ int mmc0_dat0;
+ int mmc0_clk;
+ int mmc0_cmd;
+ int mii1_col;
+ int mii1_crs;
+ int mii1_rxerr;
+ int mii1_txen;
+ int mii1_rxdv;
+ int mii1_txd3;
+ int mii1_txd2;
+ int mii1_txd1;
+ int mii1_txd0;
+ int mii1_txclk;
+ int mii1_rxclk;
+ int mii1_rxd3;
+ int mii1_rxd2;
+ int mii1_rxd1;
+ int mii1_rxd0;
+ int rmii1_refclk;
+ int mdio_data;
+ int mdio_clk;
+ int spi0_sclk;
+ int spi0_d0;
+ int spi0_d1;
+ int spi0_cs0;
+ int spi0_cs1;
+ int ecap0_in_pwm0_out;
+ int uart0_ctsn;
+ int uart0_rtsn;
+ int uart0_rxd;
+ int uart0_txd;
+ int uart1_ctsn;
+ int uart1_rtsn;
+ int uart1_rxd;
+ int uart1_txd;
+ int i2c0_sda;
+ int i2c0_scl;
+ int mcasp0_aclkx;
+ int mcasp0_fsx;
+ int mcasp0_axr0;
+ int mcasp0_ahclkr;
+ int mcasp0_aclkr;
+ int mcasp0_fsr;
+ int mcasp0_axr1;
+ int mcasp0_ahclkx;
+ int xdma_event_intr0;
+ int xdma_event_intr1;
+ int nresetin_out;
+ int porz;
+ int nnmi;
+ int osc0_in;
+ int osc0_out;
+ int rsvd1;
+ int tms;
+ int tdi;
+ int tdo;
+ int tck;
+ int ntrst;
+ int emu0;
+ int emu1;
+ int osc1_in;
+ int osc1_out;
+ int pmic_power_en;
+ int rtc_porz;
+ int rsvd2;
+ int ext_wakeup;
+ int enz_kaldo_1p8v;
+ int usb0_dm;
+ int usb0_dp;
+ int usb0_ce;
+ int usb0_id;
+ int usb0_vbus;
+ int usb0_drvvbus;
+ int usb1_dm;
+ int usb1_dp;
+ int usb1_ce;
+ int usb1_id;
+ int usb1_vbus;
+ int usb1_drvvbus;
+ int ddr_resetn;
+ int ddr_csn0;
+ int ddr_cke;
+ int ddr_ck;
+ int ddr_nck;
+ int ddr_casn;
+ int ddr_rasn;
+ int ddr_wen;
+ int ddr_ba0;
+ int ddr_ba1;
+ int ddr_ba2;
+ int ddr_a0;
+ int ddr_a1;
+ int ddr_a2;
+ int ddr_a3;
+ int ddr_a4;
+ int ddr_a5;
+ int ddr_a6;
+ int ddr_a7;
+ int ddr_a8;
+ int ddr_a9;
+ int ddr_a10;
+ int ddr_a11;
+ int ddr_a12;
+ int ddr_a13;
+ int ddr_a14;
+ int ddr_a15;
+ int ddr_odt;
+ int ddr_d0;
+ int ddr_d1;
+ int ddr_d2;
+ int ddr_d3;
+ int ddr_d4;
+ int ddr_d5;
+ int ddr_d6;
+ int ddr_d7;
+ int ddr_d8;
+ int ddr_d9;
+ int ddr_d10;
+ int ddr_d11;
+ int ddr_d12;
+ int ddr_d13;
+ int ddr_d14;
+ int ddr_d15;
+ int ddr_dqm0;
+ int ddr_dqm1;
+ int ddr_dqs0;
+ int ddr_dqsn0;
+ int ddr_dqs1;
+ int ddr_dqsn1;
+ int ddr_vref;
+ int ddr_vtp;
+ int ddr_strben0;
+ int ddr_strben1;
+ int ain7;
+ int ain6;
+ int ain5;
+ int ain4;
+ int ain3;
+ int ain2;
+ int ain1;
+ int ain0;
+ int vrefp;
+ int vrefn;
+};
+
+struct module_pin_mux {
+ short reg_offset;
+ unsigned char val;
+};
+
+/* Pad control register offset */
+#define PAD_CTRL_BASE 0x800
+#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
+ (PAD_CTRL_BASE))->x)
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
+
+#endif
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 06d4384..9eefc51 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -16,244 +16,11 @@
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
#include "evm.h"
-#define MUX_CFG(value, offset) \
- __raw_writel(value, (CTRL_BASE + offset));
-
-/* PAD Control Fields */
-#define SLEWCTRL (0x1 << 6)
-#define RXACTIVE (0x1 << 5)
-#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
-#define PULLUDEN (0x0 << 3) /* Pull up enabled */
-#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
-#define MODE(val) val /* used for Readability */
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
- int gpmc_ad0;
- int gpmc_ad1;
- int gpmc_ad2;
- int gpmc_ad3;
- int gpmc_ad4;
- int gpmc_ad5;
- int gpmc_ad6;
- int gpmc_ad7;
- int gpmc_ad8;
- int gpmc_ad9;
- int gpmc_ad10;
- int gpmc_ad11;
- int gpmc_ad12;
- int gpmc_ad13;
- int gpmc_ad14;
- int gpmc_ad15;
- int gpmc_a0;
- int gpmc_a1;
- int gpmc_a2;
- int gpmc_a3;
- int gpmc_a4;
- int gpmc_a5;
- int gpmc_a6;
- int gpmc_a7;
- int gpmc_a8;
- int gpmc_a9;
- int gpmc_a10;
- int gpmc_a11;
- int gpmc_wait0;
- int gpmc_wpn;
- int gpmc_be1n;
- int gpmc_csn0;
- int gpmc_csn1;
- int gpmc_csn2;
- int gpmc_csn3;
- int gpmc_clk;
- int gpmc_advn_ale;
- int gpmc_oen_ren;
- int gpmc_wen;
- int gpmc_be0n_cle;
- int lcd_data0;
- int lcd_data1;
- int lcd_data2;
- int lcd_data3;
- int lcd_data4;
- int lcd_data5;
- int lcd_data6;
- int lcd_data7;
- int lcd_data8;
- int lcd_data9;
- int lcd_data10;
- int lcd_data11;
- int lcd_data12;
- int lcd_data13;
- int lcd_data14;
- int lcd_data15;
- int lcd_vsync;
- int lcd_hsync;
- int lcd_pclk;
- int lcd_ac_bias_en;
- int mmc0_dat3;
- int mmc0_dat2;
- int mmc0_dat1;
- int mmc0_dat0;
- int mmc0_clk;
- int mmc0_cmd;
- int mii1_col;
- int mii1_crs;
- int mii1_rxerr;
- int mii1_txen;
- int mii1_rxdv;
- int mii1_txd3;
- int mii1_txd2;
- int mii1_txd1;
- int mii1_txd0;
- int mii1_txclk;
- int mii1_rxclk;
- int mii1_rxd3;
- int mii1_rxd2;
- int mii1_rxd1;
- int mii1_rxd0;
- int rmii1_refclk;
- int mdio_data;
- int mdio_clk;
- int spi0_sclk;
- int spi0_d0;
- int spi0_d1;
- int spi0_cs0;
- int spi0_cs1;
- int ecap0_in_pwm0_out;
- int uart0_ctsn;
- int uart0_rtsn;
- int uart0_rxd;
- int uart0_txd;
- int uart1_ctsn;
- int uart1_rtsn;
- int uart1_rxd;
- int uart1_txd;
- int i2c0_sda;
- int i2c0_scl;
- int mcasp0_aclkx;
- int mcasp0_fsx;
- int mcasp0_axr0;
- int mcasp0_ahclkr;
- int mcasp0_aclkr;
- int mcasp0_fsr;
- int mcasp0_axr1;
- int mcasp0_ahclkx;
- int xdma_event_intr0;
- int xdma_event_intr1;
- int nresetin_out;
- int porz;
- int nnmi;
- int osc0_in;
- int osc0_out;
- int rsvd1;
- int tms;
- int tdi;
- int tdo;
- int tck;
- int ntrst;
- int emu0;
- int emu1;
- int osc1_in;
- int osc1_out;
- int pmic_power_en;
- int rtc_porz;
- int rsvd2;
- int ext_wakeup;
- int enz_kaldo_1p8v;
- int usb0_dm;
- int usb0_dp;
- int usb0_ce;
- int usb0_id;
- int usb0_vbus;
- int usb0_drvvbus;
- int usb1_dm;
- int usb1_dp;
- int usb1_ce;
- int usb1_id;
- int usb1_vbus;
- int usb1_drvvbus;
- int ddr_resetn;
- int ddr_csn0;
- int ddr_cke;
- int ddr_ck;
- int ddr_nck;
- int ddr_casn;
- int ddr_rasn;
- int ddr_wen;
- int ddr_ba0;
- int ddr_ba1;
- int ddr_ba2;
- int ddr_a0;
- int ddr_a1;
- int ddr_a2;
- int ddr_a3;
- int ddr_a4;
- int ddr_a5;
- int ddr_a6;
- int ddr_a7;
- int ddr_a8;
- int ddr_a9;
- int ddr_a10;
- int ddr_a11;
- int ddr_a12;
- int ddr_a13;
- int ddr_a14;
- int ddr_a15;
- int ddr_odt;
- int ddr_d0;
- int ddr_d1;
- int ddr_d2;
- int ddr_d3;
- int ddr_d4;
- int ddr_d5;
- int ddr_d6;
- int ddr_d7;
- int ddr_d8;
- int ddr_d9;
- int ddr_d10;
- int ddr_d11;
- int ddr_d12;
- int ddr_d13;
- int ddr_d14;
- int ddr_d15;
- int ddr_dqm0;
- int ddr_dqm1;
- int ddr_dqs0;
- int ddr_dqsn0;
- int ddr_dqs1;
- int ddr_dqsn1;
- int ddr_vref;
- int ddr_vtp;
- int ddr_strben0;
- int ddr_strben1;
- int ain7;
- int ain6;
- int ain5;
- int ain4;
- int ain3;
- int ain2;
- int ain1;
- int ain0;
- int vrefp;
- int vrefn;
-};
-
-struct module_pin_mux {
- short reg_offset;
- unsigned char val;
-};
-
-/* Pad control register offset */
-#define PAD_CTRL_BASE 0x800
-#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
- (PAD_CTRL_BASE))->x)
-
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
@@ -363,20 +130,6 @@ static struct module_pin_mux mii1_pin_mux[] = {
{-1},
};
-/*
- * Configure the pin mux for the module
- */
-static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
-{
- int i;
-
- if (!mod_pin_mux)
- return;
-
- for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
- MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
-}
-
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH 5/5] am33xx: support board specific ddr settings
2012-10-16 15:15 [U-Boot] [PATCH 0/5] am33xx: support non-ti boards Peter Korsgaard
` (3 preceding siblings ...)
2012-10-16 15:15 ` [U-Boot] [PATCH 4/5] am33xx: move generic parts of pinmux handling out from board/ti/am335x Peter Korsgaard
@ 2012-10-16 15:15 ` Peter Korsgaard
2012-10-16 15:31 ` Tom Rini
4 siblings, 1 reply; 15+ messages in thread
From: Peter Korsgaard @ 2012-10-16 15:15 UTC (permalink / raw)
To: u-boot
Move the hardcoded ddr2/ddr3 settings for the ti boards to board code,
so other boards can use different types/timings.
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
---
arch/arm/cpu/armv7/am33xx/emif4.c | 114 +++---------------------
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 39 +--------
board/ti/am335x/evm.c | 125 ++++++++++++++++++++++++---
3 files changed, 126 insertions(+), 152 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index b2d7c0d..01e3a52 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -47,78 +47,6 @@ void dram_init_banksize(void)
static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
-static const struct ddr_data ddr2_data = {
- .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
- |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
- .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
- |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
- .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
- |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
- .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
- |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
- .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
- |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
- .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
- |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
- .datauserank0delay = DDR2_PHY_RANK0_DELAY,
- .datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr2_cmd_ctrl_data = {
- .cmd0csratio = DDR2_RATIO,
- .cmd0dldiff = DDR2_DLL_LOCK_DIFF,
- .cmd0iclkout = DDR2_INVERT_CLKOUT,
-
- .cmd1csratio = DDR2_RATIO,
- .cmd1dldiff = DDR2_DLL_LOCK_DIFF,
- .cmd1iclkout = DDR2_INVERT_CLKOUT,
-
- .cmd2csratio = DDR2_RATIO,
- .cmd2dldiff = DDR2_DLL_LOCK_DIFF,
- .cmd2iclkout = DDR2_INVERT_CLKOUT,
-};
-
-static const struct emif_regs ddr2_emif_reg_data = {
- .sdram_config = DDR2_EMIF_SDCFG,
- .ref_ctrl = DDR2_EMIF_SDREF,
- .sdram_tim1 = DDR2_EMIF_TIM1,
- .sdram_tim2 = DDR2_EMIF_TIM2,
- .sdram_tim3 = DDR2_EMIF_TIM3,
- .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
-};
-
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = DDR3_RD_DQS,
- .datawdsratio0 = DDR3_WR_DQS,
- .datafwsratio0 = DDR3_PHY_FIFO_WE,
- .datawrsratio0 = DDR3_PHY_WR_DATA,
- .datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = DDR3_RATIO,
- .cmd0dldiff = DDR3_DLL_LOCK_DIFF,
- .cmd0iclkout = DDR3_INVERT_CLKOUT,
-
- .cmd1csratio = DDR3_RATIO,
- .cmd1dldiff = DDR3_DLL_LOCK_DIFF,
- .cmd1iclkout = DDR3_INVERT_CLKOUT,
-
- .cmd2csratio = DDR3_RATIO,
- .cmd2dldiff = DDR3_DLL_LOCK_DIFF,
- .cmd2iclkout = DDR3_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = DDR3_EMIF_SDCFG,
- .ref_ctrl = DDR3_EMIF_SDREF,
- .sdram_tim1 = DDR3_EMIF_TIM1,
- .sdram_tim2 = DDR3_EMIF_TIM2,
- .sdram_tim3 = DDR3_EMIF_TIM3,
- .zq_config = DDR3_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
-};
-
static void config_vtp(void)
{
writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@@ -134,46 +62,26 @@ static void config_vtp(void)
;
}
-void config_ddr(short ddr_type)
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+ const struct ddr_data *data, const struct cmd_control *ctrl,
+ const struct emif_regs *regs)
{
- int ddr_pll, ioctrl_val;
- const struct emif_regs *emif_regs;
- const struct ddr_data *ddr_data;
- const struct cmd_control *cmd_ctrl_data;
-
- if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
- ddr_pll = 266;
- cmd_ctrl_data = &ddr2_cmd_ctrl_data;
- ddr_data = &ddr2_data;
- ioctrl_val = DDR2_IOCTRL_VALUE;
- emif_regs = &ddr2_emif_reg_data;
- } else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
- ddr_pll = 303;
- cmd_ctrl_data = &ddr3_cmd_ctrl_data;
- ddr_data = &ddr3_data;
- ioctrl_val = DDR3_IOCTRL_VALUE;
- emif_regs = &ddr3_emif_reg_data;
- } else {
- puts("Unknown memory type");
- hang();
- }
-
enable_emif_clocks();
- ddr_pll_config(ddr_pll);
+ ddr_pll_config(pll);
config_vtp();
- config_cmd_ctrl(cmd_ctrl_data);
+ config_cmd_ctrl(ctrl);
- config_ddr_data(0, ddr_data);
- config_ddr_data(1, ddr_data);
+ config_ddr_data(0, data);
+ config_ddr_data(1, data);
- config_io_ctrl(ioctrl_val);
+ config_io_ctrl(ioctrl);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
/* Program EMIF instance */
- config_ddr_phy(emif_regs);
- set_sdram_timings(emif_regs);
- config_sdram(emif_regs);
+ config_ddr_phy(regs);
+ set_sdram_timings(regs);
+ config_sdram(regs);
}
#endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 6b22c45..ea9682e 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -29,41 +29,6 @@
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL 0x1
-#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
-#define DDR2_EMIF_TIM1 0x0666B3C9
-#define DDR2_EMIF_TIM2 0x243631CA
-#define DDR2_EMIF_TIM3 0x0000033F
-#define DDR2_EMIF_SDCFG 0x41805332
-#define DDR2_EMIF_SDREF 0x0000081a
-#define DDR2_DLL_LOCK_DIFF 0x0
-#define DDR2_RATIO 0x80
-#define DDR2_INVERT_CLKOUT 0x00
-#define DDR2_RD_DQS 0x12
-#define DDR2_WR_DQS 0x00
-#define DDR2_PHY_WRLVL 0x00
-#define DDR2_PHY_GATELVL 0x00
-#define DDR2_PHY_WR_DATA 0x40
-#define DDR2_PHY_FIFO_WE 0x80
-#define DDR2_PHY_RANK0_DELAY 0x1
-#define DDR2_IOCTRL_VALUE 0x18B
-
-/* Micron MT41J128M16JT-125 */
-#define DDR3_EMIF_READ_LATENCY 0x06
-#define DDR3_EMIF_TIM1 0x0888A39B
-#define DDR3_EMIF_TIM2 0x26337FDA
-#define DDR3_EMIF_TIM3 0x501F830F
-#define DDR3_EMIF_SDCFG 0x61C04AB2
-#define DDR3_EMIF_SDREF 0x0000093B
-#define DDR3_ZQ_CFG 0x50074BE4
-#define DDR3_DLL_LOCK_DIFF 0x1
-#define DDR3_RATIO 0x40
-#define DDR3_INVERT_CLKOUT 0x1
-#define DDR3_RD_DQS 0x3B
-#define DDR3_WR_DQS 0x85
-#define DDR3_PHY_WR_DATA 0xC1
-#define DDR3_PHY_FIFO_WE 0x100
-#define DDR3_IOCTRL_VALUE 0x18B
-
/**
* Configure SDRAM
*/
@@ -189,6 +154,8 @@ struct ddr_ctrl {
unsigned int ddrckectrl;
};
-void config_ddr(short ddr_type);
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+ const struct ddr_data *data, const struct cmd_control *ctrl,
+ const struct emif_regs *regs);
#endif /* _DDR_DEFS_H */
diff --git a/board/ti/am335x/evm.c b/board/ti/am335x/evm.c
index 9dd372c..dcb3777 100644
--- a/board/ti/am335x/evm.c
+++ b/board/ti/am335x/evm.c
@@ -110,19 +110,115 @@ static int read_eeprom(void)
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
-#endif
-/*
- * Determine what type of DDR we have.
- */
-static short inline board_memory_type(void)
-{
- /* The following boards are known to use DDR3. */
- if (board_is_evm_sk())
- return EMIF_REG_SDRAM_TYPE_DDR3;
+/* Micron MT47H128M16RT-25E */
+#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
+#define DDR2_EMIF_TIM1 0x0666B3C9
+#define DDR2_EMIF_TIM2 0x243631CA
+#define DDR2_EMIF_TIM3 0x0000033F
+#define DDR2_EMIF_SDCFG 0x41805332
+#define DDR2_EMIF_SDREF 0x0000081a
+#define DDR2_DLL_LOCK_DIFF 0x0
+#define DDR2_RATIO 0x80
+#define DDR2_INVERT_CLKOUT 0x00
+#define DDR2_RD_DQS 0x12
+#define DDR2_WR_DQS 0x00
+#define DDR2_PHY_WRLVL 0x00
+#define DDR2_PHY_GATELVL 0x00
+#define DDR2_PHY_WR_DATA 0x40
+#define DDR2_PHY_FIFO_WE 0x80
+#define DDR2_PHY_RANK0_DELAY 0x1
+#define DDR2_IOCTRL_VALUE 0x18B
+
+/* Micron MT41J128M16JT-125 */
+#define DDR3_EMIF_READ_LATENCY 0x06
+#define DDR3_EMIF_TIM1 0x0888A39B
+#define DDR3_EMIF_TIM2 0x26337FDA
+#define DDR3_EMIF_TIM3 0x501F830F
+#define DDR3_EMIF_SDCFG 0x61C04AB2
+#define DDR3_EMIF_SDREF 0x0000093B
+#define DDR3_ZQ_CFG 0x50074BE4
+#define DDR3_DLL_LOCK_DIFF 0x1
+#define DDR3_RATIO 0x40
+#define DDR3_INVERT_CLKOUT 0x1
+#define DDR3_RD_DQS 0x3B
+#define DDR3_WR_DQS 0x85
+#define DDR3_PHY_WR_DATA 0xC1
+#define DDR3_PHY_FIFO_WE 0x100
+#define DDR3_IOCTRL_VALUE 0x18B
+
+static const struct ddr_data ddr2_data = {
+ .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
+ |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
+ .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
+ |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
+ .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
+ |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
+ .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
+ |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
+ .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
+ |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
+ .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
+ |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+ .datauserank0delay = DDR2_PHY_RANK0_DELAY,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
- return EMIF_REG_SDRAM_TYPE_DDR2;
-}
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+ .cmd0csratio = DDR2_RATIO,
+ .cmd0dldiff = DDR2_DLL_LOCK_DIFF,
+ .cmd0iclkout = DDR2_INVERT_CLKOUT,
+
+ .cmd1csratio = DDR2_RATIO,
+ .cmd1dldiff = DDR2_DLL_LOCK_DIFF,
+ .cmd1iclkout = DDR2_INVERT_CLKOUT,
+
+ .cmd2csratio = DDR2_RATIO,
+ .cmd2dldiff = DDR2_DLL_LOCK_DIFF,
+ .cmd2iclkout = DDR2_INVERT_CLKOUT,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+ .sdram_config = DDR2_EMIF_SDCFG,
+ .ref_ctrl = DDR2_EMIF_SDREF,
+ .sdram_tim1 = DDR2_EMIF_TIM1,
+ .sdram_tim2 = DDR2_EMIF_TIM2,
+ .sdram_tim3 = DDR2_EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
+};
+
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = DDR3_RD_DQS,
+ .datawdsratio0 = DDR3_WR_DQS,
+ .datafwsratio0 = DDR3_PHY_FIFO_WE,
+ .datawrsratio0 = DDR3_PHY_WR_DATA,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = DDR3_RATIO,
+ .cmd0dldiff = DDR3_DLL_LOCK_DIFF,
+ .cmd0iclkout = DDR3_INVERT_CLKOUT,
+
+ .cmd1csratio = DDR3_RATIO,
+ .cmd1dldiff = DDR3_DLL_LOCK_DIFF,
+ .cmd1iclkout = DDR3_INVERT_CLKOUT,
+
+ .cmd2csratio = DDR3_RATIO,
+ .cmd2dldiff = DDR3_DLL_LOCK_DIFF,
+ .cmd2iclkout = DDR3_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = DDR3_EMIF_SDCFG,
+ .ref_ctrl = DDR3_EMIF_SDREF,
+ .sdram_tim1 = DDR3_EMIF_TIM1,
+ .sdram_tim2 = DDR3_EMIF_TIM2,
+ .sdram_tim3 = DDR3_EMIF_TIM3,
+ .zq_config = DDR3_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
+};
+#endif
/*
* early system init of muxing and clocks.
@@ -178,9 +274,12 @@ void s_init(void)
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
- }
- config_ddr(board_memory_type());
+ config_ddr(303, DDR3_IOCTRL_VALUE, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+ } else
+ config_ddr(266, DDR2_IOCTRL_VALUE, &ddr2_data,
+ &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
#endif
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH 5/5] am33xx: support board specific ddr settings
2012-10-16 15:15 ` [U-Boot] [PATCH 5/5] am33xx: support board specific ddr settings Peter Korsgaard
@ 2012-10-16 15:31 ` Tom Rini
2012-10-16 17:43 ` Peter Korsgaard
0 siblings, 1 reply; 15+ messages in thread
From: Tom Rini @ 2012-10-16 15:31 UTC (permalink / raw)
To: u-boot
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On 10/16/12 08:15, Peter Korsgaard wrote:
> Move the hardcoded ddr2/ddr3 settings for the ti boards to board
> code, so other boards can use different types/timings.
>
> Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> ---
> arch/arm/cpu/armv7/am33xx/emif4.c | 114
> +++---------------------
> arch/arm/include/asm/arch-am33xx/ddr_defs.h | 39 +--------
> board/ti/am335x/evm.c | 125
> ++++++++++++++++++++++++--- 3 files changed, 126 insertions(+),
> 152 deletions(-)
I would like to see the ddr information kept in
arch/arm/cpu/armv7/am33xx but prefixed with vendor/part information so
we can re-use it on other boards.
- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://www.enigmail.net/
iQIcBAEBAgAGBQJQfX3uAAoJENk4IS6UOR1WookP/Rwjqm8Xrg2u6E7WnVG74tKc
KhVZO7PptoA4ZLpENvNPQ097IUAD0ECQaL6BaoByIRE4CCvGAfAFB5vINhQ0Ysr5
SpbmMG42KRMCre1kSlFMzDTkmdUmyq7Ko/KkYGXIe5hk4LLNL/CE1Cd6Z0U8E3jF
lSNgMpcS5YVNsshdCTGEJr9V6LhXyxRFELX5OuQnSpI/xTuT3bsa1szOot30lDib
6nlyjo0Qu7Pd0n7FUXM8xusjMnmDohUrM0q3N//N3hKg+HIMLt8A2RL641bC2Yft
7yLgkRqf6tuvkL3Th/wImRSWoBFqG+YGPBX0AIrU9+HCAyGrEaSMKDNB5YLVlUl+
rAp2y5haETPWRiR5Q9Oyzqyr/HS7IqE8HPbvaF342uUzwha7e4ikFWUcqD3tDxc5
1iQegEAp8UchbA6SIt1Ob5zaRL8pfKDTfoU2LyJzaRz4zCQQUAiG4BCeuBMYUhRs
nPoMmOZB/A6NqOPOnBinoQZ8mAZ+wu/xArAu0ihZMphkgjWToKmn75p8PkvvgObX
DWW8CcPFyZSerlbxFqm5s7rVaQ5s5DWXxAQhdsJ+BvDpNRmZ8EpR64GdGgtI8hlk
YXKihHzy/XD6V607ihtpxSSkUMVQ9SbUDOSckjfXxrwv8sSEVmawXPgrcWx+m0h5
GRplVn9IlFZSPMBnBiFl
=YrlN
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 5/5] am33xx: support board specific ddr settings
2012-10-16 15:31 ` Tom Rini
@ 2012-10-16 17:43 ` Peter Korsgaard
2012-10-16 21:13 ` Tom Rini
0 siblings, 1 reply; 15+ messages in thread
From: Peter Korsgaard @ 2012-10-16 17:43 UTC (permalink / raw)
To: u-boot
>>>>> "Tom" == Tom Rini <trini@ti.com> writes:
Hi,
Tom> I would like to see the ddr information kept in
Tom> arch/arm/cpu/armv7/am33xx but prefixed with vendor/part information so
Tom> we can re-use it on other boards.
So something like:
/* Micron MT41J128M16JT-125 */
#define MICRON_MT41J128M16JT125_EMIF_READ_LATENCY 0x06
#define MICRON_MT41J128M16JT125_EMIF_TIM1 0x0888A39B
..
That's seems pretty long, but OK - I can do that.
The board I'm using has a MT41J64, so those numbers are basically the
same as the 128 except for the number of rows.
--
Bye, Peter Korsgaard
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 5/5] am33xx: support board specific ddr settings
2012-10-16 17:43 ` Peter Korsgaard
@ 2012-10-16 21:13 ` Tom Rini
0 siblings, 0 replies; 15+ messages in thread
From: Tom Rini @ 2012-10-16 21:13 UTC (permalink / raw)
To: u-boot
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On 10/16/12 10:43, Peter Korsgaard wrote:
>>>>>> "Tom" == Tom Rini <trini@ti.com> writes:
>
> Hi,
>
> Tom> I would like to see the ddr information kept in Tom>
> arch/arm/cpu/armv7/am33xx but prefixed with vendor/part information
> so Tom> we can re-use it on other boards.
>
> So something like:
>
> /* Micron MT41J128M16JT-125 */ #define
> MICRON_MT41J128M16JT125_EMIF_READ_LATENCY 0x06 #define
> MICRON_MT41J128M16JT125_EMIF_TIM1 0x0888A39B ..
>
> That's seems pretty long, but OK - I can do that.
>
> The board I'm using has a MT41J64, so those numbers are basically
> the same as the 128 except for the number of rows.
MICRON_MT41J{128,64}M_... then?
- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://www.enigmail.net/
iQIcBAEBAgAGBQJQfc3fAAoJENk4IS6UOR1WGtwP/2wCuMDhncZM/oSzbcW0Cjsd
eGx1lBit+X7lmaqhIgixFL3Q083DJ6acJ5WAoR5E8m0CFzHBVyoPnHpr9Gz1RQHP
gu9T6VxdPFa4EABE9YyLSaCYmDgETaRUfLiQq3fBztLYwMG3QxkXDgLf05rl9giQ
9s1cXT5S+3DnT8cRg5FHO7fRuq7BJHgHNTW1CrR6wDKNKlx6QrlyyS8aSieaUkdI
3+HWE2vkKETaBXPNUSpJ/iutlgh3PTXmgydAjWSK+biFNb+9kNjzbYwdZBnAgWo0
8tpuaNIqY27zjk3W8erTjF3MB6sCmFUetQoLQcVgXdQYRa242DT3gQhJ0Frlkibt
8vsMVHWewwmJ0OKwcVdcLTB/pG/8u4GKD4EaV4lsxN02SruVrHALraT0mVw3sMV2
lUQd15HE9SAXCX7u/rTa1iCyT1Ll1O8ELrux559wx1R31ob2gLQvwNN9QWeA3Pwf
Gp/9QykTXNB9nSGN5Ri9pJp9YJXxv7aOreD7wMZwQHJ1nefplX+EirkCysaiw3bi
Q8LOoKPLyvKe0eltn4IpYzNTtzRybl79lap8rw7k8IowFlKuE2xzO4SJBIY9SEFB
QNo+lyxrw3Yl95EU41IOB8fq2QElmxJveCQTT07MotkjS1X3nv8ScQfS+dC/SWBL
EkZB1u7ORVcNX3BfGB3q
=NDut
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^ permalink raw reply [flat|nested] 15+ messages in thread