* [U-Boot] [PATCH 1/3] mx5: lowlevel_init.S: Split init_clock macro
@ 2012-10-15 15:37 Fabio Estevam
2012-10-15 15:37 ` [U-Boot] [PATCH 2/3] mx5: lowlevel_init.S: Fix PLL settings for mx53 Fabio Estevam
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Fabio Estevam @ 2012-10-15 15:37 UTC (permalink / raw)
To: u-boot
init_clock is currently shared between mx51 and mx53 and it contains lots of
ifdef's which makes it really hard to follow the code.
Split the init_clock between mx51 and mx53 to allow easier readability.
No functional changes are made.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/cpu/armv7/mx5/lowlevel_init.S | 95 ++++++++++++++++++++++----------
1 file changed, 65 insertions(+), 30 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 529e35b..d0bab45 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -162,9 +162,9 @@ setup_pll_func:
.endm
.macro init_clock
+#if defined (CONFIG_MX51)
ldr r0, =CCM_BASE_ADDR
-#if defined(CONFIG_MX51)
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
@@ -190,21 +190,6 @@ setup_pll_func:
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
-#else
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r4, [r0, #CLKCTL_CCGR1]
- str r4, [r0, #CLKCTL_CCGR2]
- str r4, [r0, #CLKCTL_CCGR3]
- str r4, [r0, #CLKCTL_CCGR7]
-
- ldr r1, =0x00030000
- str r1, [r0, #CLKCTL_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #CLKCTL_CCGR5]
- ldr r1, =0x0F00030F
- str r1, [r0, #CLKCTL_CCGR6]
-#endif
/* Switch ARM to step clock */
mov r1, #0x4
@@ -217,7 +202,6 @@ setup_pll_func:
setup_pll PLL1_BASE_ADDR, 800
#endif
-#if defined(CONFIG_MX51)
setup_pll PLL3_BASE_ADDR, 665
/* Switch peripheral to PLL 3 */
@@ -234,7 +218,7 @@ setup_pll_func:
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
-#endif
+
setup_pll PLL3_BASE_ADDR, 216
/* Set the platform clock dividers */
@@ -244,21 +228,17 @@ setup_pll_func:
ldr r0, =CCM_BASE_ADDR
-#if defined(CONFIG_MX51)
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
-#else
- mov r1, #0
-#endif
+
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
str r4, [r0, #CLKCTL_CCSR]
-#if defined(CONFIG_MX51)
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
@@ -266,7 +246,6 @@ setup_pll_func:
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
-#endif
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
@@ -277,17 +256,72 @@ setup_pll_func:
str r1, [r0, #CLKCTL_CCGR4]
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
-#if defined(CONFIG_MX53)
- str r1, [r0, #CLKCTL_CCGR7]
-#endif
-#if defined(CONFIG_MX51)
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, =0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
-#elif defined(CONFIG_MX53)
+ /* make sure divider effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ str r4, [r0, #CLKCTL_CCDR]
+
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+#else /* CONFIG_MX53 */
+ ldr r0, =CCM_BASE_ADDR
+
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r4, [r0, #CLKCTL_CCGR1]
+ str r4, [r0, #CLKCTL_CCGR2]
+ str r4, [r0, #CLKCTL_CCGR3]
+ str r4, [r0, #CLKCTL_CCGR7]
+ ldr r1, =0x00030000
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =0x0F00030F
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+
+ setup_pll PLL1_BASE_ADDR, 800
+
+ setup_pll PLL3_BASE_ADDR, 216
+
+ /* Set the platform clock dividers */
+ ldr r0, =ARM_BASE_ADDR
+ ldr r1, =0x00000725
+ str r1, [r0, #0x14]
+
+ ldr r0, =CCM_BASE_ADDR
+
+ mov r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1 */
+ str r4, [r0, #CLKCTL_CCSR]
+
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+ str r1, [r0, #CLKCTL_CCGR7]
+
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00808145
@@ -306,7 +340,7 @@ setup_pll_func:
and r1, r1, #0xffffffc0
orr r1, r1, #0x0a
str r1, [r0, #CLKCTL_CSCDR1]
-#endif
+
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
@@ -318,6 +352,7 @@ setup_pll_func:
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
+#endif /* CONFIG_MX53 */
.endm
.macro setup_wdog
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/3] mx5: lowlevel_init.S: Fix PLL settings for mx53
2012-10-15 15:37 [U-Boot] [PATCH 1/3] mx5: lowlevel_init.S: Split init_clock macro Fabio Estevam
@ 2012-10-15 15:37 ` Fabio Estevam
2012-10-17 16:11 ` Stefano Babic
2012-10-15 15:37 ` [U-Boot] [PATCH 3/3] mx53loco: Adapt the IPU clock Fabio Estevam
2012-10-17 16:11 ` [U-Boot] [PATCH 1/3] mx5: lowlevel_init.S: Split init_clock macro Stefano Babic
2 siblings, 1 reply; 6+ messages in thread
From: Fabio Estevam @ 2012-10-15 15:37 UTC (permalink / raw)
To: u-boot
Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.
Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz
instead.
Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI
at 1080p because the IPU clock cannot reach the requested frequency.
Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its
maximum frequency.
Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little
bit to allow easier comparison with the original clock setup from FSL U-boot.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/cpu/armv7/mx5/lowlevel_init.S | 96 ++++++++++++++++++++----------
arch/arm/include/asm/arch-mx5/imx-regs.h | 4 ++
2 files changed, 67 insertions(+), 33 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index d0bab45..d62093b 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -296,20 +296,66 @@ setup_pll_func:
setup_pll PLL1_BASE_ADDR, 800
- setup_pll PLL3_BASE_ADDR, 216
+ setup_pll PLL3_BASE_ADDR, 400
+
+ /* Switch peripheral to PLL3 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00015154
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, =0x02888945
+ orr r1, r1, #(1 << 16)
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ setup_pll PLL2_BASE_ADDR, 400
+
+ /* Switch peripheral to PLL2 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00808145
+ orr r1, r1, #(2 << 10)
+ orr r1, r1, #(0 << 16)
+ orr r1, r1, #(1 << 19)
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ ldr r1, =0x00016154
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ /*change uart clk parent to pll2*/
+ ldr r1, [r0, #CLKCTL_CSCMR1]
+ and r1, r1, #0xfcffffff
+ orr r1, r1, #0x01000000
+ str r1, [r0, #CLKCTL_CSCMR1]
+
+ /* make sure change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ setup_pll PLL3_BASE_ADDR, 216
+
+ setup_pll PLL4_BASE_ADDR, 455
/* Set the platform clock dividers */
ldr r0, =ARM_BASE_ADDR
- ldr r1, =0x00000725
+ ldr r1, =0x00000124
str r1, [r0, #0x14]
ldr r0, =CCM_BASE_ADDR
-
mov r1, #0
str r1, [r0, #CLKCTL_CACRR]
- /* Switch ARM back to PLL 1 */
- str r4, [r0, #CLKCTL_CCSR]
+ /* Switch ARM back to PLL 1. */
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCSR]
+
+ /* make uart div=6 */
+ ldr r1, [r0, #CLKCTL_CSCDR1]
+ and r1, r1, #0xffffffc0
+ orr r1, r1, #0x0a
+ str r1, [r0, #CLKCTL_CSCDR1]
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
@@ -322,36 +368,14 @@ setup_pll_func:
str r1, [r0, #CLKCTL_CCGR6]
str r1, [r0, #CLKCTL_CCGR7]
- /* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x00808145
- orr r1, r1, #2 << 10
- orr r1, r1, #1 << 19
- str r1, [r0, #CLKCTL_CBCDR]
+ mov r1, #0x00000
+ str r1, [r0, #CLKCTL_CCDR]
- ldr r1, =0x00016154
- str r1, [r0, #CLKCTL_CBCMR]
- /* Change uart clk parent to pll2*/
- ldr r1, [r0, #CLKCTL_CSCMR1]
- and r1, r1, #0xfcffffff
- orr r1, r1, #0x01000000
- str r1, [r0, #CLKCTL_CSCMR1]
- ldr r1, [r0, #CLKCTL_CSCDR1]
- and r1, r1, #0xffffffc0
- orr r1, r1, #0x0a
- str r1, [r0, #CLKCTL_CSCDR1]
-
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
- str r4, [r0, #CLKCTL_CCDR]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
#endif /* CONFIG_MX53 */
.endm
@@ -405,3 +429,9 @@ W_DP_665: .word DP_OP_665
W_DP_216: .word DP_OP_216
.word DP_MFD_216
.word DP_MFN_216
+W_DP_400: .word DP_OP_400
+ .word DP_MFD_400
+ .word DP_MFN_400
+W_DP_455: .word DP_OP_455
+ .word DP_MFD_455
+ .word DP_MFN_455
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 46017f4..1d060fd 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -308,6 +308,10 @@
#define DP_MFD_400 (3 - 1)
#define DP_MFN_400 1
+#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
+#define DP_MFD_455 (48 - 1)
+#define DP_MFN_455 23
+
#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
#define DP_MFD_216 (4 - 1)
#define DP_MFN_216 3
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 3/3] mx53loco: Adapt the IPU clock
2012-10-15 15:37 [U-Boot] [PATCH 1/3] mx5: lowlevel_init.S: Split init_clock macro Fabio Estevam
2012-10-15 15:37 ` [U-Boot] [PATCH 2/3] mx5: lowlevel_init.S: Fix PLL settings for mx53 Fabio Estevam
@ 2012-10-15 15:37 ` Fabio Estevam
2012-10-17 16:11 ` Stefano Babic
2012-10-17 16:11 ` [U-Boot] [PATCH 1/3] mx5: lowlevel_init.S: Split init_clock macro Stefano Babic
2 siblings, 1 reply; 6+ messages in thread
From: Fabio Estevam @ 2012-10-15 15:37 UTC (permalink / raw)
To: u-boot
Since PLL2 now has changed, it is necessary to adapt the CONFIG_IPUV3_CLK
accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
include/configs/mx53loco.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 6a6aaa1..2ecfbd6 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -222,6 +222,6 @@
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK 133000000
+#define CONFIG_IPUV3_CLK 200000000
#endif /* __CONFIG_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/3] mx5: lowlevel_init.S: Fix PLL settings for mx53
2012-10-15 15:37 ` [U-Boot] [PATCH 2/3] mx5: lowlevel_init.S: Fix PLL settings for mx53 Fabio Estevam
@ 2012-10-17 16:11 ` Stefano Babic
0 siblings, 0 replies; 6+ messages in thread
From: Stefano Babic @ 2012-10-17 16:11 UTC (permalink / raw)
To: u-boot
Am 15/10/2012 17:37, schrieb Fabio Estevam:
> Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.
>
> Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz
> instead.
>
> Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI
> at 1080p because the IPU clock cannot reach the requested frequency.
>
> Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its
> maximum frequency.
>
> Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little
> bit to allow easier comparison with the original clock setup from FSL U-boot.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 3/3] mx53loco: Adapt the IPU clock
2012-10-15 15:37 ` [U-Boot] [PATCH 3/3] mx53loco: Adapt the IPU clock Fabio Estevam
@ 2012-10-17 16:11 ` Stefano Babic
0 siblings, 0 replies; 6+ messages in thread
From: Stefano Babic @ 2012-10-17 16:11 UTC (permalink / raw)
To: u-boot
Am 15/10/2012 17:37, schrieb Fabio Estevam:
> Since PLL2 now has changed, it is necessary to adapt the CONFIG_IPUV3_CLK
> accordingly.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/3] mx5: lowlevel_init.S: Split init_clock macro
2012-10-15 15:37 [U-Boot] [PATCH 1/3] mx5: lowlevel_init.S: Split init_clock macro Fabio Estevam
2012-10-15 15:37 ` [U-Boot] [PATCH 2/3] mx5: lowlevel_init.S: Fix PLL settings for mx53 Fabio Estevam
2012-10-15 15:37 ` [U-Boot] [PATCH 3/3] mx53loco: Adapt the IPU clock Fabio Estevam
@ 2012-10-17 16:11 ` Stefano Babic
2 siblings, 0 replies; 6+ messages in thread
From: Stefano Babic @ 2012-10-17 16:11 UTC (permalink / raw)
To: u-boot
Am 15/10/2012 17:37, schrieb Fabio Estevam:
> init_clock is currently shared between mx51 and mx53 and it contains lots of
> ifdef's which makes it really hard to follow the code.
>
> Split the init_clock between mx51 and mx53 to allow easier readability.
>
> No functional changes are made.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-10-17 16:11 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2012-10-15 15:37 [U-Boot] [PATCH 1/3] mx5: lowlevel_init.S: Split init_clock macro Fabio Estevam
2012-10-15 15:37 ` [U-Boot] [PATCH 2/3] mx5: lowlevel_init.S: Fix PLL settings for mx53 Fabio Estevam
2012-10-17 16:11 ` Stefano Babic
2012-10-15 15:37 ` [U-Boot] [PATCH 3/3] mx53loco: Adapt the IPU clock Fabio Estevam
2012-10-17 16:11 ` Stefano Babic
2012-10-17 16:11 ` [U-Boot] [PATCH 1/3] mx5: lowlevel_init.S: Split init_clock macro Stefano Babic
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