From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Wed, 17 Oct 2012 18:11:09 +0200 Subject: [U-Boot] [PATCH 2/3] mx5: lowlevel_init.S: Fix PLL settings for mx53 In-Reply-To: <1350315437-29848-2-git-send-email-fabio.estevam@freescale.com> References: <1350315437-29848-1-git-send-email-fabio.estevam@freescale.com> <1350315437-29848-2-git-send-email-fabio.estevam@freescale.com> Message-ID: <507ED89D.5000303@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Am 15/10/2012 17:37, schrieb Fabio Estevam: > Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. > > Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz > instead. > > Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI > at 1080p because the IPU clock cannot reach the requested frequency. > > Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its > maximum frequency. > > Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little > bit to allow easier comparison with the original clock setup from FSL U-boot. > > Signed-off-by: Fabio Estevam > --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================