* [U-Boot] [PATCH v2 02/13] ehci-mxc: Clean up
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
@ 2012-11-08 20:28 ` Benoît Thébaudeau
2012-11-08 20:28 ` [U-Boot] [PATCH v2 03/13] ehci-mx5: " Benoît Thébaudeau
` (12 subsequent siblings)
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:28 UTC (permalink / raw)
To: u-boot
Clean up ehci-mxc:
- Remove useless #if's.
- Fix identation.
- Issue a #error if used with an unsupported platform.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
.../drivers/usb/host/ehci-mxc.c | 86 +++++++++-----------
1 file changed, 40 insertions(+), 46 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
index a38bc9c..e21f2c5 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
@@ -28,14 +28,11 @@
#define USBCTRL_OTGBASE_OFFSET 0x600
-#ifdef CONFIG_MX25
#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
#define MX25_USB_CTRL_HSTD_BIT (1<<5)
#define MX25_USB_CTRL_USBTE_BIT (1<<4)
#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
-#endif
-#ifdef CONFIG_MX31
#define MX31_OTG_SIC_SHIFT 29
#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
#define MX31_OTG_PM_BIT (1 << 24)
@@ -49,59 +46,56 @@
#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
#define MX31_H1_PM_BIT (1 << 8)
#define MX31_H1_DT_BIT (1 << 4)
-#endif
static int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25)
v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#endif
+#elif defined(CONFIG_MX31)
+ v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-#ifdef CONFIG_MX31
- v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-
- switch (port) {
- case 0: /* OTG port */
- v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK)
- << MX31_OTG_SIC_SHIFT;
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_OTG_PM_BIT;
-
- break;
- case 1: /* H1 port */
- v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
- MX31_H1_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK)
- << MX31_H1_SIC_SHIFT;
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_H1_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX31_H1_DT_BIT;
-
- break;
- case 2: /* H2 port */
- v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
- MX31_H2_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK)
- << MX31_H2_SIC_SHIFT;
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_H2_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX31_H2_DT_BIT;
-
- break;
- default:
- return -EINVAL;
- }
-#endif
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_OTG_PM_BIT;
+
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_H1_PM_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX31_H1_DT_BIT;
+
+ break;
+ case 2: /* H2 port */
+ v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_H2_PM_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX31_H2_DT_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
+#else
+#error MXC EHCI USB driver not supported on this platform
+#endif
writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+
return 0;
}
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 03/13] ehci-mx5: Clean up
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
2012-11-08 20:28 ` [U-Boot] [PATCH v2 02/13] ehci-mxc: Clean up Benoît Thébaudeau
@ 2012-11-08 20:28 ` Benoît Thébaudeau
2012-11-08 20:28 ` [U-Boot] [PATCH v2 04/13] ehci-mx5: Fix OC_DIS usage Benoît Thébaudeau
` (11 subsequent siblings)
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:28 UTC (permalink / raw)
To: u-boot
Clean up ehci-mx5:
- Fix column alignments.
- Fix comments.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
.../drivers/usb/host/ehci-mx5.c | 34 ++++++++++----------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 9a2c295..66ab25d 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -29,9 +29,9 @@
#define MX5_USBOTHER_REGS_OFFSET 0x800
-#define MXC_OTG_OFFSET 0
-#define MXC_H1_OFFSET 0x200
-#define MXC_H2_OFFSET 0x400
+#define MXC_OTG_OFFSET 0
+#define MXC_H1_OFFSET 0x200
+#define MXC_H2_OFFSET 0x400
#define MXC_USBCTRL_OFFSET 0
#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
@@ -40,23 +40,23 @@
#define MXC_USBH2CTRL_OFFSET 0x14
/* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
+#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
+#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
/* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
/* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
/* USB_CTRL_1 */
-#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
+#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
/* USB pin configuration */
#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
@@ -160,7 +160,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
- case 1: /* Host 1 Host ULPI */
+ case 1: /* Host 1 ULPI */
#ifdef CONFIG_MX51
/* The clock for the USBH1 ULPI port will come externally
from the PHY. */
@@ -171,7 +171,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+ v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
else
v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
@@ -187,7 +187,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
case 2: /* Host 2 ULPI */
v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+ v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
else
v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 04/13] ehci-mx5: Fix OC_DIS usage
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
2012-11-08 20:28 ` [U-Boot] [PATCH v2 02/13] ehci-mxc: Clean up Benoît Thébaudeau
2012-11-08 20:28 ` [U-Boot] [PATCH v2 03/13] ehci-mx5: " Benoît Thébaudeau
@ 2012-11-08 20:28 ` Benoît Thébaudeau
2012-11-08 20:29 ` [U-Boot] [PATCH v2 05/13] ehci-mx5: Fix OPM usage Benoît Thébaudeau
` (10 subsequent siblings)
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:28 UTC (permalink / raw)
To: u-boot
MXC_OTG_PHYCTRL_OC_DIS_BIT disables the oc pin if set, like MXC_H1_OC_DIS_BIT,
not the opposite.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
.../drivers/usb/host/ehci-mx5.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 66ab25d..1248671 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -144,11 +144,11 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v = __raw_readl(usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- /* OC/USBPWR is not used */
- v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
- else
/* OC/USBPWR is used */
v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+ else
+ /* OC/USBPWR is not used */
+ v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
__raw_writel(v, usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 05/13] ehci-mx5: Fix OPM usage
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
` (2 preceding siblings ...)
2012-11-08 20:28 ` [U-Boot] [PATCH v2 04/13] ehci-mx5: Fix OC_DIS usage Benoît Thébaudeau
@ 2012-11-08 20:29 ` Benoît Thébaudeau
2012-11-08 20:29 ` [U-Boot] [PATCH v2 06/13] ehci-mx5: Fix *PM usage for i.MX53 Benoît Thébaudeau
` (9 subsequent siblings)
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:29 UTC (permalink / raw)
To: u-boot
MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like
MXC_H1_UCTRL_H1PM_BIT and MXC_H2_UCTRL_H2PM_BIT, not the opposite.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
.../drivers/usb/host/ehci-mx5.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 1248671..bd1f119 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -154,9 +154,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- v |= MXC_OTG_UCTRL_OPM_BIT;
- else
v &= ~MXC_OTG_UCTRL_OPM_BIT;
+ else
+ v |= MXC_OTG_UCTRL_OPM_BIT;
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 06/13] ehci-mx5: Fix *PM usage for i.MX53
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
` (3 preceding siblings ...)
2012-11-08 20:29 ` [U-Boot] [PATCH v2 05/13] ehci-mx5: Fix OPM usage Benoît Thébaudeau
@ 2012-11-08 20:29 ` Benoît Thébaudeau
2012-11-08 20:29 ` [U-Boot] [PATCH v2 07/13] ehci-mx5: Add missing OC_DIS " Benoît Thébaudeau
` (8 subsequent siblings)
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:29 UTC (permalink / raw)
To: u-boot
The MXC_*_UCTRL_*PM_BIT bits are available only on i.MX51.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
.../drivers/usb/host/ehci-mx5.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index bd1f119..8e42e56 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -153,10 +153,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
MXC_USB_PHY_CTR_FUNC_OFFSET);
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_OTG_UCTRL_OPM_BIT;
else
v |= MXC_OTG_UCTRL_OPM_BIT;
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
@@ -170,10 +172,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
#endif
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
else
v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
@@ -186,10 +190,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
break;
case 2: /* Host 2 ULPI */
v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+#ifdef CONFIG_MX51
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
else
v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+#endif
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
break;
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 07/13] ehci-mx5: Add missing OC_DIS for i.MX53
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
` (4 preceding siblings ...)
2012-11-08 20:29 ` [U-Boot] [PATCH v2 06/13] ehci-mx5: Fix *PM usage for i.MX53 Benoît Thébaudeau
@ 2012-11-08 20:29 ` Benoît Thébaudeau
2012-11-08 20:29 ` [U-Boot] [PATCH v2 08/13] ehci-mxc: Make EHCI power/oc polarities configurable Benoît Thébaudeau
` (7 subsequent siblings)
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:29 UTC (permalink / raw)
To: u-boot
The i.MX53 has MXC_H*_UCTRL_H*_OC_DIS_BIT bits to disable the oc pin.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
.../drivers/usb/host/ehci-mx5.c | 25 ++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 8e42e56..7da1398 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -32,12 +32,14 @@
#define MXC_OTG_OFFSET 0
#define MXC_H1_OFFSET 0x200
#define MXC_H2_OFFSET 0x400
+#define MXC_H3_OFFSET 0x600
#define MXC_USBCTRL_OFFSET 0
#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
#define MXC_USB_CTRL_1_OFFSET 0x10
#define MXC_USBH2CTRL_OFFSET 0x14
+#define MXC_USBH3CTRL_OFFSET 0x18
/* USB_CTRL */
#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
@@ -51,10 +53,16 @@
#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+/* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
+#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
+#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
+
/* USB_CTRL_1 */
#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
@@ -196,9 +204,26 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
else
v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
#endif
+#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
+ else
+ v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+#endif
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
break;
+#ifdef CONFIG_MX53
+ case 3: /* Host 3 ULPI */
+ v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
+ else
+ v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+
+ __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
+ break;
+#endif
}
return ret;
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 08/13] ehci-mxc: Make EHCI power/oc polarities configurable
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
` (5 preceding siblings ...)
2012-11-08 20:29 ` [U-Boot] [PATCH v2 07/13] ehci-mx5: Add missing OC_DIS " Benoît Thébaudeau
@ 2012-11-08 20:29 ` Benoît Thébaudeau
2012-11-08 20:30 ` [U-Boot] [PATCH v2 09/13] ehci-mxc: Make i.MX25 EHCI configurable Benoît Thébaudeau
` (6 subsequent siblings)
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:29 UTC (permalink / raw)
To: u-boot
Make EHCI power and overcurrent polarities configurable. If not set, these new
configurartions keep the default register values so that existing board files
do not have to be changed.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
.../drivers/usb/host/ehci-mx5.c | 51 ++++++++++++++++++++
.../include/usb/ehci-fsl.h | 10 ++--
2 files changed, 57 insertions(+), 4 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 7da1398..52aeae5 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -44,24 +44,33 @@
/* USB_CTRL */
#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* OTG power pin polarity */
#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* HOST1 power pin polarity */
/* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */
#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */
#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */
/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
/* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
+#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
/* USB_CTRL_1 */
#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
@@ -151,12 +160,22 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
if (flags & MXC_EHCI_INTERNAL_PHY) {
v = __raw_readl(usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
+ else
+ v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
/* OC/USBPWR is used */
v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
else
/* OC/USBPWR is not used */
v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+#ifdef CONFIG_MX51
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
+ else
+ v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
@@ -167,6 +186,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
else
v |= MXC_OTG_UCTRL_OPM_BIT;
#endif
+#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
+ else
+ v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
@@ -186,9 +211,19 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
else
v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
#endif
+#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
+ else
+ v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H1_OC_POL_BIT;
+ else
+ v &= ~MXC_H1_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
else
@@ -205,10 +240,18 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
#endif
#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
+ else
+ v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
else
v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
+ else
+ v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
#endif
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
@@ -216,10 +259,18 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
#ifdef CONFIG_MX53
case 3: /* Host 3 ULPI */
v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
+ else
+ v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
else
v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
+ else
+ v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
break;
diff --git u-boot-usb-76454b2.orig/include/usb/ehci-fsl.h u-boot-usb-76454b2/include/usb/ehci-fsl.h
index 4dee5b0..a1438d6 100644
--- u-boot-usb-76454b2.orig/include/usb/ehci-fsl.h
+++ u-boot-usb-76454b2/include/usb/ehci-fsl.h
@@ -266,11 +266,13 @@ struct usb_ehci {
#define MXC_EHCI_INTERFACE_MASK (0xf)
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
-#define MXC_EHCI_TTL_ENABLED (1 << 6)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
+#define MXC_EHCI_TTL_ENABLED (1 << 8)
-#define MXC_EHCI_INTERNAL_PHY (1 << 7)
-#define MXC_EHCI_IPPUE_DOWN (1 << 8)
-#define MXC_EHCI_IPPUE_UP (1 << 9)
+#define MXC_EHCI_INTERNAL_PHY (1 << 9)
+#define MXC_EHCI_IPPUE_DOWN (1 << 10)
+#define MXC_EHCI_IPPUE_UP (1 << 11)
/* Board-specific initialization */
int board_ehci_hcd_init(int port);
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 09/13] ehci-mxc: Make i.MX25 EHCI configurable
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
` (6 preceding siblings ...)
2012-11-08 20:29 ` [U-Boot] [PATCH v2 08/13] ehci-mxc: Make EHCI power/oc polarities configurable Benoît Thébaudeau
@ 2012-11-08 20:30 ` Benoît Thébaudeau
2012-11-08 20:30 ` [U-Boot] [PATCH v2 10/13] ehci-mxc: Define host offsets Benoît Thébaudeau
` (5 subsequent siblings)
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:30 UTC (permalink / raw)
To: u-boot
Use EHCI MXC configuration options for i.MX25.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matthias Weisser <weisserm@arcor.de>
---
Changes for v2: None.
.../drivers/usb/host/ehci-mxc.c | 71 +++++++++++++++++---
.../include/configs/zmx25.h | 6 +-
2 files changed, 66 insertions(+), 11 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
index e21f2c5..711c4a7 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
@@ -28,10 +28,21 @@
#define USBCTRL_OTGBASE_OFFSET 0x600
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
-#define MX25_USB_CTRL_HSTD_BIT (1<<5)
-#define MX25_USB_CTRL_USBTE_BIT (1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
+#define MX25_OTG_SIC_SHIFT 29
+#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BIT (1 << 24)
+#define MX25_OTG_PP_BIT (1 << 11)
+#define MX25_OTG_OCPOL_BIT (1 << 3)
+
+#define MX25_H1_SIC_SHIFT 21
+#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT (1 << 18)
+#define MX25_H1_PM_BIT (1 << 8)
+#define MX25_H1_IPPUE_UP_BIT (1 << 7)
+#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
+#define MX25_H1_TLL_BIT (1 << 5)
+#define MX25_H1_USBTE_BIT (1 << 4)
+#define MX25_H1_OCPOL_BIT (1 << 2)
#define MX31_OTG_SIC_SHIFT 29
#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
@@ -51,12 +62,56 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
-#if defined(CONFIG_MX25)
- v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
- MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#elif defined(CONFIG_MX31)
v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+#if defined(CONFIG_MX25)
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
+ MX25_OTG_OCPOL_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX25_OTG_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX25_OTG_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX25_OTG_OCPOL_BIT;
+
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
+ MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
+ MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX25_H1_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX25_H1_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX25_H1_OCPOL_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX25_H1_TLL_BIT;
+
+ if (flags & MXC_EHCI_INTERNAL_PHY)
+ v |= MX25_H1_USBTE_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_DOWN)
+ v |= MX25_H1_IPPUE_DOWN_BIT;
+ if (flags & MXC_EHCI_IPPUE_UP)
+ v |= MX25_H1_IPPUE_UP_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
+#elif defined(CONFIG_MX31)
switch (port) {
case 0: /* OTG port */
v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
diff --git u-boot-usb-76454b2.orig/include/configs/zmx25.h u-boot-usb-76454b2/include/configs/zmx25.h
index 447683a..e9216d9 100644
--- u-boot-usb-76454b2.orig/include/configs/zmx25.h
+++ u-boot-usb-76454b2/include/configs/zmx25.h
@@ -109,9 +109,9 @@
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT 2
-#define CONFIG_MXC_USB_PORTSC 0xC0000000
-#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
+#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 10/13] ehci-mxc: Define host offsets
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
` (7 preceding siblings ...)
2012-11-08 20:30 ` [U-Boot] [PATCH v2 09/13] ehci-mxc: Make i.MX25 EHCI configurable Benoît Thébaudeau
@ 2012-11-08 20:30 ` Benoît Thébaudeau
2012-11-08 20:30 ` [U-Boot] [PATCH v2 11/13] ehci-mxc: Add support for i.MX35 Benoît Thébaudeau
` (4 subsequent siblings)
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:30 UTC (permalink / raw)
To: u-boot
Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare
to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at
SoC level.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
.../arch/arm/include/asm/arch-mx25/imx-regs.h | 1 +
.../arch/arm/include/asm/arch-mx31/imx-regs.h | 1 +
.../drivers/usb/host/ehci-mxc.c | 2 +-
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx25/imx-regs.h u-boot-usb-76454b2/arch/arm/include/asm/arch-mx25/imx-regs.h
index e780296..c1bc4bc 100644
--- u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ u-boot-usb-76454b2/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -246,6 +246,7 @@ struct aips_regs {
#define IMX_RTIC_BASE (0x53FEC000)
#define IMX_IIM_BASE (0x53FF0000)
#define IMX_USB_BASE (0x53FF4000)
+#define IMX_USB_PORT_OFFSET 0x200
#define IMX_CSI_BASE (0x53FF8000)
#define IMX_DRYICE_BASE (0x53FFC000)
diff --git u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx31/imx-regs.h u-boot-usb-76454b2/arch/arm/include/asm/arch-mx31/imx-regs.h
index 01a849d..ae3658b 100644
--- u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ u-boot-usb-76454b2/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -895,6 +895,7 @@ struct esdc_regs {
#define MX31_AIPS1_BASE_ADDR 0x43f00000
#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_PORT_OFFSET 0x200
/*
* CSPI register definitions
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
index 711c4a7..cd09462 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
@@ -168,7 +168,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
udelay(80);
ehci = (struct usb_ehci *)(IMX_USB_BASE +
- (0x200 * CONFIG_MXC_USB_PORT));
+ IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 11/13] ehci-mxc: Add support for i.MX35
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
` (8 preceding siblings ...)
2012-11-08 20:30 ` [U-Boot] [PATCH v2 10/13] ehci-mxc: Define host offsets Benoît Thébaudeau
@ 2012-11-08 20:30 ` Benoît Thébaudeau
2012-11-08 20:31 ` [U-Boot] [PATCH v2 12/13] mx35pdk: Add support for OTG Benoît Thébaudeau
` (3 subsequent siblings)
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:30 UTC (permalink / raw)
To: u-boot
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
.../arch/arm/include/asm/arch-mx35/imx-regs.h | 2 +
.../drivers/usb/host/ehci-mxc.c | 68 ++++++++++++++++++++
2 files changed, 70 insertions(+)
diff --git u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx35/imx-regs.h u-boot-usb-76454b2/arch/arm/include/asm/arch-mx35/imx-regs.h
index 7b09809..cd7716f 100644
--- u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ u-boot-usb-76454b2/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -82,6 +82,8 @@
#define PWM_BASE_ADDR 0x53FE0000
#define RTIC_BASE_ADDR 0x53FEC000
#define IIM_BASE_ADDR 0x53FF0000
+#define IMX_USB_BASE 0x53FF4000
+#define IMX_USB_PORT_OFFSET 0x400
#define IMX_CCM_BASE CCM_BASE_ADDR
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
index cd09462..98b9e7c 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
@@ -58,6 +58,22 @@
#define MX31_H1_PM_BIT (1 << 8)
#define MX31_H1_DT_BIT (1 << 4)
+#define MX35_OTG_SIC_SHIFT 29
+#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
+#define MX35_OTG_PM_BIT (1 << 24)
+#define MX35_OTG_PP_BIT (1 << 11)
+#define MX35_OTG_OCPOL_BIT (1 << 3)
+
+#define MX35_H1_SIC_SHIFT 21
+#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PP_BIT (1 << 18)
+#define MX35_H1_PM_BIT (1 << 8)
+#define MX35_H1_IPPUE_UP_BIT (1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
+#define MX35_H1_TLL_BIT (1 << 5)
+#define MX35_H1_USBTE_BIT (1 << 4)
+#define MX35_H1_OCPOL_BIT (1 << 2)
+
static int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
@@ -146,6 +162,54 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
default:
return -EINVAL;
}
+#elif defined(CONFIG_MX35)
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
+ MX35_OTG_OCPOL_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX35_OTG_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX35_OTG_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX35_OTG_OCPOL_BIT;
+
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
+ MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
+ MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX35_H1_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX35_H1_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX35_H1_OCPOL_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX35_H1_TLL_BIT;
+
+ if (flags & MXC_EHCI_INTERNAL_PHY)
+ v |= MX35_H1_USBTE_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_DOWN)
+ v |= MX35_H1_IPPUE_DOWN_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_UP)
+ v |= MX35_H1_IPPUE_UP_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
#else
#error MXC EHCI USB driver not supported on this platform
#endif
@@ -175,6 +239,10 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
+#ifdef CONFIG_MX35
+ /* Workaround for ENGcm11601 */
+ __raw_writel(0, &ehci->sbuscfg);
+#endif
udelay(10000);
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 12/13] mx35pdk: Add support for OTG
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
` (9 preceding siblings ...)
2012-11-08 20:30 ` [U-Boot] [PATCH v2 11/13] ehci-mxc: Add support for i.MX35 Benoît Thébaudeau
@ 2012-11-08 20:31 ` Benoît Thébaudeau
2012-11-08 20:31 ` [U-Boot] [PATCH v2 13/13] ehci-mx5/6: Make board_ehci_hcd_init() optional Benoît Thébaudeau
` (2 subsequent siblings)
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:31 UTC (permalink / raw)
To: u-boot
Add support for the OTG port on the mx35pdk Personality board.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
---
Changes for v2:
- Tested by Stefano.
.../board/freescale/mx35pdk/lowlevel_init.S | 4 ++++
.../board/freescale/mx35pdk/mx35pdk.c | 19 +++++++++++++++++++
.../include/configs/mx35pdk.h | 14 ++++++++++++++
3 files changed, 37 insertions(+)
diff --git u-boot-usb-76454b2.orig/board/freescale/mx35pdk/lowlevel_init.S u-boot-usb-76454b2/board/freescale/mx35pdk/lowlevel_init.S
index 698c4cf..6f4d4e0 100644
--- u-boot-usb-76454b2.orig/board/freescale/mx35pdk/lowlevel_init.S
+++ u-boot-usb-76454b2/board/freescale/mx35pdk/lowlevel_init.S
@@ -178,6 +178,10 @@
orr r1, r1, #0x00000C00
orr r1, r1, #0x00000003
str r1, [r0, #CLKCTL_CGR1]
+
+ ldr r1, [r0, #CLKCTL_CGR2]
+ orr r1, r1, #0x00C00000
+ str r1, [r0, #CLKCTL_CGR2]
.endm
.macro setup_sdram
diff --git u-boot-usb-76454b2.orig/board/freescale/mx35pdk/mx35pdk.c u-boot-usb-76454b2/board/freescale/mx35pdk/mx35pdk.c
index 7cb6b30..e9ef4d1 100644
--- u-boot-usb-76454b2.orig/board/freescale/mx35pdk/mx35pdk.c
+++ u-boot-usb-76454b2/board/freescale/mx35pdk/mx35pdk.c
@@ -97,6 +97,24 @@ static void setup_iomux_spi(void)
mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
}
+static void setup_iomux_usbotg(void)
+{
+ int in_pad, out_pad;
+
+ /* Set up pins for USBOTG. */
+ mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+ in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+ out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+ PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+
static void setup_iomux_fec(void)
{
int pad;
@@ -188,6 +206,7 @@ int board_early_init_f(void)
__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
setup_iomux_i2c();
+ setup_iomux_usbotg();
setup_iomux_fec();
setup_iomux_spi();
diff --git u-boot-usb-76454b2.orig/include/configs/mx35pdk.h u-boot-usb-76454b2/include/configs/mx35pdk.h
index 826c912..69b7d23 100644
--- u-boot-usb-76454b2.orig/include/configs/mx35pdk.h
+++ u-boot-usb-76454b2/include/configs/mx35pdk.h
@@ -110,6 +110,8 @@
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_CMD_DATE
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
@@ -242,6 +244,18 @@
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
+/* EHCI driver */
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_MXC_USB_PORT 0
+#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \
+ MXC_EHCI_POWER_PINS_ENABLED | \
+ MXC_EHCI_OC_PIN_ACTIVE_LOW)
+#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
+
/* mmc driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 13/13] ehci-mx5/6: Make board_ehci_hcd_init() optional
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
` (10 preceding siblings ...)
2012-11-08 20:31 ` [U-Boot] [PATCH v2 12/13] mx35pdk: Add support for OTG Benoît Thébaudeau
@ 2012-11-08 20:31 ` Benoît Thébaudeau
2012-11-10 7:42 ` [U-Boot] [PATCH v2 01/13] mx31: Move EHCI definitions to ehci-fsl.h Stefano Babic
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
13 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-08 20:31 UTC (permalink / raw)
To: u-boot
A custom board_ehci_hcd_init() may be unneeded, so add a weak default
implementation doing nothing.
By the way, use simple __weak from linux/compiler.h for
board_ehci_hcd_postinit() instead of weak alias with full attribute.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
- Use simple __weak from linux/compiler.h instead of __attribute__.
- Also use __weak instead of __attribute__ for board_ehci_hcd_postinit().
- Extend to ehci-mx6.c.
.../drivers/usb/host/ehci-mx5.c | 8 +++++---
.../drivers/usb/host/ehci-mx6.c | 5 +++++
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 52aeae5..be43d90 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -280,12 +280,14 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
return ret;
}
-void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+int __weak board_ehci_hcd_init(int port)
{
+ return 0;
}
-void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
- __attribute((weak, alias("__board_ehci_hcd_postinit")));
+void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+{
+}
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx6.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx6.c
index 9ce25da..1b20e41 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx6.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx6.c
@@ -159,6 +159,11 @@ static void usbh1_oc_config(void)
__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
}
+int __weak board_ehci_hcd_init(int port)
+{
+ return 0;
+}
+
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 01/13] mx31: Move EHCI definitions to ehci-fsl.h
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
` (11 preceding siblings ...)
2012-11-08 20:31 ` [U-Boot] [PATCH v2 13/13] ehci-mx5/6: Make board_ehci_hcd_init() optional Benoît Thébaudeau
@ 2012-11-10 7:42 ` Stefano Babic
2012-11-10 12:37 ` Benoît Thébaudeau
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
13 siblings, 1 reply; 54+ messages in thread
From: Stefano Babic @ 2012-11-10 7:42 UTC (permalink / raw)
To: u-boot
On 08/11/2012 21:27, Beno?t Th?baudeau wrote:
> The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to
> ehci-fsl.h so that all MXC SoCs can use them.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
Hi Beno?t,
> Changes for v2: None.
>
> .../arch/arm/include/asm/arch-mx31/imx-regs.h | 26 --------------------
> .../include/usb/ehci-fsl.h | 22 +++++++++++++++++
> 2 files changed, 22 insertions(+), 26 deletions(-)
>
By applying this patchset I see several minor issues reported by checkpatch:
WARNING: line over 80 characters
#303: FILE: drivers/usb/host/ehci-mx5.c:43:
+#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
WARNING: line over 80 characters
#305: FILE: drivers/usb/host/ehci-mx5.c:45:
+#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
WARNING: line over 80 characters
#306: FILE: drivers/usb/host/ehci-mx5.c:46:
+#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
WARNING: line over 80 characters
#312: FILE: drivers/usb/host/ehci-mx5.c:50:
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent
Event */
WARNING: line over 80 characters
#313: FILE: drivers/usb/host/ehci-mx5.c:51:
+#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
WARNING: line over 80 characters
#343: FILE: drivers/usb/host/ehci-mx5.c:174:
+ v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
WARNING: line over 80 characters
#352: FILE: drivers/usb/host/ehci-mx5.c:190:
+ v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
WARNING: line over 80 characters
#641: FILE: drivers/usb/host/ehci-mx5.c:47:
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* OTG power pin polarity */
WARNING: line over 80 characters
#645: FILE: drivers/usb/host/ehci-mx5.c:51:
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* HOST1 power pin polarity */
WARNING: line over 80 characters
#648: FILE: drivers/usb/host/ehci-mx5.c:54:
+#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of
Overcurrent */
WARNING: line over 80 characters
#650: FILE: drivers/usb/host/ehci-mx5.c:56:
+#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */
WARNING: line over 80 characters
#652: FILE: drivers/usb/host/ehci-mx5.c:58:
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */
WARNING: line over 80 characters
#873: FILE: drivers/usb/host/ehci-mxc.c:85:
+ MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
WARNING: line over 80 characters
#1078: FILE: drivers/usb/host/ehci-mxc.c:184:
+ MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
WARNING: line over 80 characters
#1179: FILE: board/freescale/mx35pdk/mx35pdk.c:105:
+ mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
WARNING: line over 80 characters
#1180: FILE: board/freescale/mx35pdk/mx35pdk.c:106:
+ mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
total: 0 errors, 16 warnings, 810 lines checked
Can you fix them ? Thanks !
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================
^ permalink raw reply [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v2 01/13] mx31: Move EHCI definitions to ehci-fsl.h
2012-11-10 7:42 ` [U-Boot] [PATCH v2 01/13] mx31: Move EHCI definitions to ehci-fsl.h Stefano Babic
@ 2012-11-10 12:37 ` Benoît Thébaudeau
2012-11-10 12:46 ` Albert ARIBAUD
2012-11-10 16:45 ` stefano babic
0 siblings, 2 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-10 12:37 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Saturday, November 10, 2012 8:42:24 AM, Stefano Babic wrote:
> On 08/11/2012 21:27, Beno?t Th?baudeau wrote:
> > The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so
> > move them to
> > ehci-fsl.h so that all MXC SoCs can use them.
> >
> > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Stefano Babic <sbabic@denx.de>
> > ---
>
> Hi Beno?t,
>
> > Changes for v2: None.
> >
> > .../arch/arm/include/asm/arch-mx31/imx-regs.h | 26
> > --------------------
> > .../include/usb/ehci-fsl.h | 22
> > +++++++++++++++++
> > 2 files changed, 22 insertions(+), 26 deletions(-)
> >
>
> By applying this patchset I see several minor issues reported by
> checkpatch:
>
> WARNING: line over 80 characters
> #303: FILE: drivers/usb/host/ehci-mx5.c:43:
> +#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable
> */
>
> WARNING: line over 80 characters
> #305: FILE: drivers/usb/host/ehci-mx5.c:45:
> +#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt
> enable */
>
> WARNING: line over 80 characters
> #306: FILE: drivers/usb/host/ehci-mx5.c:46:
> +#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr
> enable */
>
> WARNING: line over 80 characters
> #312: FILE: drivers/usb/host/ehci-mx5.c:50:
> +#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable
> Overcurrent
> Event */
>
> WARNING: line over 80 characters
> #313: FILE: drivers/usb/host/ehci-mx5.c:51:
> +#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event
> */
>
> WARNING: line over 80 characters
> #343: FILE: drivers/usb/host/ehci-mx5.c:174:
> + v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
>
> WARNING: line over 80 characters
> #352: FILE: drivers/usb/host/ehci-mx5.c:190:
> + v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
>
> WARNING: line over 80 characters
> #641: FILE: drivers/usb/host/ehci-mx5.c:47:
> +#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* OTG power pin
> polarity */
>
> WARNING: line over 80 characters
> #645: FILE: drivers/usb/host/ehci-mx5.c:51:
> +#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* HOST1 power pin
> polarity */
>
> WARNING: line over 80 characters
> #648: FILE: drivers/usb/host/ehci-mx5.c:54:
> +#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of
> Overcurrent */
>
> WARNING: line over 80 characters
> #650: FILE: drivers/usb/host/ehci-mx5.c:56:
> +#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent
> */
>
> WARNING: line over 80 characters
> #652: FILE: drivers/usb/host/ehci-mx5.c:58:
> +#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin
> Polarity */
>
> WARNING: line over 80 characters
> #873: FILE: drivers/usb/host/ehci-mxc.c:85:
> + MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
>
> WARNING: line over 80 characters
> #1078: FILE: drivers/usb/host/ehci-mxc.c:184:
> + MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
>
> WARNING: line over 80 characters
> #1179: FILE: board/freescale/mx35pdk/mx35pdk.c:105:
> + mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION |
> MUX_CONFIG_FUNC);
>
> WARNING: line over 80 characters
> #1180: FILE: board/freescale/mx35pdk/mx35pdk.c:106:
> + mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION |
> MUX_CONFIG_FUNC);
>
> total: 0 errors, 16 warnings, 810 lines checked
>
> Can you fix them ? Thanks !
OK, I'll do that. For the #define-s, do you prefer that I move the comment to
the previous line, or that I split the end of the comment to the next line?
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 54+ messages in thread
* [U-Boot] [PATCH v2 01/13] mx31: Move EHCI definitions to ehci-fsl.h
2012-11-10 12:37 ` Benoît Thébaudeau
@ 2012-11-10 12:46 ` Albert ARIBAUD
2012-11-10 12:47 ` Albert ARIBAUD
2012-11-10 16:45 ` stefano babic
1 sibling, 1 reply; 54+ messages in thread
From: Albert ARIBAUD @ 2012-11-10 12:46 UTC (permalink / raw)
To: u-boot
Hi Beno?t,
On Sat, 10 Nov 2012 13:37:12 +0100 (CET), Beno?t Th?baudeau
<benoit.thebaudeau@advansee.com> wrote:
> Hi Stefano,
>
> On Saturday, November 10, 2012 8:42:24 AM, Stefano Babic wrote:
> > On 08/11/2012 21:27, Beno?t Th?baudeau wrote:
> > > The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so
> > > move them to
> > > ehci-fsl.h so that all MXC SoCs can use them.
> > >
> > > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > > Cc: Marek Vasut <marex@denx.de>
> > > Cc: Stefano Babic <sbabic@denx.de>
> > > ---
> >
> > Hi Beno?t,
> >
> > > Changes for v2: None.
> > >
> > > .../arch/arm/include/asm/arch-mx31/imx-regs.h | 26
> > > --------------------
> > > .../include/usb/ehci-fsl.h | 22
> > > +++++++++++++++++
> > > 2 files changed, 22 insertions(+), 26 deletions(-)
> > >
> >
> > By applying this patchset I see several minor issues reported by
> > checkpatch:
> >
> > WARNING: line over 80 characters
> > #303: FILE: drivers/usb/host/ehci-mx5.c:43:
> > +#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable
> > */
> >
> > WARNING: line over 80 characters
> > #305: FILE: drivers/usb/host/ehci-mx5.c:45:
> > +#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt
> > enable */
> >
> > WARNING: line over 80 characters
> > #306: FILE: drivers/usb/host/ehci-mx5.c:46:
> > +#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr
> > enable */
> >
> > WARNING: line over 80 characters
> > #312: FILE: drivers/usb/host/ehci-mx5.c:50:
> > +#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable
> > Overcurrent
> > Event */
> >
> > WARNING: line over 80 characters
> > #313: FILE: drivers/usb/host/ehci-mx5.c:51:
> > +#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event
> > */
> >
> > WARNING: line over 80 characters
> > #343: FILE: drivers/usb/host/ehci-mx5.c:174:
> > + v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
> >
> > WARNING: line over 80 characters
> > #352: FILE: drivers/usb/host/ehci-mx5.c:190:
> > + v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
> >
> > WARNING: line over 80 characters
> > #641: FILE: drivers/usb/host/ehci-mx5.c:47:
> > +#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* OTG power pin
> > polarity */
> >
> > WARNING: line over 80 characters
> > #645: FILE: drivers/usb/host/ehci-mx5.c:51:
> > +#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* HOST1 power pin
> > polarity */
> >
> > WARNING: line over 80 characters
> > #648: FILE: drivers/usb/host/ehci-mx5.c:54:
> > +#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of
> > Overcurrent */
> >
> > WARNING: line over 80 characters
> > #650: FILE: drivers/usb/host/ehci-mx5.c:56:
> > +#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent
> > */
> >
> > WARNING: line over 80 characters
> > #652: FILE: drivers/usb/host/ehci-mx5.c:58:
> > +#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin
> > Polarity */
> >
> > WARNING: line over 80 characters
> > #873: FILE: drivers/usb/host/ehci-mxc.c:85:
> > + MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
> >
> > WARNING: line over 80 characters
> > #1078: FILE: drivers/usb/host/ehci-mxc.c:184:
> > + MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
> >
> > WARNING: line over 80 characters
> > #1179: FILE: board/freescale/mx35pdk/mx35pdk.c:105:
> > + mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION |
> > MUX_CONFIG_FUNC);
> >
> > WARNING: line over 80 characters
> > #1180: FILE: board/freescale/mx35pdk/mx35pdk.c:106:
> > + mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION |
> > MUX_CONFIG_FUNC);
> >
> > total: 0 errors, 16 warnings, 810 lines checked
> >
> > Can you fix them ? Thanks !
>
> OK, I'll do that. For the #define-s, do you prefer that I move the comment to
> the previous line, or that I split the end of the comment to the next line?
I'll let Stefano give a definitive answer of course, but I personally
prefer that comments be moved before the defines.
> Best regards,
> Beno?t
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 54+ messages in thread
* [U-Boot] [PATCH v2 01/13] mx31: Move EHCI definitions to ehci-fsl.h
2012-11-10 12:46 ` Albert ARIBAUD
@ 2012-11-10 12:47 ` Albert ARIBAUD
2012-11-10 13:51 ` Benoît Thébaudeau
0 siblings, 1 reply; 54+ messages in thread
From: Albert ARIBAUD @ 2012-11-10 12:47 UTC (permalink / raw)
To: u-boot
> I'll let Stefano give a definitive answer of course, but I personally
> prefer that comments be moved before the defines.
Note: I mean that each comment should precede its corresponding define,
of course; I don't want all these comments lumped together in a single
block.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 54+ messages in thread
* [U-Boot] [PATCH v2 01/13] mx31: Move EHCI definitions to ehci-fsl.h
2012-11-10 12:47 ` Albert ARIBAUD
@ 2012-11-10 13:51 ` Benoît Thébaudeau
0 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-10 13:51 UTC (permalink / raw)
To: u-boot
On Saturday, November 10, 2012 1:47:51 PM, Albert ARIBAUD wrote:
> > I'll let Stefano give a definitive answer of course, but I
> > personally
> > prefer that comments be moved before the defines.
>
> Note: I mean that each comment should precede its corresponding
> define,
> of course; I don't want all these comments lumped together in a
> single
> block.
Sure. And if some comments fit at the end of the line, but not all, do you
prefer to also move these fitting comments to the previous line for more
consistency?
Cordialement,
Beno?t
^ permalink raw reply [flat|nested] 54+ messages in thread
* [U-Boot] [PATCH v2 01/13] mx31: Move EHCI definitions to ehci-fsl.h
2012-11-10 12:37 ` Benoît Thébaudeau
2012-11-10 12:46 ` Albert ARIBAUD
@ 2012-11-10 16:45 ` stefano babic
1 sibling, 0 replies; 54+ messages in thread
From: stefano babic @ 2012-11-10 16:45 UTC (permalink / raw)
To: u-boot
Am 10/11/2012 13:37, schrieb Beno?t Th?baudeau:
> Hi Stefano,
>
> On Saturday, November 10, 2012 8:42:24 AM, Stefano Babic wrote:
>> On 08/11/2012 21:27, Beno?t Th?baudeau wrote:
>>> The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so
>>> move them to
>>> ehci-fsl.h so that all MXC SoCs can use them.
>>>
>>> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
>>> Cc: Marek Vasut <marex@denx.de>
>>> Cc: Stefano Babic <sbabic@denx.de>
>>> ---
>>
>> Hi Beno?t,
>>
>>> Changes for v2: None.
>>>
>>> .../arch/arm/include/asm/arch-mx31/imx-regs.h | 26
>>> --------------------
>>> .../include/usb/ehci-fsl.h | 22
>>> +++++++++++++++++
>>> 2 files changed, 22 insertions(+), 26 deletions(-)
>>>
>>
>> By applying this patchset I see several minor issues reported by
>> checkpatch:
>>
>> WARNING: line over 80 characters
>> #303: FILE: drivers/usb/host/ehci-mx5.c:43:
>> +#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable
>> */
>>
>> WARNING: line over 80 characters
>> #305: FILE: drivers/usb/host/ehci-mx5.c:45:
>> +#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt
>> enable */
>>
>> WARNING: line over 80 characters
>> #306: FILE: drivers/usb/host/ehci-mx5.c:46:
>> +#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr
>> enable */
>>
>> WARNING: line over 80 characters
>> #312: FILE: drivers/usb/host/ehci-mx5.c:50:
>> +#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable
>> Overcurrent
>> Event */
>>
>> WARNING: line over 80 characters
>> #313: FILE: drivers/usb/host/ehci-mx5.c:51:
>> +#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event
>> */
>>
>> WARNING: line over 80 characters
>> #343: FILE: drivers/usb/host/ehci-mx5.c:174:
>> + v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
>>
>> WARNING: line over 80 characters
>> #352: FILE: drivers/usb/host/ehci-mx5.c:190:
>> + v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
>>
>> WARNING: line over 80 characters
>> #641: FILE: drivers/usb/host/ehci-mx5.c:47:
>> +#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* OTG power pin
>> polarity */
>>
>> WARNING: line over 80 characters
>> #645: FILE: drivers/usb/host/ehci-mx5.c:51:
>> +#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* HOST1 power pin
>> polarity */
>>
>> WARNING: line over 80 characters
>> #648: FILE: drivers/usb/host/ehci-mx5.c:54:
>> +#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of
>> Overcurrent */
>>
>> WARNING: line over 80 characters
>> #650: FILE: drivers/usb/host/ehci-mx5.c:56:
>> +#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent
>> */
>>
>> WARNING: line over 80 characters
>> #652: FILE: drivers/usb/host/ehci-mx5.c:58:
>> +#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin
>> Polarity */
>>
>> WARNING: line over 80 characters
>> #873: FILE: drivers/usb/host/ehci-mxc.c:85:
>> + MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
>>
>> WARNING: line over 80 characters
>> #1078: FILE: drivers/usb/host/ehci-mxc.c:184:
>> + MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
>>
>> WARNING: line over 80 characters
>> #1179: FILE: board/freescale/mx35pdk/mx35pdk.c:105:
>> + mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION |
>> MUX_CONFIG_FUNC);
>>
>> WARNING: line over 80 characters
>> #1180: FILE: board/freescale/mx35pdk/mx35pdk.c:106:
>> + mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION |
>> MUX_CONFIG_FUNC);
>>
>> total: 0 errors, 16 warnings, 810 lines checked
>>
>> Can you fix them ? Thanks !
>
> OK, I'll do that. For the #define-s, do you prefer that I move the comment to
> the previous line, or that I split the end of the comment to the next line?
I have no preference, I usually move the comment to the previous line,
but it is a question of taste ;-)
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 54+ messages in thread
* [U-Boot] [PATCH v3 01/13] mx31: Move EHCI definitions to ehci-fsl.h
2012-11-08 20:27 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
` (12 preceding siblings ...)
2012-11-10 7:42 ` [U-Boot] [PATCH v2 01/13] mx31: Move EHCI definitions to ehci-fsl.h Stefano Babic
@ 2012-11-13 19:55 ` Benoît Thébaudeau
2012-11-13 19:55 ` [U-Boot] [PATCH v3 02/13] ehci-mxc: Clean up Benoît Thébaudeau
` (11 more replies)
13 siblings, 12 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:55 UTC (permalink / raw)
To: u-boot
The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to
ehci-fsl.h so that all MXC SoCs can use them.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
Changes for v3: None.
.../arch/arm/include/asm/arch-mx31/imx-regs.h | 26 --------------------
.../include/usb/ehci-fsl.h | 22 +++++++++++++++++
2 files changed, 22 insertions(+), 26 deletions(-)
diff --git u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx31/imx-regs.h u-boot-usb-76454b2/arch/arm/include/asm/arch-mx31/imx-regs.h
index 8fd3d08..01a849d 100644
--- u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ u-boot-usb-76454b2/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -896,32 +896,6 @@ struct esdc_regs {
#define MX31_AIPS1_BASE_ADDR 0x43f00000
#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
-/* USB portsc */
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
-#define MXC_EHCI_FORCE_FS (1 << 24)
-#define MXC_EHCI_UTMI_8BIT (0 << 28)
-#define MXC_EHCI_UTMI_16BIT (1 << 28)
-#define MXC_EHCI_SERIAL (1 << 29)
-#define MXC_EHCI_MODE_UTMI (0 << 30)
-#define MXC_EHCI_MODE_PHILIPS (1 << 30)
-#define MXC_EHCI_MODE_ULPI (2 << 30)
-#define MXC_EHCI_MODE_SERIAL (3 << 30)
-
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
-#define MXC_EHCI_INTERFACE_MASK (0xf)
-
-#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
-#define MXC_EHCI_TTL_ENABLED (1 << 6)
-
-#define MXC_EHCI_INTERNAL_PHY (1 << 7)
-#define MXC_EHCI_IPPUE_DOWN (1 << 8)
-#define MXC_EHCI_IPPUE_UP (1 << 9)
-
/*
* CSPI register definitions
*/
diff --git u-boot-usb-76454b2.orig/include/usb/ehci-fsl.h u-boot-usb-76454b2/include/usb/ehci-fsl.h
index 2869302..4dee5b0 100644
--- u-boot-usb-76454b2.orig/include/usb/ehci-fsl.h
+++ u-boot-usb-76454b2/include/usb/ehci-fsl.h
@@ -246,9 +246,31 @@ struct usb_ehci {
/*
* For MXC SOCs
*/
+
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
+#define MXC_EHCI_FORCE_FS (1 << 24)
+#define MXC_EHCI_UTMI_8BIT (0 << 28)
+#define MXC_EHCI_UTMI_16BIT (1 << 28)
+#define MXC_EHCI_SERIAL (1 << 29)
+#define MXC_EHCI_MODE_UTMI (0 << 30)
+#define MXC_EHCI_MODE_PHILIPS (1 << 30)
+#define MXC_EHCI_MODE_ULPI (2 << 30)
+#define MXC_EHCI_MODE_SERIAL (3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
+#define MXC_EHCI_INTERFACE_MASK (0xf)
+
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
#define MXC_EHCI_TTL_ENABLED (1 << 6)
+
#define MXC_EHCI_INTERNAL_PHY (1 << 7)
+#define MXC_EHCI_IPPUE_DOWN (1 << 8)
+#define MXC_EHCI_IPPUE_UP (1 << 9)
/* Board-specific initialization */
int board_ehci_hcd_init(int port);
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 02/13] ehci-mxc: Clean up
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
@ 2012-11-13 19:55 ` Benoît Thébaudeau
2012-11-16 8:29 ` Stefano Babic
2012-11-13 19:56 ` [U-Boot] [PATCH v3 03/13] ehci-mx5: " Benoît Thébaudeau
` (10 subsequent siblings)
11 siblings, 1 reply; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:55 UTC (permalink / raw)
To: u-boot
Clean up ehci-mxc:
- Remove useless #if's.
- Fix identation.
- Issue a #error if used with an unsupported platform.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
Changes for v3: None.
.../drivers/usb/host/ehci-mxc.c | 86 +++++++++-----------
1 file changed, 40 insertions(+), 46 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
index a38bc9c..e21f2c5 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
@@ -28,14 +28,11 @@
#define USBCTRL_OTGBASE_OFFSET 0x600
-#ifdef CONFIG_MX25
#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
#define MX25_USB_CTRL_HSTD_BIT (1<<5)
#define MX25_USB_CTRL_USBTE_BIT (1<<4)
#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
-#endif
-#ifdef CONFIG_MX31
#define MX31_OTG_SIC_SHIFT 29
#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
#define MX31_OTG_PM_BIT (1 << 24)
@@ -49,59 +46,56 @@
#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
#define MX31_H1_PM_BIT (1 << 8)
#define MX31_H1_DT_BIT (1 << 4)
-#endif
static int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25)
v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#endif
+#elif defined(CONFIG_MX31)
+ v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-#ifdef CONFIG_MX31
- v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-
- switch (port) {
- case 0: /* OTG port */
- v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK)
- << MX31_OTG_SIC_SHIFT;
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_OTG_PM_BIT;
-
- break;
- case 1: /* H1 port */
- v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
- MX31_H1_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK)
- << MX31_H1_SIC_SHIFT;
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_H1_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX31_H1_DT_BIT;
-
- break;
- case 2: /* H2 port */
- v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
- MX31_H2_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK)
- << MX31_H2_SIC_SHIFT;
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_H2_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX31_H2_DT_BIT;
-
- break;
- default:
- return -EINVAL;
- }
-#endif
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_OTG_PM_BIT;
+
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_H1_PM_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX31_H1_DT_BIT;
+
+ break;
+ case 2: /* H2 port */
+ v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_H2_PM_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX31_H2_DT_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
+#else
+#error MXC EHCI USB driver not supported on this platform
+#endif
writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+
return 0;
}
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 02/13] ehci-mxc: Clean up
2012-11-13 19:55 ` [U-Boot] [PATCH v3 02/13] ehci-mxc: Clean up Benoît Thébaudeau
@ 2012-11-16 8:29 ` Stefano Babic
0 siblings, 0 replies; 54+ messages in thread
From: Stefano Babic @ 2012-11-16 8:29 UTC (permalink / raw)
To: u-boot
On 13/11/2012 20:55, Beno?t Th?baudeau wrote:
> Clean up ehci-mxc:
> - Remove useless #if's.
> - Fix identation.
> - Issue a #error if used with an unsupported platform.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
Applied (whole sries) to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 54+ messages in thread
* [U-Boot] [PATCH v3 03/13] ehci-mx5: Clean up
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
2012-11-13 19:55 ` [U-Boot] [PATCH v3 02/13] ehci-mxc: Clean up Benoît Thébaudeau
@ 2012-11-13 19:56 ` Benoît Thébaudeau
2012-11-13 19:56 ` [U-Boot] [PATCH v3 04/13] ehci-mx5: Fix OC_DIS usage Benoît Thébaudeau
` (9 subsequent siblings)
11 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:56 UTC (permalink / raw)
To: u-boot
Clean up ehci-mx5:
- Fix column alignments.
- Fix comments.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
Changes for v3:
- Fix lines over 80 characters.
.../drivers/usb/host/ehci-mx5.c | 45 +++++++++++---------
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 9a2c295..46973b0 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -29,9 +29,9 @@
#define MX5_USBOTHER_REGS_OFFSET 0x800
-#define MXC_OTG_OFFSET 0
-#define MXC_H1_OFFSET 0x200
-#define MXC_H2_OFFSET 0x400
+#define MXC_OTG_OFFSET 0
+#define MXC_H1_OFFSET 0x200
+#define MXC_H2_OFFSET 0x400
#define MXC_USBCTRL_OFFSET 0
#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
@@ -40,23 +40,30 @@
#define MXC_USBH2CTRL_OFFSET 0x14
/* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
+/* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
+/* OTG power mask */
+#define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
+/* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
+/* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
+/* HOST1 power mask */
+#define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
/* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
+/* OTG Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
+/* UH1 Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT (1 << 5)
/* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
/* USB_CTRL_1 */
-#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
+#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
/* USB pin configuration */
#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
@@ -160,7 +167,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
- case 1: /* Host 1 Host ULPI */
+ case 1: /* Host 1 ULPI */
#ifdef CONFIG_MX51
/* The clock for the USBH1 ULPI port will come externally
from the PHY. */
@@ -171,9 +178,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+ v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
else
- v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+ v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
@@ -187,9 +194,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
case 2: /* Host 2 ULPI */
v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+ v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
else
- v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+ v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
break;
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 04/13] ehci-mx5: Fix OC_DIS usage
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
2012-11-13 19:55 ` [U-Boot] [PATCH v3 02/13] ehci-mxc: Clean up Benoît Thébaudeau
2012-11-13 19:56 ` [U-Boot] [PATCH v3 03/13] ehci-mx5: " Benoît Thébaudeau
@ 2012-11-13 19:56 ` Benoît Thébaudeau
2012-11-13 19:56 ` [U-Boot] [PATCH v3 05/13] ehci-mx5: Fix OPM usage Benoît Thébaudeau
` (8 subsequent siblings)
11 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:56 UTC (permalink / raw)
To: u-boot
MXC_OTG_PHYCTRL_OC_DIS_BIT disables the oc pin if set, like MXC_H1_OC_DIS_BIT,
not the opposite.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
Changes for v3: None.
.../drivers/usb/host/ehci-mx5.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 46973b0..72cde1a 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -151,11 +151,11 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v = __raw_readl(usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- /* OC/USBPWR is not used */
- v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
- else
/* OC/USBPWR is used */
v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+ else
+ /* OC/USBPWR is not used */
+ v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
__raw_writel(v, usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 05/13] ehci-mx5: Fix OPM usage
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
` (2 preceding siblings ...)
2012-11-13 19:56 ` [U-Boot] [PATCH v3 04/13] ehci-mx5: Fix OC_DIS usage Benoît Thébaudeau
@ 2012-11-13 19:56 ` Benoît Thébaudeau
2012-11-13 19:56 ` [U-Boot] [PATCH v3 06/13] ehci-mx5: Fix *PM usage for i.MX53 Benoît Thébaudeau
` (7 subsequent siblings)
11 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:56 UTC (permalink / raw)
To: u-boot
MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like
MXC_H1_UCTRL_H1PM_BIT and MXC_H2_UCTRL_H2PM_BIT, not the opposite.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
Changes for v3: None.
.../drivers/usb/host/ehci-mx5.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 72cde1a..8c1b70a 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -161,9 +161,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- v |= MXC_OTG_UCTRL_OPM_BIT;
- else
v &= ~MXC_OTG_UCTRL_OPM_BIT;
+ else
+ v |= MXC_OTG_UCTRL_OPM_BIT;
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 06/13] ehci-mx5: Fix *PM usage for i.MX53
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
` (3 preceding siblings ...)
2012-11-13 19:56 ` [U-Boot] [PATCH v3 05/13] ehci-mx5: Fix OPM usage Benoît Thébaudeau
@ 2012-11-13 19:56 ` Benoît Thébaudeau
2012-11-13 19:57 ` [U-Boot] [PATCH v3 07/13] ehci-mx5: Add missing OC_DIS " Benoît Thébaudeau
` (6 subsequent siblings)
11 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:56 UTC (permalink / raw)
To: u-boot
The MXC_*_UCTRL_*PM_BIT bits are available only on i.MX51.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
Changes for v3: None.
.../drivers/usb/host/ehci-mx5.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 8c1b70a..4f4b98a 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -160,10 +160,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
MXC_USB_PHY_CTR_FUNC_OFFSET);
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_OTG_UCTRL_OPM_BIT;
else
v |= MXC_OTG_UCTRL_OPM_BIT;
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
@@ -177,10 +179,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
#endif
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
else
v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
@@ -193,11 +197,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
break;
case 2: /* Host 2 ULPI */
v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+#ifdef CONFIG_MX51
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
else
v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
-
+#endif
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
break;
}
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 07/13] ehci-mx5: Add missing OC_DIS for i.MX53
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
` (4 preceding siblings ...)
2012-11-13 19:56 ` [U-Boot] [PATCH v3 06/13] ehci-mx5: Fix *PM usage for i.MX53 Benoît Thébaudeau
@ 2012-11-13 19:57 ` Benoît Thébaudeau
2012-11-13 19:57 ` [U-Boot] [PATCH v3 08/13] ehci-mxc: Make EHCI power/oc polarities configurable Benoît Thébaudeau
` (5 subsequent siblings)
11 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:57 UTC (permalink / raw)
To: u-boot
The i.MX53 has MXC_H*_UCTRL_H*_OC_DIS_BIT bits to disable the oc pin.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
Changes for v3: None.
.../drivers/usb/host/ehci-mx5.c | 24 ++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 4f4b98a..6f7fe80 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -32,12 +32,14 @@
#define MXC_OTG_OFFSET 0
#define MXC_H1_OFFSET 0x200
#define MXC_H2_OFFSET 0x400
+#define MXC_H3_OFFSET 0x600
#define MXC_USBCTRL_OFFSET 0
#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
#define MXC_USB_CTRL_1_OFFSET 0x10
#define MXC_USBH2CTRL_OFFSET 0x14
+#define MXC_USBH3CTRL_OFFSET 0x18
/* USB_CTRL */
/* OTG wakeup intr enable */
@@ -58,10 +60,16 @@
#define MXC_H1_OC_DIS_BIT (1 << 5)
/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+/* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
+#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
+#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
+
/* USB_CTRL_1 */
#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
@@ -203,8 +211,24 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
else
v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
#endif
+#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
+ else
+ v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+#endif
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
break;
+#ifdef CONFIG_MX53
+ case 3: /* Host 3 ULPI */
+ v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
+ else
+ v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+ __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
+ break;
+#endif
}
return ret;
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 08/13] ehci-mxc: Make EHCI power/oc polarities configurable
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
` (5 preceding siblings ...)
2012-11-13 19:57 ` [U-Boot] [PATCH v3 07/13] ehci-mx5: Add missing OC_DIS " Benoît Thébaudeau
@ 2012-11-13 19:57 ` Benoît Thébaudeau
2012-11-13 19:57 ` [U-Boot] [PATCH v3 09/13] ehci-mxc: Make i.MX25 EHCI configurable Benoît Thébaudeau
` (4 subsequent siblings)
11 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:57 UTC (permalink / raw)
To: u-boot
Make EHCI power and overcurrent polarities configurable. If not set, these new
configurartions keep the default register values so that existing board files
do not have to be changed.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
Changes for v3:
- Fix lines over 80 characters.
.../drivers/usb/host/ehci-mx5.c | 56 ++++++++++++++++++++
.../include/usb/ehci-fsl.h | 10 ++--
2 files changed, 62 insertions(+), 4 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 6f7fe80..7e60c3c 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -46,29 +46,43 @@
#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
/* OTG power mask */
#define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
+/* OTG power pin polarity */
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
/* Host1 ULPI interrupt enable */
#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
/* HOST1 wakeup intr enable */
#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
/* HOST1 power mask */
#define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
+/* HOST1 power pin polarity */
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
/* USB_PHY_CTRL_FUNC */
+/* OTG Polarity of Overcurrent */
+#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
/* OTG Disable Overcurrent Event */
#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
+/* UH1 Polarity of Overcurrent */
+#define MXC_H1_OC_POL_BIT (1 << 6)
/* UH1 Disable Overcurrent Event */
#define MXC_H1_OC_DIS_BIT (1 << 5)
+/* OTG Power Pin Polarity */
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
/* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
+#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
/* USB_CTRL_1 */
#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
@@ -158,12 +172,22 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
if (flags & MXC_EHCI_INTERNAL_PHY) {
v = __raw_readl(usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
+ else
+ v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
/* OC/USBPWR is used */
v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
else
/* OC/USBPWR is not used */
v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+#ifdef CONFIG_MX51
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
+ else
+ v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
@@ -174,6 +198,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
else
v |= MXC_OTG_UCTRL_OPM_BIT;
#endif
+#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
+ else
+ v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
@@ -193,9 +223,19 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
else
v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
#endif
+#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
+ else
+ v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H1_OC_POL_BIT;
+ else
+ v &= ~MXC_H1_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
else
@@ -212,20 +252,36 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
#endif
#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
+ else
+ v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
else
v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
+ else
+ v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
#endif
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
break;
#ifdef CONFIG_MX53
case 3: /* Host 3 ULPI */
v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
+ else
+ v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
else
v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
+ else
+ v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
break;
#endif
diff --git u-boot-usb-76454b2.orig/include/usb/ehci-fsl.h u-boot-usb-76454b2/include/usb/ehci-fsl.h
index 4dee5b0..a1438d6 100644
--- u-boot-usb-76454b2.orig/include/usb/ehci-fsl.h
+++ u-boot-usb-76454b2/include/usb/ehci-fsl.h
@@ -266,11 +266,13 @@ struct usb_ehci {
#define MXC_EHCI_INTERFACE_MASK (0xf)
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
-#define MXC_EHCI_TTL_ENABLED (1 << 6)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
+#define MXC_EHCI_TTL_ENABLED (1 << 8)
-#define MXC_EHCI_INTERNAL_PHY (1 << 7)
-#define MXC_EHCI_IPPUE_DOWN (1 << 8)
-#define MXC_EHCI_IPPUE_UP (1 << 9)
+#define MXC_EHCI_INTERNAL_PHY (1 << 9)
+#define MXC_EHCI_IPPUE_DOWN (1 << 10)
+#define MXC_EHCI_IPPUE_UP (1 << 11)
/* Board-specific initialization */
int board_ehci_hcd_init(int port);
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 09/13] ehci-mxc: Make i.MX25 EHCI configurable
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
` (6 preceding siblings ...)
2012-11-13 19:57 ` [U-Boot] [PATCH v3 08/13] ehci-mxc: Make EHCI power/oc polarities configurable Benoît Thébaudeau
@ 2012-11-13 19:57 ` Benoît Thébaudeau
2012-11-13 19:57 ` [U-Boot] [PATCH v3 10/13] ehci-mxc: Define host offsets Benoît Thébaudeau
` (3 subsequent siblings)
11 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:57 UTC (permalink / raw)
To: u-boot
Use EHCI MXC configuration options for i.MX25.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matthias Weisser <weisserm@arcor.de>
---
Changes for v2: None.
Changes for v3:
- Fix lines over 80 characters.
.../drivers/usb/host/ehci-mxc.c | 72 +++++++++++++++++---
.../include/configs/zmx25.h | 6 +-
2 files changed, 67 insertions(+), 11 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
index e21f2c5..846aa3b 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
@@ -28,10 +28,21 @@
#define USBCTRL_OTGBASE_OFFSET 0x600
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
-#define MX25_USB_CTRL_HSTD_BIT (1<<5)
-#define MX25_USB_CTRL_USBTE_BIT (1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
+#define MX25_OTG_SIC_SHIFT 29
+#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BIT (1 << 24)
+#define MX25_OTG_PP_BIT (1 << 11)
+#define MX25_OTG_OCPOL_BIT (1 << 3)
+
+#define MX25_H1_SIC_SHIFT 21
+#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT (1 << 18)
+#define MX25_H1_PM_BIT (1 << 8)
+#define MX25_H1_IPPUE_UP_BIT (1 << 7)
+#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
+#define MX25_H1_TLL_BIT (1 << 5)
+#define MX25_H1_USBTE_BIT (1 << 4)
+#define MX25_H1_OCPOL_BIT (1 << 2)
#define MX31_OTG_SIC_SHIFT 29
#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
@@ -51,12 +62,57 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
-#if defined(CONFIG_MX25)
- v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
- MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#elif defined(CONFIG_MX31)
v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+#if defined(CONFIG_MX25)
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
+ MX25_OTG_OCPOL_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX25_OTG_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX25_OTG_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX25_OTG_OCPOL_BIT;
+
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
+ MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
+ MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
+ MX25_H1_IPPUE_UP_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX25_H1_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX25_H1_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX25_H1_OCPOL_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX25_H1_TLL_BIT;
+
+ if (flags & MXC_EHCI_INTERNAL_PHY)
+ v |= MX25_H1_USBTE_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_DOWN)
+ v |= MX25_H1_IPPUE_DOWN_BIT;
+ if (flags & MXC_EHCI_IPPUE_UP)
+ v |= MX25_H1_IPPUE_UP_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
+#elif defined(CONFIG_MX31)
switch (port) {
case 0: /* OTG port */
v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
diff --git u-boot-usb-76454b2.orig/include/configs/zmx25.h u-boot-usb-76454b2/include/configs/zmx25.h
index 447683a..e9216d9 100644
--- u-boot-usb-76454b2.orig/include/configs/zmx25.h
+++ u-boot-usb-76454b2/include/configs/zmx25.h
@@ -109,9 +109,9 @@
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT 2
-#define CONFIG_MXC_USB_PORTSC 0xC0000000
-#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
+#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 10/13] ehci-mxc: Define host offsets
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
` (7 preceding siblings ...)
2012-11-13 19:57 ` [U-Boot] [PATCH v3 09/13] ehci-mxc: Make i.MX25 EHCI configurable Benoît Thébaudeau
@ 2012-11-13 19:57 ` Benoît Thébaudeau
2012-11-13 19:58 ` [U-Boot] [PATCH v3 11/13] ehci-mxc: Add support for i.MX35 Benoît Thébaudeau
` (2 subsequent siblings)
11 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:57 UTC (permalink / raw)
To: u-boot
Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare
to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at
SoC level.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
Changes for v3: None.
.../arch/arm/include/asm/arch-mx25/imx-regs.h | 1 +
.../arch/arm/include/asm/arch-mx31/imx-regs.h | 1 +
.../drivers/usb/host/ehci-mxc.c | 2 +-
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx25/imx-regs.h u-boot-usb-76454b2/arch/arm/include/asm/arch-mx25/imx-regs.h
index e780296..c1bc4bc 100644
--- u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ u-boot-usb-76454b2/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -246,6 +246,7 @@ struct aips_regs {
#define IMX_RTIC_BASE (0x53FEC000)
#define IMX_IIM_BASE (0x53FF0000)
#define IMX_USB_BASE (0x53FF4000)
+#define IMX_USB_PORT_OFFSET 0x200
#define IMX_CSI_BASE (0x53FF8000)
#define IMX_DRYICE_BASE (0x53FFC000)
diff --git u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx31/imx-regs.h u-boot-usb-76454b2/arch/arm/include/asm/arch-mx31/imx-regs.h
index 01a849d..ae3658b 100644
--- u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ u-boot-usb-76454b2/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -895,6 +895,7 @@ struct esdc_regs {
#define MX31_AIPS1_BASE_ADDR 0x43f00000
#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_PORT_OFFSET 0x200
/*
* CSPI register definitions
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
index 846aa3b..6260a8c 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
@@ -169,7 +169,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
udelay(80);
ehci = (struct usb_ehci *)(IMX_USB_BASE +
- (0x200 * CONFIG_MXC_USB_PORT));
+ IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 11/13] ehci-mxc: Add support for i.MX35
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
` (8 preceding siblings ...)
2012-11-13 19:57 ` [U-Boot] [PATCH v3 10/13] ehci-mxc: Define host offsets Benoît Thébaudeau
@ 2012-11-13 19:58 ` Benoît Thébaudeau
2012-11-13 19:58 ` [U-Boot] [PATCH v3 12/13] mx35pdk: Add support for OTG Benoît Thébaudeau
2012-11-13 19:58 ` [U-Boot] [PATCH v3 13/13] ehci-mx5/6: Make board_ehci_hcd_init() optional Benoît Thébaudeau
11 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:58 UTC (permalink / raw)
To: u-boot
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2: None.
Changes for v3:
- Fix lines over 80 characters.
.../arch/arm/include/asm/arch-mx35/imx-regs.h | 2 +
.../drivers/usb/host/ehci-mxc.c | 69 ++++++++++++++++++++
2 files changed, 71 insertions(+)
diff --git u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx35/imx-regs.h u-boot-usb-76454b2/arch/arm/include/asm/arch-mx35/imx-regs.h
index 7b09809..cd7716f 100644
--- u-boot-usb-76454b2.orig/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ u-boot-usb-76454b2/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -82,6 +82,8 @@
#define PWM_BASE_ADDR 0x53FE0000
#define RTIC_BASE_ADDR 0x53FEC000
#define IIM_BASE_ADDR 0x53FF0000
+#define IMX_USB_BASE 0x53FF4000
+#define IMX_USB_PORT_OFFSET 0x400
#define IMX_CCM_BASE CCM_BASE_ADDR
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
index 6260a8c..7c5f71c 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mxc.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mxc.c
@@ -58,6 +58,22 @@
#define MX31_H1_PM_BIT (1 << 8)
#define MX31_H1_DT_BIT (1 << 4)
+#define MX35_OTG_SIC_SHIFT 29
+#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
+#define MX35_OTG_PM_BIT (1 << 24)
+#define MX35_OTG_PP_BIT (1 << 11)
+#define MX35_OTG_OCPOL_BIT (1 << 3)
+
+#define MX35_H1_SIC_SHIFT 21
+#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PP_BIT (1 << 18)
+#define MX35_H1_PM_BIT (1 << 8)
+#define MX35_H1_IPPUE_UP_BIT (1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
+#define MX35_H1_TLL_BIT (1 << 5)
+#define MX35_H1_USBTE_BIT (1 << 4)
+#define MX35_H1_OCPOL_BIT (1 << 2)
+
static int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
@@ -147,6 +163,55 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
default:
return -EINVAL;
}
+#elif defined(CONFIG_MX35)
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
+ MX35_OTG_OCPOL_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX35_OTG_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX35_OTG_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX35_OTG_OCPOL_BIT;
+
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
+ MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
+ MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
+ MX35_H1_IPPUE_UP_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX35_H1_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX35_H1_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX35_H1_OCPOL_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX35_H1_TLL_BIT;
+
+ if (flags & MXC_EHCI_INTERNAL_PHY)
+ v |= MX35_H1_USBTE_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_DOWN)
+ v |= MX35_H1_IPPUE_DOWN_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_UP)
+ v |= MX35_H1_IPPUE_UP_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
#else
#error MXC EHCI USB driver not supported on this platform
#endif
@@ -176,6 +241,10 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
+#ifdef CONFIG_MX35
+ /* Workaround for ENGcm11601 */
+ __raw_writel(0, &ehci->sbuscfg);
+#endif
udelay(10000);
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 12/13] mx35pdk: Add support for OTG
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
` (9 preceding siblings ...)
2012-11-13 19:58 ` [U-Boot] [PATCH v3 11/13] ehci-mxc: Add support for i.MX35 Benoît Thébaudeau
@ 2012-11-13 19:58 ` Benoît Thébaudeau
2012-11-13 19:58 ` [U-Boot] [PATCH v3 13/13] ehci-mx5/6: Make board_ehci_hcd_init() optional Benoît Thébaudeau
11 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:58 UTC (permalink / raw)
To: u-boot
Add support for the OTG port on the mx35pdk Personality board.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
---
Changes for v2:
- Tested by Stefano.
Changes for v3:
- Fix lines over 80 characters.
.../board/freescale/mx35pdk/lowlevel_init.S | 4 ++++
.../board/freescale/mx35pdk/mx35pdk.c | 21 ++++++++++++++++++++
.../include/configs/mx35pdk.h | 14 +++++++++++++
3 files changed, 39 insertions(+)
diff --git u-boot-usb-76454b2.orig/board/freescale/mx35pdk/lowlevel_init.S u-boot-usb-76454b2/board/freescale/mx35pdk/lowlevel_init.S
index 698c4cf..6f4d4e0 100644
--- u-boot-usb-76454b2.orig/board/freescale/mx35pdk/lowlevel_init.S
+++ u-boot-usb-76454b2/board/freescale/mx35pdk/lowlevel_init.S
@@ -178,6 +178,10 @@
orr r1, r1, #0x00000C00
orr r1, r1, #0x00000003
str r1, [r0, #CLKCTL_CGR1]
+
+ ldr r1, [r0, #CLKCTL_CGR2]
+ orr r1, r1, #0x00C00000
+ str r1, [r0, #CLKCTL_CGR2]
.endm
.macro setup_sdram
diff --git u-boot-usb-76454b2.orig/board/freescale/mx35pdk/mx35pdk.c u-boot-usb-76454b2/board/freescale/mx35pdk/mx35pdk.c
index 7cb6b30..4fa2c27 100644
--- u-boot-usb-76454b2.orig/board/freescale/mx35pdk/mx35pdk.c
+++ u-boot-usb-76454b2/board/freescale/mx35pdk/mx35pdk.c
@@ -97,6 +97,26 @@ static void setup_iomux_spi(void)
mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
}
+static void setup_iomux_usbotg(void)
+{
+ int in_pad, out_pad;
+
+ /* Set up pins for USBOTG. */
+ mxc_request_iomux(MX35_PIN_USBOTG_PWR,
+ MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_USBOTG_OC,
+ MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+ in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+ out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+ PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+
static void setup_iomux_fec(void)
{
int pad;
@@ -188,6 +208,7 @@ int board_early_init_f(void)
__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
setup_iomux_i2c();
+ setup_iomux_usbotg();
setup_iomux_fec();
setup_iomux_spi();
diff --git u-boot-usb-76454b2.orig/include/configs/mx35pdk.h u-boot-usb-76454b2/include/configs/mx35pdk.h
index 826c912..69b7d23 100644
--- u-boot-usb-76454b2.orig/include/configs/mx35pdk.h
+++ u-boot-usb-76454b2/include/configs/mx35pdk.h
@@ -110,6 +110,8 @@
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_CMD_DATE
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
@@ -242,6 +244,18 @@
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
+/* EHCI driver */
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_MXC_USB_PORT 0
+#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \
+ MXC_EHCI_POWER_PINS_ENABLED | \
+ MXC_EHCI_OC_PIN_ACTIVE_LOW)
+#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
+
/* mmc driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
^ permalink raw reply related [flat|nested] 54+ messages in thread* [U-Boot] [PATCH v3 13/13] ehci-mx5/6: Make board_ehci_hcd_init() optional
2012-11-13 19:55 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
` (10 preceding siblings ...)
2012-11-13 19:58 ` [U-Boot] [PATCH v3 12/13] mx35pdk: Add support for OTG Benoît Thébaudeau
@ 2012-11-13 19:58 ` Benoît Thébaudeau
11 siblings, 0 replies; 54+ messages in thread
From: Benoît Thébaudeau @ 2012-11-13 19:58 UTC (permalink / raw)
To: u-boot
A custom board_ehci_hcd_init() may be unneeded, so add a weak default
implementation doing nothing.
By the way, use simple __weak from linux/compiler.h for
board_ehci_hcd_postinit() instead of weak alias with full attribute.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
- Use simple __weak from linux/compiler.h instead of __attribute__.
- Also use __weak instead of __attribute__ for board_ehci_hcd_postinit().
- Extend to ehci-mx6.c.
Changes for v3: None.
.../drivers/usb/host/ehci-mx5.c | 8 +++++---
.../drivers/usb/host/ehci-mx6.c | 5 +++++
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 7e60c3c..adbed5c 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -290,12 +290,14 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
return ret;
}
-void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+int __weak board_ehci_hcd_init(int port)
{
+ return 0;
}
-void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
- __attribute((weak, alias("__board_ehci_hcd_postinit")));
+void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+{
+}
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx6.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx6.c
index 9ce25da..1b20e41 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx6.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx6.c
@@ -159,6 +159,11 @@ static void usbh1_oc_config(void)
__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
}
+int __weak board_ehci_hcd_init(int port)
+{
+ return 0;
+}
+
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
^ permalink raw reply related [flat|nested] 54+ messages in thread