From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Fri, 16 Nov 2012 14:17:26 +0100 Subject: [U-Boot] [PATCH 4/4] spi: mxc_spi: Fix spi clock glitch durant reset In-Reply-To: <1353014604-26493-4-git-send-email-festevam@gmail.com> References: <1353014604-26493-1-git-send-email-festevam@gmail.com> <1353014604-26493-4-git-send-email-festevam@gmail.com> Message-ID: <50A63CE6.4070909@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 15/11/2012 22:23, Fabio Estevam wrote: > From: Fabio Estevam > > Measuring the spi clock line on a scope shows a 'glitch' during the reset of the > spi. > > Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes > always stable. > > Signed-off-by: Fabio Estevam > --- > drivers/spi/mxc_spi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c > index 4bed4f0..102fca5 100644 > --- a/drivers/spi/mxc_spi.c > +++ b/drivers/spi/mxc_spi.c > @@ -140,8 +140,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, > reg_ctrl = reg_read(®s->ctrl); > > /* Reset spi */ > - reg_write(®s->ctrl, 0); > - reg_write(®s->ctrl, (reg_ctrl | 0x1)); > + reg_write(®s->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN)); > + reg_write(®s->ctrl, (reg_ctrl | MXC_CSPICTRL_EN)); > Right - the enabled was set after clearing the register, but before setting it. Acked-by: Stefano Babic Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================