[U-Boot] [PATCH 01/22] ARM: sunxi: Basic Allwinner A10/A13 (sun4i/sun5i) support

Luka Perkov
2012-11-25T12:23:28Z

Hi Henrik,

I have few comments bellow.

On Sun, Nov 25, 2012 at 12:37:30PM +0100, Henrik Nordstr?m wrote:
> This adds support for the Allwinner A10/A13 SoC's. Additionally
> board support for the dev-boards sun4i/sun5i is added.
>
> Signed-off-by: Tom Cubie <tangliang@allwinnertech.com>
> Signed-off-by: Henrik Nordstr?m <henrik@henriknordstrom.net>
> Signed-off-by: Stefan Roese <sr@denx.de>
> ---
> MAINTAINERS | 13 ++
> arch/arm/cpu/armv7/Makefile | 2 +-
> arch/arm/cpu/armv7/sunxi/Makefile | 51 +++++++
> arch/arm/cpu/armv7/sunxi/board.c | 77 +++++++++++
> arch/arm/cpu/armv7/sunxi/clock.c | 57 ++++++++
> arch/arm/cpu/armv7/sunxi/pinmux.c | 61 +++++++++
> arch/arm/cpu/armv7/sunxi/reset.S | 39 ++++++
> arch/arm/cpu/armv7/sunxi/timer.c | 117 +++++++++++++++++
> arch/arm/include/asm/arch-sunxi/clock.h | 179 +++++++++++++++++++++++++
> arch/arm/include/asm/arch-sunxi/cpu.h | 146 +++++++++++++++++++++
> arch/arm/include/asm/arch-sunxi/dram.h | 114 ++++++++++++++++
> arch/arm/include/asm/arch-sunxi/gpio.h | 164 +++++++++++++++++++++++
> arch/arm/include/asm/arch-sunxi/sys_proto.h | 32 +++++
> arch/arm/include/asm/arch-sunxi/timer.h | 102 ++++++++++++++
> board/sunxi/Makefile | 46 +++++++
> board/sunxi/board.c | 57 ++++++++
> boards.cfg | 4 +
> include/configs/sun4i.h | 47 +++++++
> include/configs/sun5i.h | 56 ++++++++
> include/configs/sunxi-common.h | 189 +++++++++++++++++++++++++++
> 20 files changed, 1552 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/cpu/armv7/sunxi/Makefile
> create mode 100644 arch/arm/cpu/armv7/sunxi/board.c
> create mode 100644 arch/arm/cpu/armv7/sunxi/clock.c
> create mode 100644 arch/arm/cpu/armv7/sunxi/pinmux.c
> create mode 100644 arch/arm/cpu/armv7/sunxi/reset.S
> create mode 100644 arch/arm/cpu/armv7/sunxi/timer.c
> create mode 100644 arch/arm/include/asm/arch-sunxi/clock.h
> create mode 100644 arch/arm/include/asm/arch-sunxi/cpu.h
> create mode 100644 arch/arm/include/asm/arch-sunxi/dram.h
> create mode 100644 arch/arm/include/asm/arch-sunxi/gpio.h
> create mode 100644 arch/arm/include/asm/arch-sunxi/sys_proto.h
> create mode 100644 arch/arm/include/asm/arch-sunxi/timer.h
> create mode 100644 board/sunxi/Makefile
> create mode 100644 board/sunxi/board.c
> create mode 100644 include/configs/sun4i.h
> create mode 100644 include/configs/sun5i.h
> create mode 100644 include/configs/sunxi-common.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c430574..80c1bd7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -331,6 +331,19 @@ Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
> TOP5200 MPC5200
> TOP9000 ARM926EJS (AT91SAM9xxx SoC)
>
> +Henrik Nordstrom <henrik@henriknordstrom.net>
> + A13_OLINUXINO ARM V7 (Allwinner A13 SoC)
> + A13_MID ARM V7 (Allwinner A13 SoC)
> + CUBIEBOARD ARM V7 (Allwinner A10 SoC)
> + CUBIEBOARD_512 ARM V7 (Allwinner A10 SoC)
> + HACKBERRY ARM V7 (Allwinner A10 SoC)
> + MELE_A1000 ARM V7 (Allwinner A10 SoC)
> + MINI-X ARM V7 (Allwinner A10 SoC)
> + SUN4I ARM V7 (Allwinner A10 SoC)
> + SUN4I_SDCON ARM V7 (Allwinner A10 SoC)
> + SUN5I ARM V7 (Allwinner A13 SoC)
> + SUN5I_SDCON ARM V7 (Allwinner A13 SoC)
> +
> Kyle Moffett <Kyle.D.Moffett@boeing.com>
>
> HWW1U1A P2020
> diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
> index da1b5e8..56f51b5 100644
> --- a/arch/arm/cpu/armv7/Makefile
> +++ b/arch/arm/cpu/armv7/Makefile
> @@ -33,7 +33,7 @@ COBJS += cpu.o
> COBJS += syslib.o
> COBJS += cmd_boot.o
>
> -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
> +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20)$(CONFIG_SUNXI),)
> SOBJS += lowlevel_init.o
> endif
>
> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
> new file mode 100644
> index 0000000..cbe1015
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
> @@ -0,0 +1,51 @@
> +#
> +# (C) Copyright 2000-2003

I don't know about the dates. It's 2012 now... Same goes for all other files.

> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(SOC).o
> +
> +SOBJS += reset.o
> +
> +COBJS += timer.o
> +COBJS += dram.o
> +COBJS += board.o
> +COBJS += clock.o
> +COBJS += pinmux.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
> +
> +all: $(obj).depend $(LIB)
> +
> +$(LIB): $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
> new file mode 100644
> index 0000000..652c19d
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/board.c
> @@ -0,0 +1,77 @@
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * Some init for sunxi platform.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <serial.h>
> +#include <asm/gpio.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/timer.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/sys_proto.h>
> +
> +int gpio_init(void)
> +{
> +#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
> +#ifdef CONFIG_SUN4I
> + /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
> + gpio_direction_input(SUNXI_GPB(22));
> + gpio_direction_input(SUNXI_GPB(23));
> +#endif
> + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
> + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN4I)
> + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
> + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
> +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
> + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART0_TX);
> + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART0_RX);
> +#else
> +#error Unsupported console port number. Please fix pin mux settings in board.c
> +#endif
> +
> + return 0;
> +}
> +
> +/* do some early init */
> +void s_init(void)
> +{
> + clock_init();
> + gpio_init();
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> + sunxi_reset();
> +}
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +void enable_caches(void)
> +{
> + /* Enable D-cache. I-cache is already enabled in start.S */
> + dcache_enable();
> +}
> +#endif
> diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
> new file mode 100644
> index 0000000..424acfc
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/clock.c
> @@ -0,0 +1,57 @@
> +/*
> + * (C) Copyright 2007-2012
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
> +
> +int clock_init(void)
> +{
> + struct sunxi_ccm_reg *const ccm =
> + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> +
> + /* uart clock source is apb1 */
> + sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
> + sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N);
> + sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M);
> +
> + /* open the clock for uart */
> + sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
> +
> + return 0;
> +}
> +
> +/* Return PLL5 frequency in Hz
> + * Note: Assumes PLL5 reference is 24MHz clock
> + */
> +unsigned int clock_get_pll5(void)
> +{
> + struct sunxi_ccm_reg *const ccm =
> + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> + uint32_t rval = readl(&ccm->pll5_cfg);
> + int n = (rval >> 8) & 0x1f;
> + int k = ((rval >> 4) & 3) + 1;
> + int p = 1 << ((rval >> 16) & 3);
> + return 24000000 * n * k / p;
> +}
> diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c
> new file mode 100644
> index 0000000..77e1d90
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/pinmux.c
> @@ -0,0 +1,61 @@
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/gpio.h>
> +
> +int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
> +{
> + u32 cfg;
> + u32 bank = GPIO_BANK(pin);
> + u32 index = GPIO_CFG_INDEX(pin);
> + u32 offset = GPIO_CFG_OFFSET(pin);
> + struct sunxi_gpio *pio =
> + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
> +
> + cfg = readl(&pio->cfg[0] + index);
> + cfg &= ~(0xf << offset);
> + cfg |= val << offset;
> +
> + writel(cfg, &pio->cfg[0] + index);
> +
> + return 0;
> +}
> +
> +int sunxi_gpio_get_cfgpin(u32 pin)
> +{
> + u32 cfg;
> + u32 bank = GPIO_BANK(pin);
> + u32 index = GPIO_CFG_INDEX(pin);
> + u32 offset = GPIO_CFG_OFFSET(pin);
> + struct sunxi_gpio *pio =
> + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
> +
> + cfg = readl(&pio->cfg[0] + index);
> + cfg >>= offset;
> +
> + return cfg & 0xf;
> +}
> +
> diff --git a/arch/arm/cpu/armv7/sunxi/reset.S b/arch/arm/cpu/armv7/sunxi/reset.S
> new file mode 100644
> index 0000000..36714e7
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/reset.S
> @@ -0,0 +1,39 @@
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * Configuration settings for the Allwinner A10-evb board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <asm/arch/cpu.h>
> +
> +#define SUNXI_WDOG_CTL 0x01C20C90
> +#define SUNXI_WDOG_MODE 0x01C20C94
> +
> +.globl sunxi_reset
> +sunxi_reset:
> + ldr r1, =SUNXI_WDOG_MODE
> + mov r3, #0x3
> + str r3, [r1]
> + mov r0, r0
> +_loop_forever:
> + b _loop_forever
> diff --git a/arch/arm/cpu/armv7/sunxi/timer.c b/arch/arm/cpu/armv7/sunxi/timer.c
> new file mode 100644
> index 0000000..e19df09
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/timer.c
> @@ -0,0 +1,117 @@
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/timer.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define TIMER_MODE (0 << 7) /* continuous mode */
> +#define TIMER_DIV (0 << 4) /* pre scale 1 */
> +#define TIMER_SRC (1 << 2) /* osc24m */
> +#define TIMER_RELOAD (1 << 1) /* reload internal value */
> +#define TIMER_EN (1 << 0) /* enable timer */
> +
> +#define TIMER_CLOCK (24 * 1000 * 1000)
> +#define COUNT_TO_USEC(x) ((x) / 24)
> +#define USEC_TO_COUNT(x) ((x) * 24)
> +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
> +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
> +
> +#define TIMER_LOAD_VAL 0xffffffff
> +
> +#define TIMER_NUM 0 /* we use timer 0 */
> +
> +static struct sunxi_timer *timer_base =
> + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->timer[TIMER_NUM];
> +
> +/* macro to read the 32 bit timer: since it decrements, we invert read value */
> +#define READ_TIMER() (~readl(&timer_base->val))
> +
> +/* init timer register */
> +int timer_init(void)
> +{
> + writel(TIMER_LOAD_VAL, &timer_base->inter);
> + writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
> + &timer_base->ctl);
> +
> + return 0;
> +}
> +
> +/* timer without interrupts */
> +ulong get_timer(ulong base)
> +{
> + return get_timer_masked() - base;
> +}
> +
> +ulong get_timer_masked(void)
> +{
> + /* current tick value */
> + ulong now = TICKS_TO_HZ(READ_TIMER());
> +
> + if (now >= gd->lastinc) /* normal (non rollover) */
> + gd->tbl += (now - gd->lastinc);
> + else /* rollover */
> + gd->tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - gd->lastinc) + now;
> + gd->lastinc = now;
> +
> + return gd->tbl;
> +}
> +
> +/* delay x useconds */
> +void __udelay(unsigned long usec)
> +{
> + long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
> + ulong now, last = READ_TIMER();
> +
> + while (tmo > 0) {
> + now = READ_TIMER();
> + if (now > last) /* normal (non rollover) */
> + tmo -= now - last;
> + else /* rollover */
> + tmo -= TIMER_LOAD_VAL - last + now;
> + last = now;
> + }
> +}
> +
> +/*
> + * This function is derived from PowerPC code (read timebase as long long).
> + * On ARM it just returns the timer value.
> + */
> +unsigned long long get_ticks(void)
> +{
> + return get_timer(0);
> +}
> +
> +/*
> + * This function is derived from PowerPC code (timebase clock frequency).
> + * On ARM it returns the number of timer ticks per second.
> + */
> +ulong get_tbclk(void)
> +{
> + ulong tbclk;
> + tbclk = CONFIG_SYS_HZ;
> + return tbclk;
> +}
> diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
> new file mode 100644
> index 0000000..863e59e
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/clock.h
> @@ -0,0 +1,179 @@
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _SUNXI_CLOCK_H
> +#define _SUNXI_CLOCK_H
> +
> +/* clock control module regs definition */
> +
> +struct sunxi_ccm_reg {
> + u32 pll1_cfg; /* 0x00 pll1 control */
> + u32 pll1_tun; /* 0x04 pll1 tuning */
> + u32 pll2_cfg; /* 0x08 pll2 control */
> + u32 pll2_tun; /* 0x0c pll2 tuning */
> + u32 pll3_cfg; /* 0x10 pll3 control */
> + u8 res0[0x4];
> + u32 pll4_cfg; /* 0x18 pll4 control */
> + u8 res1[0x4];
> + u32 pll5_cfg; /* 0x20 pll5 control */
> + u32 pll5_tun; /* 0x24 pll5 tuning */
> + u32 pll6_cfg; /* 0x28 pll6 control */
> + u32 pll6_tun; /* 0x2c pll6 tuning */
> + u32 pll7_cfg; /* 0x30 pll7 control */
> + u32 pll1_tun2; /* 0x34 pll5 tuning2 */
> + u8 res2[0x4];
> + u32 pll5_tun2; /* 0x3c pll5 tuning2 */
> + u8 res3[0xc];
> + u32 pll_lock_dbg; /* 0x4c pll lock time debug */
> + u32 osc24m_cfg; /* 0x50 osc24m control */
> + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */
> + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */
> + u32 axi_gate; /* 0x5c axi module clock gating */
> + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
> + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
> + u32 apb0_gate; /* 0x68 apb0 module clock gating */
> + u32 apb1_gate; /* 0x6c apb1 module clock gating */
> + u8 res4[0x10];
> + u32 nand_sclk_cfg; /* 0x80 nand sub clock control */
> + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */
> + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
> + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
> + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
> + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
> + u32 ts_clk_cfg; /* 0x98 transport stream clock control */
> + u32 ss_clk_cfg; /* 0x9c */
> + u32 spi0_clk_cfg; /* 0xa0 */
> + u32 spi1_clk_cfg; /* 0xa4 */
> + u32 spi2_clk_cfg; /* 0xa8 */
> + u32 pata_clk_cfg; /* 0xac */
> + u32 ir0_clk_cfg; /* 0xb0 */
> + u32 ir1_clk_cfg; /* 0xb4 */
> + u32 iis_clk_cfg; /* 0xb8 */
> + u32 ac97_clk_cfg; /* 0xbc */
> + u32 spdif_clk_cfg; /* 0xc0 */
> + u32 keypad_clk_cfg; /* 0xc4 */
> + u32 sata_clk_cfg; /* 0xc8 */
> + u32 usb_clk_cfg; /* 0xcc */
> + u32 gps_clk_cfg; /* 0xd0 */
> + u32 spi3_clk_cfg; /* 0xd4 */
> + u8 res5[0x28];
> + u32 dram_clk_cfg; /* 0x100 */
> + u32 be0_clk_cfg; /* 0x104 */
> + u32 be1_clk_cfg; /* 0x108 */
> + u32 fe0_clk_cfg; /* 0x10c */
> + u32 fe1_clk_cfg; /* 0x110 */
> + u32 mp_clk_cfg; /* 0x114 */
> + u32 lcd0_ch0_clk_cfg; /* 0x118 */
> + u32 lcd1_ch0_clk_cfg; /* 0x11c */
> + u32 csi_isp_clk_cfg; /* 0x120 */
> + u8 res6[0x4];
> + u32 tvd_clk_reg; /* 0x128 */
> + u32 lcd0_ch1_clk_cfg; /* 0x12c */
> + u32 lcd1_ch1_clk_cfg; /* 0x130 */
> + u32 csi0_clk_cfg; /* 0x134 */
> + u32 csi1_clk_cfg; /* 0x138 */
> + u32 ve_clk_cfg; /* 0x13c */
> + u32 audio_codec_clk_cfg; /* 0x140 */
> + u32 avs_clk_cfg; /* 0x144 */
> + u32 ace_clk_cfg; /* 0x148 */
> + u32 lvds_clk_cfg; /* 0x14c */
> + u32 hdmi_clk_cfg; /* 0x150 */
> + u32 mali_clk_cfg; /* 0x154 */
> + u8 res7[0x4];
> + u32 mbus_clk_cfg; /* 0x15c */
> +};
> +
> +/* apb1 bit field */
> +#define APB1_CLK_SRC_OSC24M 0
> +#define APB1_FACTOR_M 0
> +#define APB1_FACTOR_N 0
> +
> +/* clock divide */
> +#define CPU_CLK_SRC_OSC24M 1
> +#define CPU_CLK_SRC_PLL1 2
> +#define AXI_DIV_1 0
> +#define AXI_DIV_2 1
> +#define AXI_DIV_3 2
> +#define AXI_DIV_4 3
> +#define AHB_DIV_1 0
> +#define AHB_DIV_2 1
> +#define AHB_DIV_4 2
> +#define AHB_DIV_8 3
> +#define APB0_DIV_1 0
> +#define APB0_DIV_2 1
> +#define APB0_DIV_4 2
> +#define APB0_DIV_8 3
> +
> +#ifdef CONFIG_SUN5I
> +#define AHB_CLK_SRC_AXI 0
> +#endif
> +
> +#define CLK_GATE_OPEN 0x1
> +#define CLK_GATE_CLOSE 0x0
> +
> +/* nand clock */
> +#define NAND_CLK_SRC_OSC24 0
> +#define NAND_CLK_DIV_N 0
> +#define NAND_CLK_DIV_M 0
> +
> +/* gps clock */
> +#define GPS_SCLK_GATING_OFF 0
> +#define GPS_RESET 0
> +
> +/* ahb clock gate bit offset */
> +#define AHB_GATE_OFFSET_GPS 26
> +#define AHB_GATE_OFFSET_SATA 25
> +#define AHB_GATE_OFFSET_PATA 24
> +#define AHB_GATE_OFFSET_SPI3 23
> +#define AHB_GATE_OFFSET_SPI2 22
> +#define AHB_GATE_OFFSET_SPI1 21
> +#define AHB_GATE_OFFSET_SPI0 20
> +#define AHB_GATE_OFFSET_TS0 18
> +#define AHB_GATE_OFFSET_EMAC 17
> +#define AHB_GATE_OFFSET_ACE 16
> +#define AHB_GATE_OFFSET_DLL 15
> +#define AHB_GATE_OFFSET_SDRAM 14
> +#define AHB_GATE_OFFSET_NAND 13
> +#define AHB_GATE_OFFSET_MS 12
> +#define AHB_GATE_OFFSET_MMC3 11
> +#define AHB_GATE_OFFSET_MMC2 10
> +#define AHB_GATE_OFFSET_MMC1 9
> +#define AHB_GATE_OFFSET_MMC0 8
> +#define AHB_GATE_OFFSET_BIST 7
> +#define AHB_GATE_OFFSET_DMA 6
> +#define AHB_GATE_OFFSET_SS 5
> +#define AHB_GATE_OFFSET_USB_OHCI1 4
> +#define AHB_GATE_OFFSET_USB_EHCI1 3
> +#define AHB_GATE_OFFSET_USB_OHCI0 2
> +#define AHB_GATE_OFFSET_USB_EHCI0 1
> +#define AHB_GATE_OFFSET_USB 0
> +
> +#ifndef __ASSEMBLY__
> +int clock_init(void);
> +int clock_twi_onoff(int port, int state);
> +void clock_set_pll1(int mhz);
> +unsigned int clock_get_pll5(void);
> +#endif
> +
> +#endif /* _SUNXI_CLOCK_H */
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
> new file mode 100644
> index 0000000..6c8eaeb
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> @@ -0,0 +1,146 @@
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _SUNXI_CPU_H
> +#define _SUNXI_CPU_H
> +
> +#define SUNXI_SRAM_A1_BASE 0x00000000
> +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16k */
> +
> +#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16k */
> +#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13k */
> +#define SUNXI_SRAM_A4_BASE 0x0000B400 /* 3k */
> +#define SUNXI_SRAM_D_BASE 0x01C00000
> +#define SUNXI_SRAM_B_BASE 0x01C00000 /* 64k(secure) */
> +
> +#define SUNXI_SRAMC_BASE 0x01C00000
> +#define SUNXI_DRAMC_BASE 0x01C01000
> +#define SUNXI_DMA_BASE 0x01C02000
> +#define SUNXI_NFC_BASE 0x01C03000
> +#define SUNXI_TS_BASE 0x01C04000
> +#define SUNXI_SPI0_BASE 0x01C05000
> +#define SUNXI_SPI1_BASE 0x01C06000
> +#define SUNXI_MS_BASE 0x01C07000
> +#define SUNXI_TVD_BASE 0x01C08000
> +#define SUNXI_CSI0_BASE 0x01C09000
> +#define SUNXI_TVE0_BASE 0x01C0A000
> +#define SUNXI_EMAC_BASE 0x01C0B000
> +#define SUNXI_LCD0_BASE 0x01C0C000
> +#define SUNXI_LCD1_BASE 0x01C0D000
> +#define SUNXI_VE_BASE 0x01C0E000
> +#define SUNXI_MMC0_BASE 0x01C0F000
> +#define SUNXI_MMC1_BASE 0x01C10000
> +#define SUNXI_MMC2_BASE 0x01C11000
> +#define SUNXI_MMC3_BASE 0x01C12000
> +#define SUNXI_USB0_BASE 0x01C13000
> +#define SUNXI_USB1_BASE 0x01C14000
> +#define SUNXI_SS_BASE 0x01C15000
> +#define SUNXI_HDMI_BASE 0x01C16000
> +#define SUNXI_SPI2_BASE 0x01C17000
> +#define SUNXI_SATA_BASE 0x01C18000
> +#define SUNXI_PATA_BASE 0x01C19000
> +#define SUNXI_ACE_BASE 0x01C1A000
> +#define SUNXI_TVE1_BASE 0x01C1B000
> +#define SUNXI_USB2_BASE 0x01C1C000
> +#define SUNXI_CSI1_BASE 0x01C1D000
> +#define SUNXI_TZASC_BASE 0x01C1E000
> +#define SUNXI_SPI3_BASE 0x01C1F000
> +
> +#define SUNXI_CCM_BASE 0x01C20000
> +#define SUNXI_INTC_BASE 0x01C20400
> +#define SUNXI_PIO_BASE 0x01C20800
> +#define SUNXI_TIMER_BASE 0x01C20C00
> +#define SUNXI_SPDIF_BASE 0x01C21000
> +#define SUNXI_AC97_BASE 0x01C21400
> +#define SUNXI_IR0_BASE 0x01C21800
> +#define SUNXI_IR1_BASE 0x01C21C00
> +
> +#define SUNXI_IIS_BASE 0x01C22400
> +#define SUNXI_LRADC_BASE 0x01C22800
> +#define SUNXI_AD_DA_BASE 0x01C22C00
> +#define SUNXI_KEYPAD_BASE 0x01C23000
> +#define SUNXI_TZPC_BASE 0x01C23400
> +#define SUNXI_SID_BASE 0x01C23800
> +#define SUNXI_SJTAG_BASE 0x01C23C00
> +
> +#define SUNXI_TP_BASE 0x01C25000
> +#define SUNXI_PMU_BASE 0x01C25400
> +
> +#define SUNXI_UART0_BASE 0x01C28000
> +#define SUNXI_UART1_BASE 0x01C28400
> +#define SUNXI_UART2_BASE 0x01C28800
> +#define SUNXI_UART3_BASE 0x01C28C00
> +#define SUNXI_UART4_BASE 0x01C29000
> +#define SUNXI_UART5_BASE 0x01C29400
> +#define SUNXI_UART6_BASE 0x01C29800
> +#define SUNXI_UART7_BASE 0x01C29C00
> +#define SUNXI_PS2_0_BASE 0x01C2A000
> +#define SUNXI_PS2_1_BASE 0x01C2A400
> +
> +#define SUNXI_TWI0_BASE 0x01C2AC00
> +#define SUNXI_TWI1_BASE 0x01C2B000
> +#define SUNXI_TWI2_BASE 0x01C2B400
> +
> +#define SUNXI_CAN_BASE 0x01C2BC00
> +
> +#define SUNXI_SCR_BASE 0x01C2C400
> +
> +#define SUNXI_GPS_BASE 0x01C30000
> +#define SUNXI_MALI400_BASE 0x01C40000
> +
> +/* module sram */
> +#define SUNXI_SRAM_C_BASE 0x01D00000
> +
> +#define SUNXI_DE_FE0_BASE 0x01E00000
> +#define SUNXI_DE_FE1_BASE 0x01E20000
> +#define SUNXI_DE_BE0_BASE 0x01E60000
> +#define SUNXI_DE_BE1_BASE 0x01E40000
> +#define SUNXI_MP_BASE 0x01E80000
> +#define SUNXI_AVG_BASE 0x01EA0000
> +
> +/* CoreSight Debug Module */
> +#define SUNXI_CSDM_BASE 0x3F500000
> +
> +#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2G */
> +
> +#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */
> +
> +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
> +
> +#ifndef __ASSEMBLY__
> +/* boot type */
> +enum sunxi_boot_type_t {
> + SUNXI_BOOT_TYPE_NULL,
> + SUNXI_BOOT_TYPE_MMC0,
> + SUNXI_BOOT_TYPE_NAND,
> + SUNXI_BOOT_TYPE_MMC2,
> + SUNXI_BOOT_TYPE_SPI
> +};
> +
> +sunxi_boot_type_t get_boot_type(void);
> +void sunxi_board_init(void);
> +extern void sunxi_reset(void);
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* _CPU_H */
> diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
> new file mode 100644
> index 0000000..d3c0e9f
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/dram.h
> @@ -0,0 +1,114 @@
> +/*
> + * (C) Copyright 2007-2012
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Berg Xing <bergxing@allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * Sunxi platform dram register definition.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _SUNXI_DRAM_H
> +#define _SUNXI_DRAM_H
> +
> +struct sunxi_dram_reg {
> + u32 ccr; /* 0x00 controller configuration register */
> + u32 dcr; /* 0x04 dram configuration register */
> + u32 iocr; /* 0x08 i/o configuration register */
> + u32 csr; /* 0x0c controller status register */
> + u32 drr; /* 0x10 dram refresh register */
> + u32 tpr0; /* 0x14 dram timing parameters register 0 */
> + u32 tpr1; /* 0x18 dram timing parameters register 1 */
> + u32 tpr2; /* 0x1c dram timing parameters register 2 */
> + u32 gdllcr; /* 0x20 global dll control register */
> + u8 res0[0x28];
> + u32 rslr0; /* 0x4c rank system latency register */
> + u32 rslr1; /* 0x50 rank system latency register */
> + u8 res1[0x8];
> + u32 rdgr0; /* 0x5c rank dqs gating register */
> + u32 rdgr1; /* 0x60 rank dqs gating register */
> + u8 res2[0x34];
> + u32 odtcr; /* 0x98 odt configuration register */
> + u32 dtr0; /* 0x9c data training register 0 */
> + u32 dtr1; /* 0xa0 data training register 1 */
> + u32 dtar; /* 0xa4 data training address register */
> + u32 zqcr0; /* 0xa8 zq control register 0 */
> + u32 zqcr1; /* 0xac zq control register 1 */
> + u32 zqsr; /* 0xb0 zq status register */
> + u32 idcr; /* 0xb4 initializaton delay configure reg */
> + u8 res3[0x138];
> + u32 mr; /* 0x1f0 mode register */
> + u32 emr; /* 0x1f4 extended mode register */
> + u32 emr2; /* 0x1f8 extended mode register */
> + u32 emr3; /* 0x1fc extended mode register */
> + u32 dllctr; /* 0x200 dll control register */
> + u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */
> + /* 0x208 dll control register 1(byte 1) */
> + /* 0x20c dll control register 2(byte 2) */
> + /* 0x210 dll control register 3(byte 3) */
> + /* 0x214 dll control register 4(byte 4) */
> + u32 dqtr0; /* 0x218 dq timing register */
> + u32 dqtr1; /* 0x21c dq timing register */
> + u32 dqtr2; /* 0x220 dq timing register */
> + u32 dqtr3; /* 0x224 dq timing register */
> + u32 dqstr; /* 0x228 dqs timing register */
> + u32 dqsbtr; /* 0x22c dqsb timing register */
> + u32 mcr; /* 0x230 mode configure register */
> + u8 res[0x8];
> + u32 ppwrsctl; /* 0x23c pad power save control */
> + u32 apr; /* 0x240 arbiter period register */
> + u32 pldtr; /* 0x244 priority level data threshold reg */
> + u8 res5[0x8];
> + u32 hpcr[32]; /* 0x250 host port configure register */
> + u8 res6[0x10];
> + u32 csel; /* 0x2e0 controller select register */
> +};
> +
> +struct dram_para {
> + u32 clock;
> + u32 type;
> + u32 rank_num;
> + u32 density;
> + u32 io_width;
> + u32 bus_width;
> + u32 cas;
> + u32 zq;
> + u32 odt_en;
> + u32 size;
> + u32 tpr0;
> + u32 tpr1;
> + u32 tpr2;
> + u32 tpr3;
> + u32 tpr4;
> + u32 tpr5;
> + u32 emr1;
> + u32 emr2;
> + u32 emr3;
> +};
> +
> +#define SUN5I_DRAM_MCR_DCLK_OUT_OFFSET 16
> +#define SUN4I_CCM_SDRAM_DCLK_OUT_OFFSET 15
> +
> +#define DRAM_CTRL_SELECT_MAGIC 0x16237495
> +
> +int sunxi_dram_init(void);
> +int dramc_init(struct dram_para *para);
> +
> +#endif /* _SUNXI_DRAM_H */
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> new file mode 100644
> index 0000000..fceee6b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -0,0 +1,164 @@
> +/*
> + * (C) Copyright 2007-2012
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _SUNXI_GPIO_H
> +#define _SUNXI_GPIO_H
> +
> +/*
> + * sunxi has 9 banks of gpio, they are:
> + * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
> + * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
> + * PG0 - PG9 | PH0 - PH27 | PI0 - PI12
> + */
> +
> +#define SUNXI_GPIO_A 0
> +#define SUNXI_GPIO_B 1
> +#define SUNXI_GPIO_C 2
> +#define SUNXI_GPIO_D 3
> +#define SUNXI_GPIO_E 4
> +#define SUNXI_GPIO_F 5
> +#define SUNXI_GPIO_G 6
> +#define SUNXI_GPIO_H 7
> +#define SUNXI_GPIO_I 8
> +
> +struct sunxi_gpio {
> + u32 cfg[4];
> + u32 dat;
> + u32 drv[2];
> + u32 pull[2];
> +};
> +
> +/* gpio interrupt control */
> +struct sunxi_gpio_int {
> + u32 cfg[3];
> + u32 ctl;
> + u32 sta;
> + u32 deb; /* interrupt debounce */
> +};
> +
> +struct sunxi_gpio_reg {
> + struct sunxi_gpio gpio_bank[9];
> + u8 res[0xbc];
> + struct sunxi_gpio_int gpio_int;
> +};
> +
> +#define GPIO_BANK(pin) ((pin) >> 5)
> +#define GPIO_NUM(pin) ((pin) & 0x1F)
> +
> +#define GPIO_CFG_INDEX(pin) (((pin) & 0x1F) >> 3)
> +#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1F) & 0x7) << 2)
> +
> +/* GPIO bank sizes */
> +#define SUNXI_GPIO_A_NR 32
> +#define SUNXI_GPIO_B_NR 32
> +#define SUNXI_GPIO_C_NR 32
> +#define SUNXI_GPIO_D_NR 32
> +#define SUNXI_GPIO_E_NR 32
> +#define SUNXI_GPIO_F_NR 32
> +#define SUNXI_GPIO_G_NR 32
> +#define SUNXI_GPIO_H_NR 32
> +#define SUNXI_GPIO_I_NR 32
> +
> +#define SUNXI_GPIO_NEXT(__gpio) \
> + ((__gpio##_START) + (__gpio##_NR) + 0)
> +
> +enum sunxi_gpio_number {
> + SUNXI_GPIO_A_START = 0,
> + SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),
> + SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),
> + SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),
> + SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),
> + SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),
> + SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
> + SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
> + SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
> +};
> +
> +/* SUNXI GPIO number definitions */
> +#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr))
> +#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr))
> +#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr))
> +#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr))
> +#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr))
> +#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr))
> +#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
> +#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
> +#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
> +
> +/* GPIO pin function config */
> +#define SUNXI_GPIO_INPUT 0
> +#define SUNXI_GPIO_OUTPUT 1
> +
> +#define SUNXI_GPA0_ERXD3 2
> +#define SUNXI_GPA0_SPI1_CS0 3
> +#define SUNXI_GPA0_UART2_RTS 4
> +
> +#define SUNXI_GPA1_ERXD2 2
> +#define SUNXI_GPA1_SPI1_CLK 3
> +#define SUNXI_GPA1_UART2_CTS 4
> +
> +#define SUNXI_GPA2_ERXD1 2
> +#define SUNXI_GPA2_SPI1_MOSI 3
> +#define SUNXI_GPA2_UART2_TX 4
> +
> +#define SUNXI_GPA10_UART1_TX 4
> +#define SUNXI_GPA11_UART1_RX 4
> +
> +#define SUN4I_GPB22_UART0_TX 2
> +#define SUN4I_GPB23_UART0_RX 2
> +
> +#define SUN5I_GPG3_UART0_TX 4
> +#define SUN5I_GPG4_UART0_RX 4
> +
> +#define SUNXI_GPC2_NCLE 2
> +#define SUNXI_GPC2_SPI0_CLK 3
> +
> +#define SUNXI_GPC6_NRB0 2
> +#define SUNXI_GPC6_SDC2_CMD 3
> +
> +#define SUNXI_GPC7_NRB1 2
> +#define SUNXI_GPC7_SDC2_CLK 3
> +
> +#define SUNXI_GPC8_NDQ0 2
> +#define SUNXI_GPC8_SDC2_D0 3
> +
> +#define SUNXI_GPC9_NDQ1 2
> +#define SUNXI_GPC9_SDC2_D1 3
> +
> +#define SUNXI_GPC10_NDQ2 2
> +#define SUNXI_GPC10_SDC2_D2 3
> +
> +#define SUNXI_GPC11_NDQ3 2
> +#define SUNXI_GPC11_SDC2_D3 3
> +
> +#define SUNXI_GPF2_SDC0_CLK 2
> +#define SUNXI_GPF2_UART0_TX 4
> +
> +#define SUNXI_GPF4_SDC0_D3 2
> +#define SUNXI_GPF4_UART0_RX 4
> +
> +int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
> +int sunxi_gpio_get_cfgpin(u32 pin);
> +
> +#endif /* _SUNXI_GPIO_H */
> diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
> new file mode 100644
> index 0000000..1e8ae5d
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
> @@ -0,0 +1,32 @@
> +/*
> + * (C) Copyright 2007-2012
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _SYS_PROTO_H_
> +#define _SYS_PROTO_H_
> +
> +void sr32(u32 *, u32, u32, u32);
> +void sdelay(unsigned long);
> +void watchdog_init(void);
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
> new file mode 100644
> index 0000000..cbfec53
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/timer.h
> @@ -0,0 +1,102 @@
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * Configuration settings for the Allwinner A10-evb board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _SUNXI_TIMER_H_
> +#define _SUNXI_TIMER_H_
> +
> +#ifndef __ASSEMBLY__
> +
> +/* General purpose timer */
> +struct sunxi_timer {
> + u32 ctl;
> + u32 inter;
> + u32 val;
> + u8 res[4];
> +};
> +
> +/* Audio video sync*/
> +struct sunxi_avs {
> + u32 ctl; /* 0x80 */
> + u32 cnt0; /* 0x84 */
> + u32 cnt1; /* 0x88 */
> + u32 div; /* 0x8c */
> +};
> +
> +/* 64 bit counter */
> +struct sunxi_64cnt {
> + u32 ctl; /* 0xa0 */
> + u32 lo; /* 0xa4 */
> + u32 hi; /* 0xa8 */
> +};
> +
> +/* Watchdog */
> +struct sunxi_wdog {
> + u32 ctl; /* 0x90 */
> + u32 mode; /* 0x94 */
> +};
> +
> +/* Rtc */
> +struct sunxi_rtc {
> + u32 ctl; /* 0x100 */
> + u32 yymmdd; /* 0x104 */
> + u32 hhmmss; /* 0x108 */
> +};
> +
> +/* Alarm */
> +struct sunxi_alarm {
> + u32 ddhhmmss; /* 0x10c */
> + u32 hhmmss; /* 0x110 */
> + u32 en; /* 0x114 */
> + u32 irqen; /* 0x118 */
> + u32 irqsta; /* 0x11c */
> +};
> +
> +/* Timer general purpose register */
> +struct sunxi_tgp {
> + u32 tgpd;
> +};
> +
> +struct sunxi_timer_reg {
> + u32 tirqen; /* 0x00 */
> + u32 tirqsta; /* 0x04 */
> + u8 res1[8];
> + struct sunxi_timer timer[6]; /* We have 6 timers */
> + u8 res2[16];
> + struct sunxi_avs avs;
> + struct sunxi_wdog wdog;
> + u8 res3[8];
> + struct sunxi_64cnt cnt64;
> + u8 res4[0x58];
> + struct sunxi_rtc rtc;
> + struct sunxi_alarm alarm;
> + struct sunxi_tgp tgp[4];
> + u8 res5[8];
> + u32 cpu_cfg;
> +};
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#endif
> diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
> new file mode 100644
> index 0000000..43acbab
> --- /dev/null
> +++ b/board/sunxi/Makefile
> @@ -0,0 +1,46 @@
> +#
> +# (C) Copyright 2000-2003
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB := $(obj)lib$(BOARD).o
> +
> +COBJS-y := board.o
> +
> +COBJS := $(COBJS-y)
> +SRCS := $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +
> +all: $(LIB)
> +
> +$(LIB): $(obj).depend $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +########################################################################
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> new file mode 100644
> index 0000000..ae05953
> --- /dev/null
> +++ b/board/sunxi/board.c
> @@ -0,0 +1,57 @@
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * Some board init for the Allwinner A10-evb board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/dram.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/mmc.h>
> +#include <axp209.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* add board specific code here */
> +int board_init(void)
> +{
> + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_DISPLAY_BOARDINFO
> +int checkboard(void)
> +{
> + printf("Board: %s\n", CONFIG_SYS_BOARD_NAME);
> +
> + return 0;
> +}
> +#endif
> +
> +int dram_init(void)
> +{
> + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, 1 << 30);
> +
> + return 0;
> +}
> diff --git a/boards.cfg b/boards.cfg
> index 7ae663c..13d1f74 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -288,6 +288,10 @@ whistler arm armv7:arm720t whistler nvidia
> colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20
> u8500_href arm armv7 u8500 st-ericsson u8500
> snowball arm armv7 snowball st-ericsson u8500
> +sun4i arm armv7 sunxi - sunxi sun4i
> +sun4i_sdcon arm armv7 sunxi - sunxi sun4i:UART0_PORT_F
> +sun5i arm armv7 sunxi - sunxi sun5i
> +sun5i_sdcon arm armv7 sunxi - sunxi sun5i:UART0_PORT_F
> kzm9g arm armv7 kzm9g kmc rmobile
> armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile
> zynq arm armv7 zynq xilinx zynq
> diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
> new file mode 100644
> index 0000000..513f618
> --- /dev/null
> +++ b/include/configs/sun4i.h
> @@ -0,0 +1,47 @@
> +/*
> + * (C) Copyright 2012
> + * Henrik Nordstrom <henrik@henriknordstrom.net>
> + *
> + * Configuration settings for the Allwinner A10 (sun4i) CPU
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * Include common sunxi configuration where most the settings are
> + */
> +#include <configs/sunxi-common.h>
> +
> +/*
> + * A10 specific configuration
> + */
> +#define CONFIG_SUN4I /* sun4i SoC generation */
> +
> +#define CONFIG_SYS_PROMPT "sun4i#"
> +#define CONFIG_MACH_TYPE 4104
> +
> +/* Define this to have console redirected to SD port */
> +/* #define CONFIG_UART0_PORT_F */
> +
> +#define CONFIG_CONS_INDEX 1 /* UART0 */
> +
> +#endif /* __CONFIG_H */
> diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
> new file mode 100644
> index 0000000..dc84aba
> --- /dev/null
> +++ b/include/configs/sun5i.h
> @@ -0,0 +1,56 @@
> +/*
> + * (C) Copyright 2012
> + * Henrik Nordstrom <henrik@henriknordstrom.net>
> + *
> + * Configuration settings for the Allwinner A13 (sun5i) CPU
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * Include common sunxi configuration where most the settings are
> + */
> +#include <configs/sunxi-common.h>
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_SUN5I /* sun5i SoC generation */
> +
> +#define CONFIG_SYS_PROMPT "sun5i#"
> +#define CONFIG_MACH_TYPE 4138
> +
> +/* Define this to have serial channel 1 (UART0) redirected to SD port */
> +/* #define CONFIG_UART0_PORT_F */
> +
> +#ifndef CONFIG_CONS_INDEX
> +#ifdef CONFIG_UART0_PORT_F
> +#define CONFIG_CONS_INDEX 1 /* UART0 on PORT_F (sdcard) */
> +#else
> +#define CONFIG_CONS_INDEX 2 /* UART1 */
> +#endif
> +#endif
> +
> +/* Leave ICACHE off while debugging with OpenOCD */
> +#define CONFIG_SYS_ICACHE_OFF
> +
> +#endif /* __CONFIG_H */
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> new file mode 100644
> index 0000000..33309f3
> --- /dev/null
> +++ b/include/configs/sunxi-common.h
> @@ -0,0 +1,189 @@
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
> + * Configuration settings for the Allwinner A10-evb board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _SUNXI_CONFIG_H
> +#define _SUNXI_CONFIG_H
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ALLWINNER /* It's a Allwinner chip */
> +#define CONFIG_SUNXI /* which is sunxi family */

Space, not tab here.

> +#include <asm/arch/cpu.h> /* get chip and board defs */
> +
> +#define CONFIG_SYS_TEXT_BASE 0x4A000000
> +
> +/*
> + * Display CPU and Board information
> + */
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +/* Clock Defines */

Why not remove this comment when there is no defines under it ?

> +
> +/* Serial & console */
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +/* ns16550 reg in the low bits of cpu reg */
> +#define CONFIG_SYS_NS16550_REG_SIZE (-4)
> +#define CONFIG_SYS_NS16550_CLK (24000000)
> +#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
> +#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
> +#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
> +#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
> +
> +/* DRAM Base */
> +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> +#define CONFIG_SYS_INIT_RAM_ADDR 0x0
> +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32K */
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* A10-EVB has 1 banks of DRAM, we use only one in U-Boot */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
> +
> +#define CONFIG_CMD_MEMORY
> +#define CONFIG_CMD_SETEXPR
> +
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_CMDLINE_EDITING
> +
> +/*
> + * Size of malloc() pool
> + * 1MB = 0x100000, 0x100000 = 1024 * 1024
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
> +
> +/* Flat Device Tree (FDT/DT) support */
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> +#define CONFIG_CMD_ECHO
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +
> +/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +/* memtest works on */
> +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (256 << 20))
> +#define CONFIG_SYS_LOAD_ADDR 0x50000000 /* default load address */
> +
> +#define CONFIG_SYS_HZ 1000
> +
> +/* valid baudrates */
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +
> +/*-----------------------------------------------------------------------

I don't think we need "----" chars above.

> + * Stack sizes
> + *
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (256 << 10) /* 256 KB */
> +
> +/*-----------------------------------------------------------------------

I don't think we need "----" chars above.

> + * FLASH and environment organization
> + */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KB */
> +#define CONFIG_IDENT_STRING " Allwinner Technology "

Why do you need trailing space ?

> +
> +#define CONFIG_ENV_IS_NOWHERE /* No storage defined yet */
> +
> +#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512)KB */
> +#define CONFIG_ENV_SIZE (128 << 10) /* 128KB */
> +
> +#define CONFIG_BOOTCOMMAND \
> + "if run loadbootenv; then " \
> + "echo Loaded environment from ${bootenv};" \
> + "env import -t ${scriptaddr} ${filesize};" \
> + "fi;" \
> + "if test -n ${uenvcmd}; then " \
> + "echo Running uenvcmd ...;" \
> + "run uenvcmd;" \
> + "fi;" \
> + "if run loadbootscr; then "\
> + "echo Jumping to ${bootscr};" \
> + "source ${scriptaddr};" \
> + "fi;" \
> + "run setargs boot_mmc;" \
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "console=ttyS0,115200\0" \
> + "root=/dev/mmcblk0p2 rootwait\0" \
> + "panicarg=panic=10\0" \
> + "extraargs=\0" \
> + "loglevel=8\0" \
> + "scriptaddr=0x44000000\0" \
> + "setargs=setenv bootargs console=${console} root=${root}" \
> + " loglevel=${loglevel} ${panicarg} ${extraargs}\0" \
> + "kernel=uImage\0" \
> + "bootenv=uEnv.txt\0" \
> + "bootscr=boot.scr\0" \
> + "loadbootscr=fatload mmc 0 $scriptaddr ${bootscr} ||" \
> + " ext2load mmc 0 $scriptaddr ${bootscr} ||" \
> + " ext2load mmc 0 $scriptaddr boot/${bootscr}\0" \
> + "loadbootenv=fatload mmc 0 $scriptaddr ${bootenv} ||" \
> + " ext2load mmc 0 $scriptaddr ${bootenv} ||" \
> + " ext2load mmc 0 $scriptaddr boot/${bootenv}\0" \
> + "boot_mmc=fatload mmc 0 0x43000000 script.bin &&" \
> + " fatload mmc 0 0x48000000 ${kernel} &&" \
> + " bootm 0x48000000\0"
> +
> +#define CONFIG_BOOTDELAY 3
> +#define CONFIG_SYS_BOOT_GET_CMDLINE
> +#define CONFIG_AUTO_COMPLETE
> +
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_CMD_FAT /* with this we can access fat bootfs */
> +#define CONFIG_FAT_WRITE /* enable write access */
> +#define CONFIG_CMD_EXT2 /* with this we can access ext2 bootfs */
> +#define CONFIG_CMD_EXT4 /* with this we can access ext4 bootfs */
> +#define CONFIG_CMD_ZFS /* with this we can access ZFS bootfs */
> +
> +#undef CONFIG_CMD_FPGA
> +#undef CONFIG_CMD_NET
> +#undef CONFIG_CMD_NFS
> +
> +#endif /* __CONFIG_H */

Luka