* [U-Boot] [PATCH V3 1/7] Tegra30: Add arch-tegra30 include files
2012-12-11 23:34 [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Tom Warren
@ 2012-12-11 23:34 ` Tom Warren
2012-12-12 0:36 ` Stephen Warren
2012-12-12 14:55 ` Simon Glass
2012-12-11 23:34 ` [U-Boot] [PATCH V3 2/7] Tegra30: Add AVP (arm720t) files Tom Warren
` (7 subsequent siblings)
8 siblings, 2 replies; 31+ messages in thread
From: Tom Warren @ 2012-12-11 23:34 UTC (permalink / raw)
To: u-boot
Common Tegra files are in arch-tegra, shared between T20 and T30.
Tegra30-specific headers are in arch-tegra30. Note that some of
these will be filled in as more T30 support is added (drivers,
WB/LP0 support, etc.). A couple of Tegra20 files were changed
to support common headers in arch-tegra, also.
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
V2:
* Created common header files in arch-tegra.
* Reworked pmux func name enums, RSVDx values to end of list.
* Added spl.h for T30, removed emc.h.
V3:
* Use 408MHz for PLLP.
arch/arm/include/asm/arch-tegra/clk_rst.h | 148 +++++-
arch/arm/include/asm/arch-tegra/clock.h | 8 +-
arch/arm/include/asm/arch-tegra/funcmux.h | 39 ++
arch/arm/include/asm/arch-tegra/gp_padctrl.h | 39 ++
arch/arm/include/asm/arch-tegra/tegra.h | 12 +-
arch/arm/include/asm/arch-tegra20/funcmux.h | 26 +-
arch/arm/include/asm/arch-tegra20/gp_padctrl.h | 17 +-
arch/arm/include/asm/arch-tegra30/clock-tables.h | 378 ++++++++++++++
arch/arm/include/asm/arch-tegra30/clock.h | 24 +
arch/arm/include/asm/arch-tegra30/flow.h | 35 ++
arch/arm/include/asm/arch-tegra30/funcmux.h | 31 ++
arch/arm/include/asm/arch-tegra30/gp_padctrl.h | 59 +++
arch/arm/include/asm/arch-tegra30/gpio.h | 304 +++++++++++
arch/arm/include/asm/arch-tegra30/hardware.h | 22 +
arch/arm/include/asm/arch-tegra30/pinmux.h | 604 ++++++++++++++++++++++
arch/arm/include/asm/arch-tegra30/pmu.h | 23 +
arch/arm/include/asm/arch-tegra30/spl.h | 28 +
arch/arm/include/asm/arch-tegra30/tegra.h | 26 +
18 files changed, 1775 insertions(+), 48 deletions(-)
create mode 100644 arch/arm/include/asm/arch-tegra/funcmux.h
create mode 100644 arch/arm/include/asm/arch-tegra/gp_padctrl.h
create mode 100644 arch/arm/include/asm/arch-tegra30/clock-tables.h
create mode 100644 arch/arm/include/asm/arch-tegra30/clock.h
create mode 100644 arch/arm/include/asm/arch-tegra30/flow.h
create mode 100644 arch/arm/include/asm/arch-tegra30/funcmux.h
create mode 100644 arch/arm/include/asm/arch-tegra30/gp_padctrl.h
create mode 100644 arch/arm/include/asm/arch-tegra30/gpio.h
create mode 100644 arch/arm/include/asm/arch-tegra30/hardware.h
create mode 100644 arch/arm/include/asm/arch-tegra30/pinmux.h
create mode 100644 arch/arm/include/asm/arch-tegra30/pmu.h
create mode 100644 arch/arm/include/asm/arch-tegra30/spl.h
create mode 100644 arch/arm/include/asm/arch-tegra30/tegra.h
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 7b548c2..6a6e507 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -21,8 +21,8 @@
* MA 02111-1307 USA
*/
-#ifndef _CLK_RST_H_
-#define _CLK_RST_H_
+#ifndef _TEGRA_CLK_RST_H_
+#define _TEGRA_CLK_RST_H_
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll {
@@ -37,6 +37,12 @@ struct clk_pll_simple {
uint pll_misc; /* other misc things */
};
+/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
+struct clk_set_clr {
+ uint set;
+ uint clr;
+};
+
/*
* Most PLLs use the clk_pll structure, but some have a simpler two-member
* structure for which we use clk_pll_simple. The reason for this non-
@@ -45,8 +51,10 @@ struct clk_pll_simple {
enum {
TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */
TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */
- TEGRA_CLK_REGS = 3, /* Number of clock enable registers */
- TEGRA_CLK_SOURCES = 64, /* Number of peripheral clock sources */
+ TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */
+ TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */
+ TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
+ TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W*/
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -82,14 +90,53 @@ struct clk_rst_ctlr {
uint crc_reserved11; /* _reserved_11, 0xFC */
uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
- uint crc_reserved20[80]; /* 0x200-33C */
- uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */
- uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
+
+ uint crc_reserved20[64]; /* _reserved_20, 0x200-2fc */
+
+ /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
+ struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
+
+ uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */
+
+ /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
+ struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
+
+ uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */
+
+ uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
+ uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
+
+ /* Additional (T30) registers */
+ uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
+ uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
+
+ uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */
+
+ uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
+ uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
+ uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
+ uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */
+ uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
+ uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
+ uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
+ uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */
+ uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
+ uint crc_reserved33[11]; /* _reserved_33, 0x384-3ac */
+ uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
+ /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
+ struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
+ /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
+ struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
+ uint crc_reserved40[12]; /* _reserved_40, 0x450-47C */
+ uint crc_pll_cfg0; /* _PLL_CFG0_0, 0x480 */
+ uint crc_pll_cfg1; /* _PLL_CFG1_0, 0x484 */
+ uint crc_pll_cfg2; /* _PLL_CFG2_0, 0x488 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
+#define CPU3_CLK_STP_SHIFT 11
+#define CPU2_CLK_STP_SHIFT 10
#define CPU1_CLK_STP_SHIFT 9
-
#define CPU0_CLK_STP_SHIFT 8
#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
@@ -120,6 +167,12 @@ struct clk_rst_ctlr {
#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
+#define PLL_DCCON_SHIFT 20
+#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT)
+
+#define PLL_LOCK_ENABLE_SHIFT 18
+#define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT)
+
#define PLL_CPCON_SHIFT 8
#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
@@ -129,6 +182,22 @@ struct clk_rst_ctlr {
#define PLLU_VCO_FREQ_SHIFT 20
#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)
+#define PLLP_OUT1_OVR (1 << 2)
+#define PLLP_OUT2_OVR (1 << 18)
+#define PLLP_OUT3_OVR (1 << 2)
+#define PLLP_OUT4_OVR (1 << 18)
+#define PLLP_OUT1_RATIO 8
+#define PLLP_OUT2_RATIO 24
+#define PLLP_OUT3_RATIO 8
+#define PLLP_OUT4_RATIO 24
+
+enum {
+ IN_408_OUT_204_DIVISOR = 2,
+ IN_408_OUT_102_DIVISOR = 6,
+ IN_408_OUT_48_DIVISOR = 15,
+ IN_408_OUT_9_6_DIVISOR = 83,
+};
+
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_FREQ_SHIFT 30
#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
@@ -151,4 +220,65 @@ struct clk_rst_ctlr {
#define OUT_CLK_SOURCE4_SHIFT 28
#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT)
-#endif /* CLK_RST_H */
+/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
+#define SCLK_SYS_STATE_SHIFT 28U
+#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT)
+enum {
+ SCLK_SYS_STATE_STDBY,
+ SCLK_SYS_STATE_IDLE,
+ SCLK_SYS_STATE_RUN,
+ SCLK_SYS_STATE_IRQ = 4U,
+ SCLK_SYS_STATE_FIQ = 8U,
+};
+#define SCLK_COP_FIQ_MASK (1 << 27)
+#define SCLK_CPU_FIQ_MASK (1 << 26)
+#define SCLK_COP_IRQ_MASK (1 << 25)
+#define SCLK_CPU_IRQ_MASK (1 << 24)
+
+#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12
+#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \
+ (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8
+#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \
+ (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4
+#define SCLK_SWAKEUP_RUN_SOURCE_MASK \
+ (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0
+
+#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \
+ (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+enum {
+ SCLK_SOURCE_CLKM,
+ SCLK_SOURCE_PLLC_OUT1,
+ SCLK_SOURCE_PLLP_OUT4,
+ SCLK_SOURCE_PLLP_OUT3,
+ SCLK_SOURCE_PLLP_OUT2,
+ SCLK_SOURCE_CLKD,
+ SCLK_SOURCE_CLKS,
+ SCLK_SOURCE_PLLM_OUT1,
+};
+#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
+#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
+#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
+#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
+
+/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
+#define SUPER_SCLK_ENB_SHIFT 31U
+#define SUPER_SCLK_ENB_MASK (1U << 31)
+#define SUPER_SCLK_DIVIDEND_SHIFT 8
+#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT)
+#define SUPER_SCLK_DIVISOR_SHIFT 0
+#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
+
+/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */
+#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
+#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
+#define CLK_SYS_RATE_AHB_RATE_SHIFT 4
+#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
+#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
+#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
+#define CLK_SYS_RATE_APB_RATE_SHIFT 0
+#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
+
+#endif /* _TEGRA_CLK_RST_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index eac1dc2..01f86ab 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -21,8 +21,8 @@
/* Tegra clock control functions */
-#ifndef _CLOCK_H
-#define _CLOCK_H
+#ifndef _TEGRA_CLOCK_H_
+#define _TEGRA_CLOCK_H_
/* Set of oscillator frequencies supported in the internal API. */
enum clock_osc_freq {
@@ -136,7 +136,7 @@ enum crc_reset_id {
/**
* Put parts of the CPU complex into or out of reset.\
*
- * @param cpu cpu number (0 or 1 on Tegra2)
+ * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
* @param which which parts of the complex to affect (OR of crc_reset_id)
* @param reset 1 to assert reset, 0 to de-assert
*/
@@ -262,4 +262,4 @@ void clock_init(void);
/* Initialize the PLLs */
void clock_early_init(void);
-#endif /* _CLOCK_H_ */
+#endif /* _TEGRA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/funcmux.h b/arch/arm/include/asm/arch-tegra/funcmux.h
new file mode 100644
index 0000000..f101e5e
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/funcmux.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra high-level function multiplexing */
+
+#ifndef _TEGRA_FUNCMUX_H_
+#define _TEGRA_FUNCMUX_H_
+
+/**
+ * Select a config for a particular peripheral.
+ *
+ * Each peripheral can operate through a number of configurations,
+ * which are sets of pins that it uses to bring out its signals.
+ * The basic config is 0, and higher numbers indicate different
+ * pinmux settings to bring the peripheral out on other pins,
+ *
+ * This function also disables tristate for the function's pins,
+ * so that they operate in normal mode.
+ *
+ * @param id Peripheral id
+ * @param config Configuration to use (FUNCMUX_...), 0 for default
+ * @return 0 if ok, -1 on error (e.g. incorrect id or config)
+ */
+int funcmux_select(enum periph_id id, int config);
+
+#endif /* _TEGRA_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
new file mode 100644
index 0000000..e6085a0
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_GP_PADCTRL_H_
+#define _TEGRA_GP_PADCTRL_H_
+
+#define GP_HIDREV 0x804
+
+/* bit fields definitions for APB_MISC_GP_HIDREV register */
+#define HIDREV_CHIPID_SHIFT 8
+#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
+#define HIDREV_MAJORPREV_SHIFT 4
+#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
+
+/* CHIPID field returned from APB_MISC_GP_HIDREV register */
+#define CHIPID_TEGRA20 0x20
+#define CHIPID_TEGRA30 0x30
+
+#endif /* _TEGRA_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 6d2e62f..953936c 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -72,14 +72,22 @@ enum {
SKU_ID_T25 = 0x18,
SKU_ID_AP25E = 0x1b,
SKU_ID_T25E = 0x1c,
+ SKU_ID_T30 = 0x81, /* Cardhu value */
};
-/* These are the SOC categories that affect clocking */
+/*
+ * These are used to distinguish SOC types for setting up clocks. Mostly
+ * we can tell the clocking required by looking at the SOC sku_id, but
+ * for T30 it is a user option as to whether to run PLLP in fast or slow
+ * mode, so we have two options there.
+ */
enum {
TEGRA_SOC_T20,
TEGRA_SOC_T25,
+ TEGRA_SOC_T30,
+ TEGRA_SOC2_SLOW, /* T2x needs to run@slow clock initially */
- TEGRA_SOC_COUNT,
+ TEGRA_SOC_CNT,
TEGRA_SOC_UNKNOWN = -1,
};
diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h
index c986b93..1bac25e 100644
--- a/arch/arm/include/asm/arch-tegra20/funcmux.h
+++ b/arch/arm/include/asm/arch-tegra20/funcmux.h
@@ -21,8 +21,10 @@
/* Tegra20 high-level function multiplexing */
-#ifndef __FUNCMUX_H
-#define __FUNCMUX_H
+#ifndef _TEGRA20_FUNCMUX_H_
+#define _TEGRA20_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
/* Configs supported by the func mux */
enum {
@@ -62,22 +64,4 @@ enum {
FUNCMUX_NDFLASH_ATC = 0,
FUNCMUX_NDFLASH_KBC_8_BIT,
};
-
-/**
- * Select a config for a particular peripheral.
- *
- * Each peripheral can operate through a number of configurations,
- * which are sets of pins that it uses to bring out its signals.
- * The basic config is 0, and higher numbers indicate different
- * pinmux settings to bring the peripheral out on other pins,
- *
- * This function also disables tristate for the function's pins,
- * so that they operate in normal mode.
- *
- * @param id Peripheral id
- * @param config Configuration to use (FUNCMUX_...), 0 for default
- * @return 0 if ok, -1 on error (e.g. incorrect id or config)
- */
-int funcmux_select(enum periph_id id, int config);
-
-#endif
+#endif /* _TEGRA20_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
index 865af5b..eaaf903 100644
--- a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
@@ -21,8 +21,10 @@
* MA 02111-1307 USA
*/
-#ifndef _GP_PADCTRL_H_
-#define _GP_PADCTRL_H_
+#ifndef _TEGRA20_GP_PADCTRL_H_
+#define _TEGRA20_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
/* APB_MISC_GP and padctrl registers */
struct apb_misc_gp_ctlr {
@@ -61,13 +63,4 @@ struct apb_misc_gp_ctlr {
u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
};
-/* bit fields definitions for APB_MISC_GP_HIDREV register */
-#define HIDREV_CHIPID_SHIFT 8
-#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
-#define HIDREV_MAJORPREV_SHIFT 4
-#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
-
-/* CHIPID field returned from APB_MISC_GP_HIDREV register */
-#define CHIPID_TEGRA20 0x20
-
-#endif
+#endif /* _TEGRA20_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h
new file mode 100644
index 0000000..b55e09d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 clock PLL tables */
+
+#ifndef _TEGRA30_CLOCK_TABLES_H_
+#define _TEGRA30_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+ CLOCK_ID_FIRST,
+ CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+ CLOCK_ID_MEMORY,
+ CLOCK_ID_PERIPH,
+ CLOCK_ID_AUDIO,
+ CLOCK_ID_USB,
+ CLOCK_ID_DISPLAY,
+
+ /* now the simple ones */
+ CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_EPCI,
+ CLOCK_ID_SFROM32KHZ,
+
+ /* These are the base clocks (inputs to the Tegra SOC) */
+ CLOCK_ID_32KHZ,
+ CLOCK_ID_OSC,
+
+ CLOCK_ID_COUNT, /* number of PLLs */
+ CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
+ CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+ PERIPH_ID_FIRST,
+
+ /* Low word: 31:0 */
+ PERIPH_ID_CPU = PERIPH_ID_FIRST,
+ PERIPH_ID_COP,
+ PERIPH_ID_TRIGSYS,
+ PERIPH_ID_RESERVED3,
+ PERIPH_ID_RESERVED4,
+ PERIPH_ID_TMR,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+
+ /* 8 */
+ PERIPH_ID_GPIO,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_NDFLASH,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC4,
+
+ /* 16 */
+ PERIPH_ID_RESERVED16,
+ PERIPH_ID_PWM,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_EPP,
+ PERIPH_ID_VI,
+ PERIPH_ID_2D,
+ PERIPH_ID_USBD,
+ PERIPH_ID_ISP,
+
+ /* 24 */
+ PERIPH_ID_3D,
+ PERIPH_ID_RESERVED24,
+ PERIPH_ID_DISP2,
+ PERIPH_ID_DISP1,
+ PERIPH_ID_HOST1X,
+ PERIPH_ID_VCP,
+ PERIPH_ID_I2S0,
+ PERIPH_ID_CACHE2,
+
+ /* Middle word: 63:32 */
+ PERIPH_ID_MEM,
+ PERIPH_ID_AHBDMA,
+ PERIPH_ID_APBDMA,
+ PERIPH_ID_RESERVED35,
+ PERIPH_ID_KBC,
+ PERIPH_ID_STAT_MON,
+ PERIPH_ID_PMC,
+ PERIPH_ID_FUSE,
+
+ /* 40 */
+ PERIPH_ID_KFUSE,
+ PERIPH_ID_SBC1,
+ PERIPH_ID_SNOR,
+ PERIPH_ID_RESERVED43,
+ PERIPH_ID_SBC2,
+ PERIPH_ID_RESERVED45,
+ PERIPH_ID_SBC3,
+ PERIPH_ID_DVC_I2C,
+
+ /* 48 */
+ PERIPH_ID_DSI,
+ PERIPH_ID_TVO,
+ PERIPH_ID_MIPI,
+ PERIPH_ID_HDMI,
+ PERIPH_ID_CSI,
+ PERIPH_ID_TVDAC,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_UART3,
+
+ /* 56 */
+ PERIPH_ID_RESERVED56,
+ PERIPH_ID_EMC,
+ PERIPH_ID_USB2,
+ PERIPH_ID_USB3,
+ PERIPH_ID_MPE,
+ PERIPH_ID_VDE,
+ PERIPH_ID_BSEA,
+ PERIPH_ID_BSEV,
+
+ /* Upper word 95:64 */
+ PERIPH_ID_SPEEDO,
+ PERIPH_ID_UART4,
+ PERIPH_ID_UART5,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_SBC4,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_PCIE,
+ PERIPH_ID_OWR,
+
+ /* 72 */
+ PERIPH_ID_AFI,
+ PERIPH_ID_CORESIGHT,
+ PERIPH_ID_PCIEXCLK,
+ PERIPH_ID_AVPUCQ,
+ PERIPH_ID_RESERVED76,
+ PERIPH_ID_RESERVED77,
+ PERIPH_ID_RESERVED78,
+ PERIPH_ID_DTV,
+
+ /* 80 */
+ PERIPH_ID_NANDSPEED,
+ PERIPH_ID_I2CSLOW,
+ PERIPH_ID_DSIB,
+ PERIPH_ID_RESERVED83,
+ PERIPH_ID_IRAMA,
+ PERIPH_ID_IRAMB,
+ PERIPH_ID_IRAMC,
+ PERIPH_ID_IRAMD,
+
+ /* 88 */
+ PERIPH_ID_CRAM2,
+ PERIPH_ID_RESERVED89,
+ PERIPH_ID_MDOUBLER,
+ PERIPH_ID_RESERVED91,
+ PERIPH_ID_SUSOUT,
+ PERIPH_ID_RESERVED93,
+ PERIPH_ID_RESERVED94,
+ PERIPH_ID_RESERVED95,
+
+ PERIPH_ID_VW_FIRST,
+ /* V word: 31:0 */
+ PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+ PERIPH_ID_CPULP,
+ PERIPH_ID_3D2,
+ PERIPH_ID_MSELECT,
+ PERIPH_ID_TSENSOR,
+ PERIPH_ID_I2S3,
+ PERIPH_ID_I2S4,
+ PERIPH_ID_I2C4,
+
+ /* 08 */
+ PERIPH_ID_SBC5,
+ PERIPH_ID_SBC6,
+ PERIPH_ID_AUDIO,
+ PERIPH_ID_APBIF,
+ PERIPH_ID_DAM0,
+ PERIPH_ID_DAM1,
+ PERIPH_ID_DAM2,
+ PERIPH_ID_HDA2CODEC2X,
+
+ /* 16 */
+ PERIPH_ID_ATOMICS,
+ PERIPH_ID_EX_RESERVED17,
+ PERIPH_ID_EX_RESERVED18,
+ PERIPH_ID_EX_RESERVED19,
+ PERIPH_ID_EX_RESERVED20,
+ PERIPH_ID_EX_RESERVED21,
+ PERIPH_ID_EX_RESERVED22,
+ PERIPH_ID_ACTMON,
+
+ /* 24 */
+ PERIPH_ID_EX_RESERVED24,
+ PERIPH_ID_EX_RESERVED25,
+ PERIPH_ID_EX_RESERVED26,
+ PERIPH_ID_EX_RESERVED27,
+ PERIPH_ID_SATA,
+ PERIPH_ID_HDA,
+ PERIPH_ID_EX_RESERVED30,
+ PERIPH_ID_EX_RESERVED31,
+
+ /* W word: 31:0 */
+ PERIPH_ID_HDA2HDMICODEC,
+ PERIPH_ID_SATACOLD,
+ PERIPH_ID_RESERVED0_PCIERX0,
+ PERIPH_ID_RESERVED1_PCIERX1,
+ PERIPH_ID_RESERVED2_PCIERX2,
+ PERIPH_ID_RESERVED3_PCIERX3,
+ PERIPH_ID_RESERVED4_PCIERX4,
+ PERIPH_ID_RESERVED5_PCIERX5,
+
+ /* 40 */
+ PERIPH_ID_CEC,
+ PERIPH_ID_RESERVED6_PCIE2,
+ PERIPH_ID_RESERVED7_EMC,
+ PERIPH_ID_RESERVED8_HDMI,
+ PERIPH_ID_RESERVED9_SATA,
+ PERIPH_ID_RESERVED10_MIPI,
+ PERIPH_ID_EX_RESERVED46,
+ PERIPH_ID_EX_RESERVED47,
+
+ PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+ PLL_OUT1,
+ PLL_OUT2,
+ PLL_OUT3,
+ PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+ /* 0x00 */
+ PERIPHC_I2S1,
+ PERIPHC_I2S2,
+ PERIPHC_SPDIF_OUT,
+ PERIPHC_SPDIF_IN,
+ PERIPHC_PWM,
+ PERIPHC_05h,
+ PERIPHC_SBC2,
+ PERIPHC_SBC3,
+
+ /* 0x08 */
+ PERIPHC_08h,
+ PERIPHC_I2C1,
+ PERIPHC_DVC_I2C,
+ PERIPHC_0bh,
+ PERIPHC_0ch,
+ PERIPHC_SBC1,
+ PERIPHC_DISP1,
+ PERIPHC_DISP2,
+
+ /* 0x10 */
+ PERIPHC_CVE,
+ PERIPHC_11h,
+ PERIPHC_VI,
+ PERIPHC_13h,
+ PERIPHC_SDMMC1,
+ PERIPHC_SDMMC2,
+ PERIPHC_G3D,
+ PERIPHC_G2D,
+
+ /* 0x18 */
+ PERIPHC_NDFLASH,
+ PERIPHC_SDMMC4,
+ PERIPHC_VFIR,
+ PERIPHC_EPP,
+ PERIPHC_MPE,
+ PERIPHC_MIPI,
+ PERIPHC_UART1,
+ PERIPHC_UART2,
+
+ /* 0x20 */
+ PERIPHC_HOST1X,
+ PERIPHC_21h,
+ PERIPHC_TVO,
+ PERIPHC_HDMI,
+ PERIPHC_24h,
+ PERIPHC_TVDAC,
+ PERIPHC_I2C2,
+ PERIPHC_EMC,
+
+ /* 0x28 */
+ PERIPHC_UART3,
+ PERIPHC_29h,
+ PERIPHC_VI_SENSOR,
+ PERIPHC_2bh,
+ PERIPHC_2ch,
+ PERIPHC_SBC4,
+ PERIPHC_I2C3,
+ PERIPHC_SDMMC3,
+
+ /* 0x30 */
+ PERIPHC_UART4,
+ PERIPHC_UART5,
+ PERIPHC_VDE,
+ PERIPHC_OWR,
+ PERIPHC_NOR,
+ PERIPHC_CSITE,
+ PERIPHC_I2S0,
+ PERIPHC_37h,
+
+ PERIPHC_VW_FIRST,
+ /* 0x38 */
+ PERIPHC_G3D2 = PERIPHC_VW_FIRST,
+ PERIPHC_MSELECT,
+ PERIPHC_TSENSOR,
+ PERIPHC_I2S3,
+ PERIPHC_I2S4,
+ PERIPHC_I2C4,
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+
+ /* 0x40 */
+ PERIPHC_AUDIO,
+ PERIPHC_41h,
+ PERIPHC_DAM0,
+ PERIPHC_DAM1,
+ PERIPHC_DAM2,
+ PERIPHC_HDA2CODEC2X,
+ PERIPHC_ACTMON,
+ PERIPHC_EXTPERIPH1,
+
+ /* 0x48 */
+ PERIPHC_EXTPERIPH2,
+ PERIPHC_EXTPERIPH3,
+ PERIPHC_NANDSPEED,
+ PERIPHC_I2CSLOW,
+ PERIPHC_SYS,
+ PERIPHC_SPEEDO,
+ PERIPHC_4eh,
+ PERIPHC_4fh,
+
+ /* 0x50 */
+ PERIPHC_SATAOOB,
+ PERIPHC_SATA,
+ PERIPHC_HDA,
+
+ PERIPHC_COUNT,
+
+ PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+ (id < PERIPH_ID_VW_FIRST) ? \
+ ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+ (id) < PERIPH_ID_COUNT)
+
+#endif /* _TEGRA30_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/include/asm/arch-tegra30/clock.h
new file mode 100644
index 0000000..61fc4c8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/clock.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 clock control functions */
+
+#ifndef _TEGRA30_CLOCK_H_
+#define _TEGRA30_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+#endif /* _TEGRA30_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/flow.h b/arch/arm/include/asm/arch-tegra30/flow.h
new file mode 100644
index 0000000..f5966a8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/flow.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_FLOW_H_
+#define _TEGRA30_FLOW_H_
+
+struct flow_ctlr {
+ u32 halt_cpu_events;
+ u32 halt_cop_events;
+ u32 cpu_csr;
+ u32 cop_csr;
+ u32 xrq_events;
+ u32 halt_cpu1_events;
+ u32 cpu1_csr;
+ u32 halt_cpu2_events;
+ u32 cpu2_csr;
+ u32 halt_cpu3_events;
+ u32 cpu3_csr;
+ u32 cluster_control;
+};
+
+#endif /* _TEGRA30_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h
new file mode 100644
index 0000000..24b2bca
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/funcmux.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 high-level function multiplexing */
+
+#ifndef _TEGRA30_FUNCMUX_H_
+#define _TEGRA30_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+ FUNCMUX_DEFAULT = 0, /* default config */
+
+ /* UART configs */
+ FUNCMUX_UART1_ULPI = 0,
+};
+#endif /* _TEGRA30_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
new file mode 100644
index 0000000..9b383d0
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_GP_PADCTRL_H_
+#define _TEGRA30_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+ u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
+ u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
+ u32 reserved0[22]; /* 0x08 - 0x5C: */
+ u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
+ u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+ u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+ u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+ u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+ u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+ u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+ u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+ u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+ u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+ u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+ u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
+ u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+ u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+ u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+ u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+ u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+ u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
+ u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
+ u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
+ u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+ u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+ u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+ u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+ u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+ u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+ u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
+ u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
+ u32 reserved1[7]; /* 0xD0-0xE8: */
+ u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+};
+
+#endif /* _TEGRA30_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h
new file mode 100644
index 0000000..f1c89f5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/gpio.h
@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_GPIO_H_
+#define _TEGRA30_GPIO_H_
+
+/*
+ * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
+#define TEGRA_GPIO_BANKS 8 /* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+ uint gpio_config[TEGRA_GPIO_PORTS];
+ uint gpio_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_out[TEGRA_GPIO_PORTS];
+ uint gpio_in[TEGRA_GPIO_PORTS];
+ uint gpio_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_int_clear[TEGRA_GPIO_PORTS];
+ uint gpio_masked_config[TEGRA_GPIO_PORTS];
+ uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_masked_out[TEGRA_GPIO_PORTS];
+ uint gpio_masked_in[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+ struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+ GPIO_PA0 = 0, /* pin 0 */
+ GPIO_PA1,
+ GPIO_PA2,
+ GPIO_PA3,
+ GPIO_PA4,
+ GPIO_PA5,
+ GPIO_PA6,
+ GPIO_PA7,
+ GPIO_PB0, /* pin 8 */
+ GPIO_PB1,
+ GPIO_PB2,
+ GPIO_PB3,
+ GPIO_PB4,
+ GPIO_PB5,
+ GPIO_PB6,
+ GPIO_PB7,
+ GPIO_PC0, /* pin 16 */
+ GPIO_PC1,
+ GPIO_PC2,
+ GPIO_PC3,
+ GPIO_PC4,
+ GPIO_PC5,
+ GPIO_PC6,
+ GPIO_PC7,
+ GPIO_PD0, /* pin 24 */
+ GPIO_PD1,
+ GPIO_PD2,
+ GPIO_PD3,
+ GPIO_PD4,
+ GPIO_PD5,
+ GPIO_PD6,
+ GPIO_PD7,
+ GPIO_PE0, /* pin 32 */
+ GPIO_PE1,
+ GPIO_PE2,
+ GPIO_PE3,
+ GPIO_PE4,
+ GPIO_PE5,
+ GPIO_PE6,
+ GPIO_PE7,
+ GPIO_PF0, /* pin 40 */
+ GPIO_PF1,
+ GPIO_PF2,
+ GPIO_PF3,
+ GPIO_PF4,
+ GPIO_PF5,
+ GPIO_PF6,
+ GPIO_PF7,
+ GPIO_PG0, /* pin 48 */
+ GPIO_PG1,
+ GPIO_PG2,
+ GPIO_PG3,
+ GPIO_PG4,
+ GPIO_PG5,
+ GPIO_PG6,
+ GPIO_PG7,
+ GPIO_PH0, /* pin 56 */
+ GPIO_PH1,
+ GPIO_PH2,
+ GPIO_PH3,
+ GPIO_PH4,
+ GPIO_PH5,
+ GPIO_PH6,
+ GPIO_PH7,
+ GPIO_PI0, /* pin 64 */
+ GPIO_PI1,
+ GPIO_PI2,
+ GPIO_PI3,
+ GPIO_PI4,
+ GPIO_PI5,
+ GPIO_PI6,
+ GPIO_PI7,
+ GPIO_PJ0, /* pin 72 */
+ GPIO_PJ1,
+ GPIO_PJ2,
+ GPIO_PJ3,
+ GPIO_PJ4,
+ GPIO_PJ5,
+ GPIO_PJ6,
+ GPIO_PJ7,
+ GPIO_PK0, /* pin 80 */
+ GPIO_PK1,
+ GPIO_PK2,
+ GPIO_PK3,
+ GPIO_PK4,
+ GPIO_PK5,
+ GPIO_PK6,
+ GPIO_PK7,
+ GPIO_PL0, /* pin 88 */
+ GPIO_PL1,
+ GPIO_PL2,
+ GPIO_PL3,
+ GPIO_PL4,
+ GPIO_PL5,
+ GPIO_PL6,
+ GPIO_PL7,
+ GPIO_PM0, /* pin 96 */
+ GPIO_PM1,
+ GPIO_PM2,
+ GPIO_PM3,
+ GPIO_PM4,
+ GPIO_PM5,
+ GPIO_PM6,
+ GPIO_PM7,
+ GPIO_PN0, /* pin 104 */
+ GPIO_PN1,
+ GPIO_PN2,
+ GPIO_PN3,
+ GPIO_PN4,
+ GPIO_PN5,
+ GPIO_PN6,
+ GPIO_PN7,
+ GPIO_PO0, /* pin 112 */
+ GPIO_PO1,
+ GPIO_PO2,
+ GPIO_PO3,
+ GPIO_PO4,
+ GPIO_PO5,
+ GPIO_PO6,
+ GPIO_PO7,
+ GPIO_PP0, /* pin 120 */
+ GPIO_PP1,
+ GPIO_PP2,
+ GPIO_PP3,
+ GPIO_PP4,
+ GPIO_PP5,
+ GPIO_PP6,
+ GPIO_PP7,
+ GPIO_PQ0, /* pin 128 */
+ GPIO_PQ1,
+ GPIO_PQ2,
+ GPIO_PQ3,
+ GPIO_PQ4,
+ GPIO_PQ5,
+ GPIO_PQ6,
+ GPIO_PQ7,
+ GPIO_PR0, /* pin 136 */
+ GPIO_PR1,
+ GPIO_PR2,
+ GPIO_PR3,
+ GPIO_PR4,
+ GPIO_PR5,
+ GPIO_PR6,
+ GPIO_PR7,
+ GPIO_PS0, /* pin 144 */
+ GPIO_PS1,
+ GPIO_PS2,
+ GPIO_PS3,
+ GPIO_PS4,
+ GPIO_PS5,
+ GPIO_PS6,
+ GPIO_PS7,
+ GPIO_PT0, /* pin 152 */
+ GPIO_PT1,
+ GPIO_PT2,
+ GPIO_PT3,
+ GPIO_PT4,
+ GPIO_PT5,
+ GPIO_PT6,
+ GPIO_PT7,
+ GPIO_PU0, /* pin 160 */
+ GPIO_PU1,
+ GPIO_PU2,
+ GPIO_PU3,
+ GPIO_PU4,
+ GPIO_PU5,
+ GPIO_PU6,
+ GPIO_PU7,
+ GPIO_PV0, /* pin 168 */
+ GPIO_PV1,
+ GPIO_PV2,
+ GPIO_PV3,
+ GPIO_PV4,
+ GPIO_PV5,
+ GPIO_PV6,
+ GPIO_PV7,
+ GPIO_PW0, /* pin 176 */
+ GPIO_PW1,
+ GPIO_PW2,
+ GPIO_PW3,
+ GPIO_PW4,
+ GPIO_PW5,
+ GPIO_PW6,
+ GPIO_PW7,
+ GPIO_PX0, /* pin 184 */
+ GPIO_PX1,
+ GPIO_PX2,
+ GPIO_PX3,
+ GPIO_PX4,
+ GPIO_PX5,
+ GPIO_PX6,
+ GPIO_PX7,
+ GPIO_PY0, /* pin 192 */
+ GPIO_PY1,
+ GPIO_PY2,
+ GPIO_PY3,
+ GPIO_PY4,
+ GPIO_PY5,
+ GPIO_PY6,
+ GPIO_PY7,
+ GPIO_PZ0, /* pin 200 */
+ GPIO_PZ1,
+ GPIO_PZ2,
+ GPIO_PZ3,
+ GPIO_PZ4,
+ GPIO_PZ5,
+ GPIO_PZ6,
+ GPIO_PZ7,
+ GPIO_PAA0, /* pin 208 */
+ GPIO_PAA1,
+ GPIO_PAA2,
+ GPIO_PAA3,
+ GPIO_PAA4,
+ GPIO_PAA5,
+ GPIO_PAA6,
+ GPIO_PAA7,
+ GPIO_PBB0, /* pin 216 */
+ GPIO_PBB1,
+ GPIO_PBB2,
+ GPIO_PBB3,
+ GPIO_PBB4,
+ GPIO_PBB5,
+ GPIO_PBB6,
+ GPIO_PBB7,
+ GPIO_PCC0, /* pin 224 */
+ GPIO_PCC1,
+ GPIO_PCC2,
+ GPIO_PCC3,
+ GPIO_PCC4,
+ GPIO_PCC5,
+ GPIO_PCC6,
+ GPIO_PCC7,
+ GPIO_PDD0, /* pin 232 */
+ GPIO_PDD1,
+ GPIO_PDD2,
+ GPIO_PDD3,
+ GPIO_PDD4,
+ GPIO_PDD5,
+ GPIO_PDD6,
+ GPIO_PDD7,
+ GPIO_PEE0, /* pin 240 */
+ GPIO_PEE1,
+ GPIO_PEE2,
+ GPIO_PEE3,
+ GPIO_PEE4,
+ GPIO_PEE5,
+ GPIO_PEE6,
+ GPIO_PEE7, /* pin 247 */
+};
+
+#endif /* _TEGRA30_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/hardware.h b/arch/arm/include/asm/arch-tegra30/hardware.h
new file mode 100644
index 0000000..b1a5aa9
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/hardware.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_HARDWARE_H_
+#define _TEGRA30_HARDWARE_H_
+
+/* include tegra specific hardware definitions */
+
+#endif /* _TEGRA30-HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
new file mode 100644
index 0000000..de1fc12
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -0,0 +1,604 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_PINMUX_H_
+#define _TEGRA30_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ * - function
+ * - pullup / pulldown
+ * - tristate or normal
+ */
+enum pmux_pingrp {
+ PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
+ PINGRP_ULPI_DATA1,
+ PINGRP_ULPI_DATA2,
+ PINGRP_ULPI_DATA3,
+ PINGRP_ULPI_DATA4,
+ PINGRP_ULPI_DATA5,
+ PINGRP_ULPI_DATA6,
+ PINGRP_ULPI_DATA7,
+ PINGRP_ULPI_CLK,
+ PINGRP_ULPI_DIR,
+ PINGRP_ULPI_NXT,
+ PINGRP_ULPI_STP,
+ PINGRP_DAP3_FS,
+ PINGRP_DAP3_DIN,
+ PINGRP_DAP3_DOUT,
+ PINGRP_DAP3_SCLK,
+ PINGRP_GPIO_PV0,
+ PINGRP_GPIO_PV1,
+ PINGRP_SDMMC1_CLK,
+ PINGRP_SDMMC1_CMD,
+ PINGRP_SDMMC1_DAT3,
+ PINGRP_SDMMC1_DAT2,
+ PINGRP_SDMMC1_DAT1,
+ PINGRP_SDMMC1_DAT0,
+ PINGRP_GPIO_PV2,
+ PINGRP_GPIO_PV3,
+ PINGRP_CLK2_OUT,
+ PINGRP_CLK2_REQ,
+ PINGRP_LCD_PWR1,
+ PINGRP_LCD_PWR2,
+ PINGRP_LCD_SDIN,
+ PINGRP_LCD_SDOUT,
+ PINGRP_LCD_WR_N,
+ PINGRP_LCD_CS0_N,
+ PINGRP_LCD_DC0,
+ PINGRP_LCD_SCK,
+ PINGRP_LCD_PWR0,
+ PINGRP_LCD_PCLK,
+ PINGRP_LCD_DE,
+ PINGRP_LCD_HSYNC,
+ PINGRP_LCD_VSYNC,
+ PINGRP_LCD_D0,
+ PINGRP_LCD_D1,
+ PINGRP_LCD_D2,
+ PINGRP_LCD_D3,
+ PINGRP_LCD_D4,
+ PINGRP_LCD_D5,
+ PINGRP_LCD_D6,
+ PINGRP_LCD_D7,
+ PINGRP_LCD_D8,
+ PINGRP_LCD_D9,
+ PINGRP_LCD_D10,
+ PINGRP_LCD_D11,
+ PINGRP_LCD_D12,
+ PINGRP_LCD_D13,
+ PINGRP_LCD_D14,
+ PINGRP_LCD_D15,
+ PINGRP_LCD_D16,
+ PINGRP_LCD_D17,
+ PINGRP_LCD_D18,
+ PINGRP_LCD_D19,
+ PINGRP_LCD_D20,
+ PINGRP_LCD_D21,
+ PINGRP_LCD_D22,
+ PINGRP_LCD_D23,
+ PINGRP_LCD_CS1_N,
+ PINGRP_LCD_M1,
+ PINGRP_LCD_DC1,
+ PINGRP_HDMI_INT,
+ PINGRP_DDC_SCL,
+ PINGRP_DDC_SDA,
+ PINGRP_CRT_HSYNC,
+ PINGRP_CRT_VSYNC,
+ PINGRP_VI_D0,
+ PINGRP_VI_D1,
+ PINGRP_VI_D2,
+ PINGRP_VI_D3,
+ PINGRP_VI_D4,
+ PINGRP_VI_D5,
+ PINGRP_VI_D6,
+ PINGRP_VI_D7,
+ PINGRP_VI_D8,
+ PINGRP_VI_D9,
+ PINGRP_VI_D10,
+ PINGRP_VI_D11,
+ PINGRP_VI_PCLK,
+ PINGRP_VI_MCLK,
+ PINGRP_VI_VSYNC,
+ PINGRP_VI_HSYNC,
+ PINGRP_UART2_RXD,
+ PINGRP_UART2_TXD,
+ PINGRP_UART2_RTS_N,
+ PINGRP_UART2_CTS_N,
+ PINGRP_UART3_TXD,
+ PINGRP_UART3_RXD,
+ PINGRP_UART3_CTS_N,
+ PINGRP_UART3_RTS_N,
+ PINGRP_GPIO_PU0,
+ PINGRP_GPIO_PU1,
+ PINGRP_GPIO_PU2,
+ PINGRP_GPIO_PU3,
+ PINGRP_GPIO_PU4,
+ PINGRP_GPIO_PU5,
+ PINGRP_GPIO_PU6,
+ PINGRP_GEN1_I2C_SDA,
+ PINGRP_GEN1_I2C_SCL,
+ PINGRP_DAP4_FS,
+ PINGRP_DAP4_DIN,
+ PINGRP_DAP4_DOUT,
+ PINGRP_DAP4_SCLK,
+ PINGRP_CLK3_OUT,
+ PINGRP_CLK3_REQ,
+ PINGRP_GMI_WP_N,
+ PINGRP_GMI_IORDY,
+ PINGRP_GMI_WAIT,
+ PINGRP_GMI_ADV_N,
+ PINGRP_GMI_CLK,
+ PINGRP_GMI_CS0_N,
+ PINGRP_GMI_CS1_N,
+ PINGRP_GMI_CS2_N,
+ PINGRP_GMI_CS3_N,
+ PINGRP_GMI_CS4_N,
+ PINGRP_GMI_CS6_N,
+ PINGRP_GMI_CS7_N,
+ PINGRP_GMI_AD0,
+ PINGRP_GMI_AD1,
+ PINGRP_GMI_AD2,
+ PINGRP_GMI_AD3,
+ PINGRP_GMI_AD4,
+ PINGRP_GMI_AD5,
+ PINGRP_GMI_AD6,
+ PINGRP_GMI_AD7,
+ PINGRP_GMI_AD8,
+ PINGRP_GMI_AD9,
+ PINGRP_GMI_AD10,
+ PINGRP_GMI_AD11,
+ PINGRP_GMI_AD12,
+ PINGRP_GMI_AD13,
+ PINGRP_GMI_AD14,
+ PINGRP_GMI_AD15,
+ PINGRP_GMI_A16,
+ PINGRP_GMI_A17,
+ PINGRP_GMI_A18,
+ PINGRP_GMI_A19,
+ PINGRP_GMI_WR_N,
+ PINGRP_GMI_OE_N,
+ PINGRP_GMI_DQS,
+ PINGRP_GMI_RST_N,
+ PINGRP_GEN2_I2C_SCL,
+ PINGRP_GEN2_I2C_SDA,
+ PINGRP_SDMMC4_CLK,
+ PINGRP_SDMMC4_CMD,
+ PINGRP_SDMMC4_DAT0,
+ PINGRP_SDMMC4_DAT1,
+ PINGRP_SDMMC4_DAT2,
+ PINGRP_SDMMC4_DAT3,
+ PINGRP_SDMMC4_DAT4,
+ PINGRP_SDMMC4_DAT5,
+ PINGRP_SDMMC4_DAT6,
+ PINGRP_SDMMC4_DAT7,
+ PINGRP_SDMMC4_RST_N,
+ PINGRP_CAM_MCLK,
+ PINGRP_GPIO_PCC1,
+ PINGRP_GPIO_PBB0,
+ PINGRP_CAM_I2C_SCL,
+ PINGRP_CAM_I2C_SDA,
+ PINGRP_GPIO_PBB3,
+ PINGRP_GPIO_PBB4,
+ PINGRP_GPIO_PBB5,
+ PINGRP_GPIO_PBB6,
+ PINGRP_GPIO_PBB7,
+ PINGRP_GPIO_PCC2,
+ PINGRP_JTAG_RTCK,
+ PINGRP_PWR_I2C_SCL,
+ PINGRP_PWR_I2C_SDA,
+ PINGRP_KB_ROW0,
+ PINGRP_KB_ROW1,
+ PINGRP_KB_ROW2,
+ PINGRP_KB_ROW3,
+ PINGRP_KB_ROW4,
+ PINGRP_KB_ROW5,
+ PINGRP_KB_ROW6,
+ PINGRP_KB_ROW7,
+ PINGRP_KB_ROW8,
+ PINGRP_KB_ROW9,
+ PINGRP_KB_ROW10,
+ PINGRP_KB_ROW11,
+ PINGRP_KB_ROW12,
+ PINGRP_KB_ROW13,
+ PINGRP_KB_ROW14,
+ PINGRP_KB_ROW15,
+ PINGRP_KB_COL0,
+ PINGRP_KB_COL1,
+ PINGRP_KB_COL2,
+ PINGRP_KB_COL3,
+ PINGRP_KB_COL4,
+ PINGRP_KB_COL5,
+ PINGRP_KB_COL6,
+ PINGRP_KB_COL7,
+ PINGRP_CLK_32K_OUT,
+ PINGRP_SYS_CLK_REQ,
+ PINGRP_CORE_PWR_REQ,
+ PINGRP_CPU_PWR_REQ,
+ PINGRP_PWR_INT_N,
+ PINGRP_CLK_32K_IN,
+ PINGRP_OWR,
+ PINGRP_DAP1_FS,
+ PINGRP_DAP1_DIN,
+ PINGRP_DAP1_DOUT,
+ PINGRP_DAP1_SCLK,
+ PINGRP_CLK1_REQ,
+ PINGRP_CLK1_OUT,
+ PINGRP_SPDIF_IN,
+ PINGRP_SPDIF_OUT,
+ PINGRP_DAP2_FS,
+ PINGRP_DAP2_DIN,
+ PINGRP_DAP2_DOUT,
+ PINGRP_DAP2_SCLK,
+ PINGRP_SPI2_MOSI,
+ PINGRP_SPI2_MISO,
+ PINGRP_SPI2_CS0_N,
+ PINGRP_SPI2_SCK,
+ PINGRP_SPI1_MOSI,
+ PINGRP_SPI1_SCK,
+ PINGRP_SPI1_CS0_N,
+ PINGRP_SPI1_MISO,
+ PINGRP_SPI2_CS1_N,
+ PINGRP_SPI2_CS2_N,
+ PINGRP_SDMMC3_CLK,
+ PINGRP_SDMMC3_CMD,
+ PINGRP_SDMMC3_DAT0,
+ PINGRP_SDMMC3_DAT1,
+ PINGRP_SDMMC3_DAT2,
+ PINGRP_SDMMC3_DAT3,
+ PINGRP_SDMMC3_DAT4,
+ PINGRP_SDMMC3_DAT5,
+ PINGRP_SDMMC3_DAT6,
+ PINGRP_SDMMC3_DAT7,
+ PINGRP_PEX_L0_PRSNT_N,
+ PINGRP_PEX_L0_RST_N,
+ PINGRP_PEX_L0_CLKREQ_N,
+ PINGRP_PEX_WAKE_N,
+ PINGRP_PEX_L1_PRSNT_N,
+ PINGRP_PEX_L1_RST_N,
+ PINGRP_PEX_L1_CLKREQ_N,
+ PINGRP_PEX_L2_PRSNT_N,
+ PINGRP_PEX_L2_RST_N,
+ PINGRP_PEX_L2_CLKREQ_N,
+ PINGRP_HDMI_CEC, /* offset 0x33e0 */
+ PINGRP_COUNT,
+};
+
+enum pdrive_pingrp {
+ PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
+ PDRIVE_PINGROUP_AO2,
+ PDRIVE_PINGROUP_AT1,
+ PDRIVE_PINGROUP_AT2,
+ PDRIVE_PINGROUP_AT3,
+ PDRIVE_PINGROUP_AT4,
+ PDRIVE_PINGROUP_AT5,
+ PDRIVE_PINGROUP_CDEV1,
+ PDRIVE_PINGROUP_CDEV2,
+ PDRIVE_PINGROUP_CSUS,
+ PDRIVE_PINGROUP_DAP1,
+ PDRIVE_PINGROUP_DAP2,
+ PDRIVE_PINGROUP_DAP3,
+ PDRIVE_PINGROUP_DAP4,
+ PDRIVE_PINGROUP_DBG,
+ PDRIVE_PINGROUP_LCD1,
+ PDRIVE_PINGROUP_LCD2,
+ PDRIVE_PINGROUP_SDIO2,
+ PDRIVE_PINGROUP_SDIO3,
+ PDRIVE_PINGROUP_SPI,
+ PDRIVE_PINGROUP_UAA,
+ PDRIVE_PINGROUP_UAB,
+ PDRIVE_PINGROUP_UART2,
+ PDRIVE_PINGROUP_UART3,
+ PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
+ PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
+ PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
+ PDRIVE_PINGROUP_DDC,
+ PDRIVE_PINGROUP_GMA,
+ PDRIVE_PINGROUP_GMB,
+ PDRIVE_PINGROUP_GMC,
+ PDRIVE_PINGROUP_GMD,
+ PDRIVE_PINGROUP_GME,
+ PDRIVE_PINGROUP_GMF,
+ PDRIVE_PINGROUP_GMG,
+ PDRIVE_PINGROUP_GMH,
+ PDRIVE_PINGROUP_OWR,
+ PDRIVE_PINGROUP_UAD,
+ PDRIVE_PINGROUP_GPV,
+ PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
+ PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
+ PDRIVE_PINGROUP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+ PMUX_FUNC_AHB_CLK,
+ PMUX_FUNC_APB_CLK,
+ PMUX_FUNC_AUDIO_SYNC,
+ PMUX_FUNC_CRT,
+ PMUX_FUNC_DAP1,
+ PMUX_FUNC_DAP2,
+ PMUX_FUNC_DAP3,
+ PMUX_FUNC_DAP4,
+ PMUX_FUNC_DAP5,
+ PMUX_FUNC_DISPA,
+ PMUX_FUNC_DISPB,
+ PMUX_FUNC_EMC_TEST0_DLL,
+ PMUX_FUNC_EMC_TEST1_DLL,
+ PMUX_FUNC_GMI,
+ PMUX_FUNC_GMI_INT,
+ PMUX_FUNC_HDMI,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
+ PMUX_FUNC_IDE,
+ PMUX_FUNC_IRDA,
+ PMUX_FUNC_KBC,
+ PMUX_FUNC_MIO,
+ PMUX_FUNC_MIPI_HS,
+ PMUX_FUNC_NAND,
+ PMUX_FUNC_OSC,
+ PMUX_FUNC_OWR,
+ PMUX_FUNC_PCIE,
+ PMUX_FUNC_PLLA_OUT,
+ PMUX_FUNC_PLLC_OUT1,
+ PMUX_FUNC_PLLM_OUT1,
+ PMUX_FUNC_PLLP_OUT2,
+ PMUX_FUNC_PLLP_OUT3,
+ PMUX_FUNC_PLLP_OUT4,
+ PMUX_FUNC_PWM,
+ PMUX_FUNC_PWR_INTR,
+ PMUX_FUNC_PWR_ON,
+ PMUX_FUNC_RTCK,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC2,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SDMMC4,
+ PMUX_FUNC_SFLASH,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI2_ALT,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
+ PMUX_FUNC_TRACE,
+ PMUX_FUNC_TWC,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_UARTE,
+ PMUX_FUNC_ULPI,
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_SENSOR_CLK,
+ PMUX_FUNC_XIO,
+ PMUX_FUNC_BLINK,
+ PMUX_FUNC_CEC,
+ PMUX_FUNC_CLK12,
+ PMUX_FUNC_DAP,
+ PMUX_FUNC_DAPSDMMC2,
+ PMUX_FUNC_DDR,
+ PMUX_FUNC_DEV3,
+ PMUX_FUNC_DTV,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT2,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_EMC_DLL,
+ PMUX_FUNC_EXTPERIPH1,
+ PMUX_FUNC_EXTPERIPH2,
+ PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_GMI_ALT,
+ PMUX_FUNC_HDA,
+ PMUX_FUNC_HSI,
+ PMUX_FUNC_I2C4,
+ PMUX_FUNC_I2C5,
+ PMUX_FUNC_I2CPWR,
+ PMUX_FUNC_I2S0,
+ PMUX_FUNC_I2S1,
+ PMUX_FUNC_I2S2,
+ PMUX_FUNC_I2S3,
+ PMUX_FUNC_I2S4,
+ PMUX_FUNC_NAND_ALT,
+ PMUX_FUNC_POPSDIO4,
+ PMUX_FUNC_POPSDMMC4,
+ PMUX_FUNC_PWM0,
+ PMUX_FUNC_PWM1,
+ PMUX_FUNC_PWM2,
+ PMUX_FUNC_PWM3,
+ PMUX_FUNC_SATA,
+ PMUX_FUNC_SPI5,
+ PMUX_FUNC_SPI6,
+ PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_VGP1,
+ PMUX_FUNC_VGP2,
+ PMUX_FUNC_VGP3,
+ PMUX_FUNC_VGP4,
+ PMUX_FUNC_VGP5,
+ PMUX_FUNC_VGP6,
+ PMUX_FUNC_CLK_12M_OUT,
+ PMUX_FUNC_HDCP,
+ PMUX_FUNC_TEST,
+ PMUX_FUNC_CORE_PWR_REQ,
+ PMUX_FUNC_CPU_PWR_REQ,
+ PMUX_FUNC_PWR_INT_N,
+ PMUX_FUNC_CLK_32K_IN,
+ PMUX_FUNC_SAFE,
+
+ PMUX_FUNC_MAX,
+
+ PMUX_FUNC_RSVD1 = 0x8000,
+ PMUX_FUNC_RSVD2 = 0x8001,
+ PMUX_FUNC_RSVD3 = 0x8002,
+ PMUX_FUNC_RSVD4 = 0x8003,
+};
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
+ || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+ PMUX_PULL_NORMAL = 0,
+ PMUX_PULL_DOWN,
+ PMUX_PULL_UP,
+};
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
+ ((pupd) <= PMUX_PULL_UP))
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+ PMUX_TRI_NORMAL = 0,
+ PMUX_TRI_TRISTATE = 1,
+};
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
+ && ((tristate) <= PMUX_TRI_TRISTATE))
+
+enum pmux_pin_io {
+ PMUX_PIN_OUTPUT = 0,
+ PMUX_PIN_INPUT = 1,
+};
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
+ ((io) <= PMUX_PIN_INPUT))
+
+enum pmux_pin_lock {
+ PMUX_PIN_LOCK_DEFAULT = 0,
+ PMUX_PIN_LOCK_DISABLE,
+ PMUX_PIN_LOCK_ENABLE,
+};
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
+ ((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+enum pmux_pin_od {
+ PMUX_PIN_OD_DEFAULT = 0,
+ PMUX_PIN_OD_DISABLE,
+ PMUX_PIN_OD_ENABLE,
+};
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
+ ((od) <= PMUX_PIN_OD_ENABLE))
+
+enum pmux_pin_ioreset {
+ PMUX_PIN_IO_RESET_DEFAULT = 0,
+ PMUX_PIN_IO_RESET_DISABLE,
+ PMUX_PIN_IO_RESET_ENABLE,
+};
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+ (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
+ ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+/* Available power domains used by pin groups */
+enum pmux_vddio {
+ PMUX_VDDIO_BB = 0,
+ PMUX_VDDIO_LCD,
+ PMUX_VDDIO_VI,
+ PMUX_VDDIO_UART,
+ PMUX_VDDIO_DDR,
+ PMUX_VDDIO_NAND,
+ PMUX_VDDIO_SYS,
+ PMUX_VDDIO_AUDIO,
+ PMUX_VDDIO_SD,
+ PMUX_VDDIO_CAM,
+ PMUX_VDDIO_GMI,
+ PMUX_VDDIO_PEXCTL,
+ PMUX_VDDIO_SDMMC1,
+ PMUX_VDDIO_SDMMC3,
+ PMUX_VDDIO_SDMMC4,
+
+ PMUX_VDDIO_NONE
+};
+
+/* t30 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
+#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+ PDRIVE_PINGROUP_COUNT)
+struct pmux_tri_ctlr {
+ uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
+ uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
+ uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
+ uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
+ uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
+ uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
+ uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
+
+ uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
+
+ uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
+ uint pmt_reserved5[PMUX_OFFSET];
+ uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
+};
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+ enum pmux_pingrp pingroup; /* pin group PINGRP_... */
+ enum pmux_func func; /* function to assign FUNC_... */
+ enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
+ enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
+ enum pmux_pin_io io; /* input or output PMUX_PIN_... */
+ enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
+ enum pmux_pin_od od; /* open-drain or push-pull driver */
+ enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
+};
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(struct pingroup_config *config);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void pinmux_config_table(struct pingroup_config *config, int len);
+
+/* Set a group of pins from a table */
+void pinmux_init(void);
+
+#endif /* _TEGRA30_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pmu.h b/arch/arm/include/asm/arch-tegra30/pmu.h
new file mode 100644
index 0000000..52bea29
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/pmu.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_PMU_H_
+#define _TEGRA30_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif /* _TEGRA30_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/spl.h b/arch/arm/include/asm/arch-tegra30/spl.h
new file mode 100644
index 0000000..5e453c5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/spl.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM 1
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
new file mode 100644
index 0000000..46a7474
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_H_
+#define _TEGRA30_H_
+
+#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */
+
+#endif /* TEGRA30_H */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 1/7] Tegra30: Add arch-tegra30 include files
2012-12-11 23:34 ` [U-Boot] [PATCH V3 1/7] Tegra30: Add arch-tegra30 include files Tom Warren
@ 2012-12-12 0:36 ` Stephen Warren
2012-12-12 16:23 ` Tom Warren
2012-12-12 14:55 ` Simon Glass
1 sibling, 1 reply; 31+ messages in thread
From: Stephen Warren @ 2012-12-12 0:36 UTC (permalink / raw)
To: u-boot
On 12/11/2012 04:34 PM, Tom Warren wrote:
> Common Tegra files are in arch-tegra, shared between T20 and T30.
> Tegra30-specific headers are in arch-tegra30. Note that some of
> these will be filled in as more T30 support is added (drivers,
> WB/LP0 support, etc.). A couple of Tegra20 files were changed
> to support common headers in arch-tegra, also.
> diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
> + TEGRA_SOC2_SLOW, /* T2x needs to run at slow clock initially */
I don't think that's used anywhere; drop it?
> - TEGRA_SOC_COUNT,
> + TEGRA_SOC_CNT,
A little arbitrary, but whatever.
Aside from that, this patch,
Reviewed-by: Stephen Warren <swarren@nvidia.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 1/7] Tegra30: Add arch-tegra30 include files
2012-12-12 0:36 ` Stephen Warren
@ 2012-12-12 16:23 ` Tom Warren
2012-12-12 22:02 ` Stephen Warren
0 siblings, 1 reply; 31+ messages in thread
From: Tom Warren @ 2012-12-12 16:23 UTC (permalink / raw)
To: u-boot
Stephen,
On Tue, Dec 11, 2012 at 5:36 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 12/11/2012 04:34 PM, Tom Warren wrote:
>> Common Tegra files are in arch-tegra, shared between T20 and T30.
>> Tegra30-specific headers are in arch-tegra30. Note that some of
>> these will be filled in as more T30 support is added (drivers,
>> WB/LP0 support, etc.). A couple of Tegra20 files were changed
>> to support common headers in arch-tegra, also.
>
>> diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
>
>> + TEGRA_SOC2_SLOW, /* T2x needs to run at slow clock initially */
>
> I don't think that's used anywhere; drop it?
This is a series to add T30 support. I've done some changes to
combine/commonize shared files, etc., but I've tried to avoid any
T20-only changes whenever possible.
I'll add this as a note in my to-do cleanup patch list for T20.
>
>> - TEGRA_SOC_COUNT,
>> + TEGRA_SOC_CNT,
>
> A little arbitrary, but whatever.
Not arbitrary, I needed to keep the tegra_pll_x_table declaration in
common/cpu.c below 80 chars, and didn't like the look of it anywhere I
split it, so I decided to shrink this label a bit since it was only
used in that one place and would have the least impact.
>
> Aside from that, this patch,
> Reviewed-by: Stephen Warren <swarren@nvidia.com>
Thanks,
Tom
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 1/7] Tegra30: Add arch-tegra30 include files
2012-12-12 16:23 ` Tom Warren
@ 2012-12-12 22:02 ` Stephen Warren
2012-12-12 23:06 ` Tom Warren
0 siblings, 1 reply; 31+ messages in thread
From: Stephen Warren @ 2012-12-12 22:02 UTC (permalink / raw)
To: u-boot
On 12/12/2012 09:23 AM, Tom Warren wrote:
> Stephen,
>
> On Tue, Dec 11, 2012 at 5:36 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 12/11/2012 04:34 PM, Tom Warren wrote:
>>> Common Tegra files are in arch-tegra, shared between T20 and T30.
>>> Tegra30-specific headers are in arch-tegra30. Note that some of
>>> these will be filled in as more T30 support is added (drivers,
>>> WB/LP0 support, etc.). A couple of Tegra20 files were changed
>>> to support common headers in arch-tegra, also.
>>
>>> diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
>>
>>> + TEGRA_SOC2_SLOW, /* T2x needs to run at slow clock initially */
>>
>> I don't think that's used anywhere; drop it?
>
> This is a series to add T30 support. I've done some changes to
> combine/commonize shared files, etc., but I've tried to avoid any
> T20-only changes whenever possible.
>
> I'll add this as a note in my to-do cleanup patch list for T20.
My point here was that this patch adds that unused enum. I think you can
just drop the addition from the patch, and it'll never need to be
cleaned up?
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 1/7] Tegra30: Add arch-tegra30 include files
2012-12-12 22:02 ` Stephen Warren
@ 2012-12-12 23:06 ` Tom Warren
0 siblings, 0 replies; 31+ messages in thread
From: Tom Warren @ 2012-12-12 23:06 UTC (permalink / raw)
To: u-boot
Stephen,
On Wed, Dec 12, 2012 at 3:02 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 12/12/2012 09:23 AM, Tom Warren wrote:
>> Stephen,
>>
>> On Tue, Dec 11, 2012 at 5:36 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> On 12/11/2012 04:34 PM, Tom Warren wrote:
>>>> Common Tegra files are in arch-tegra, shared between T20 and T30.
>>>> Tegra30-specific headers are in arch-tegra30. Note that some of
>>>> these will be filled in as more T30 support is added (drivers,
>>>> WB/LP0 support, etc.). A couple of Tegra20 files were changed
>>>> to support common headers in arch-tegra, also.
>>>
>>>> diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
>>>
>>>> + TEGRA_SOC2_SLOW, /* T2x needs to run at slow clock initially */
>>>
>>> I don't think that's used anywhere; drop it?
>>
>> This is a series to add T30 support. I've done some changes to
>> combine/commonize shared files, etc., but I've tried to avoid any
>> T20-only changes whenever possible.
>>
>> I'll add this as a note in my to-do cleanup patch list for T20.
>
> My point here was that this patch adds that unused enum. I think you can
> just drop the addition from the patch, and it'll never need to be
> cleaned up?
>
OK, good point. I had thought TEGRA_SOC2_SLOW was there originally in
the Tegra20 codebase, but you are right - it looks like I brought it
in, probably from our internal repo. I'll drop it. Thanks.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 1/7] Tegra30: Add arch-tegra30 include files
2012-12-11 23:34 ` [U-Boot] [PATCH V3 1/7] Tegra30: Add arch-tegra30 include files Tom Warren
2012-12-12 0:36 ` Stephen Warren
@ 2012-12-12 14:55 ` Simon Glass
1 sibling, 0 replies; 31+ messages in thread
From: Simon Glass @ 2012-12-12 14:55 UTC (permalink / raw)
To: u-boot
On Tue, Dec 11, 2012 at 3:34 PM, Tom Warren <twarren.nvidia@gmail.com> wrote:
> Common Tegra files are in arch-tegra, shared between T20 and T30.
> Tegra30-specific headers are in arch-tegra30. Note that some of
> these will be filled in as more T30 support is added (drivers,
> WB/LP0 support, etc.). A couple of Tegra20 files were changed
> to support common headers in arch-tegra, also.
>
> Signed-off-by: Tom Warren <twarren@nvidia.com>
Not a thorough review but it looks good, thanks.
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 2/7] Tegra30: Add AVP (arm720t) files
2012-12-11 23:34 [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Tom Warren
2012-12-11 23:34 ` [U-Boot] [PATCH V3 1/7] Tegra30: Add arch-tegra30 include files Tom Warren
@ 2012-12-11 23:34 ` Tom Warren
2012-12-12 0:40 ` Stephen Warren
2012-12-12 14:58 ` Simon Glass
2012-12-11 23:34 ` [U-Boot] [PATCH V3 3/7] Tegra30: Add CPU (armv7) files Tom Warren
` (6 subsequent siblings)
8 siblings, 2 replies; 31+ messages in thread
From: Tom Warren @ 2012-12-11 23:34 UTC (permalink / raw)
To: u-boot
This provides SPL support for T30 boards - AVP early init, plus
CPU (A9) init/jump to main U-Boot.
Some changes were made to Tegra20 cpu.c to move common routines
into tegra-common/cpu.c and reduce code duplication.
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
V2:
* Move common CPU init code to tegra-common/cpu.c
V3:
* Use 408MHz for PLLP.
* Cleanup whitespace
arch/arm/cpu/arm720t/tegra-common/Makefile | 1 +
arch/arm/cpu/arm720t/tegra-common/cpu.c | 335 ++++++++++++++++++++++++++++
arch/arm/cpu/arm720t/tegra-common/cpu.h | 68 ++----
arch/arm/cpu/arm720t/tegra-common/spl.c | 3 +-
arch/arm/cpu/arm720t/tegra20/cpu.c | 216 ++-----------------
arch/arm/cpu/arm720t/tegra30/Makefile | 41 ++++
arch/arm/cpu/arm720t/tegra30/config.mk | 19 ++
arch/arm/cpu/arm720t/tegra30/cpu.c | 176 +++++++++++++++
8 files changed, 612 insertions(+), 247 deletions(-)
create mode 100644 arch/arm/cpu/arm720t/tegra-common/cpu.c
create mode 100644 arch/arm/cpu/arm720t/tegra30/Makefile
create mode 100644 arch/arm/cpu/arm720t/tegra30/config.mk
create mode 100644 arch/arm/cpu/arm720t/tegra30/cpu.c
diff --git a/arch/arm/cpu/arm720t/tegra-common/Makefile b/arch/arm/cpu/arm720t/tegra-common/Makefile
index febd2e3..6cbc6ad 100644
--- a/arch/arm/cpu/arm720t/tegra-common/Makefile
+++ b/arch/arm/cpu/arm720t/tegra-common/Makefile
@@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libtegra-common.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
+COBJS-y += cpu.o
SRCS := $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
new file mode 100644
index 0000000..693d584
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include "cpu.h"
+
+enum tegra_family_t {
+ TEGRA_FAMILY_T2x,
+ TEGRA_FAMILY_T3x,
+};
+
+
+enum tegra_family_t get_family(void)
+{
+ u32 reg, chip_id;
+
+ reg = readl(NV_PA_APB_MISC_BASE + GP_HIDREV);
+
+ chip_id = reg >> 8;
+ chip_id &= 0xff;
+ debug(" tegra_get_family: chip_id = %x\n", chip_id);
+ if (chip_id == 0x30)
+ return TEGRA_FAMILY_T3x;
+ else
+ return TEGRA_FAMILY_T2x;
+}
+
+int get_num_cpus(void)
+{
+ return get_family() == TEGRA_FAMILY_T3x ? 4 : 2;
+}
+
+/*
+ * Timing tables for each SOC for all four oscillator options.
+ */
+struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
+ /* T20: 1 GHz */
+ {{ 1000, 13, 0, 12}, /* OSC 13M */
+ { 625, 12, 0, 8}, /* OSC 19.2M */
+ { 1000, 12, 0, 12}, /* OSC 12M */
+ { 1000, 26, 0, 12}, /* OSC 26M */
+ },
+
+ /* T25: 1.2 GHz */
+ {{ 923, 10, 0, 12},
+ { 750, 12, 0, 8},
+ { 600, 6, 0, 12},
+ { 600, 13, 0, 12},
+ },
+
+ /* T30: 1.4 GHz */
+ {{ 862, 8, 0, 8},
+ { 583, 8, 0, 4},
+ { 700, 6, 0, 8},
+ { 700, 13, 0, 8},
+ },
+
+ /* TEGRA_SOC2_SLOW: 312 MHz */
+ {{ 312, 13, 0, 12}, /* OSC 13M */
+ { 260, 16, 0, 8}, /* OSC 19.2M */
+ { 312, 12, 0, 12}, /* OSC 12M */
+ { 312, 26, 0, 12}, /* OSC 26M */
+ },
+};
+
+void adjust_pllp_out_freqs(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
+ u32 reg;
+
+ /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+ reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */
+ reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
+ | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
+ writel(reg, &pll->pll_out[0]);
+
+ reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */
+ reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
+ | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
+ writel(reg, &pll->pll_out[1]);
+}
+
+int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
+ u32 divp, u32 cpcon)
+{
+ u32 reg;
+
+ /* If PLLX is already enabled, just return */
+ if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
+ debug("pllx_set_rate: PLLX already enabled, returning\n");
+ return 0;
+ }
+
+ debug(" pllx_set_rate entry\n");
+
+ /* Set BYPASS, m, n and p to PLLX_BASE */
+ reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
+ reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
+ writel(reg, &pll->pll_base);
+
+ /* Set cpcon to PLLX_MISC */
+ reg = (cpcon << PLL_CPCON_SHIFT);
+
+ /* Set dccon to PLLX_MISC if freq > 600MHz */
+ if (divn > 600)
+ reg |= (1 << PLL_DCCON_SHIFT);
+ writel(reg, &pll->pll_misc);
+
+ /* Enable PLLX */
+ reg = readl(&pll->pll_base);
+ reg |= PLL_ENABLE_MASK;
+
+ /* Disable BYPASS */
+ reg &= ~PLL_BYPASS_MASK;
+ writel(reg, &pll->pll_base);
+
+ /* Set lock_enable to PLLX_MISC */
+ reg = readl(&pll->pll_misc);
+ reg |= PLL_LOCK_ENABLE_MASK;
+ writel(reg, &pll->pll_misc);
+
+ return 0;
+}
+
+void init_pllx(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
+ int chip_type;
+ enum clock_osc_freq osc;
+ struct clk_pll_table *sel;
+
+ debug("init_pllx entry\n");
+
+ /* get chip type */
+ chip_type = tegra_get_chip_type();
+ debug(" init_pllx: chip_type = %d\n", chip_type);
+
+ /* get osc freq */
+ osc = clock_get_osc_freq();
+ debug(" init_pllx: osc = %d\n", osc);
+
+ /* set pllx */
+ sel = &tegra_pll_x_table[chip_type][osc];
+ pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
+
+ /* adjust PLLP_out1-4 on T30 */
+ if (chip_type == TEGRA_SOC_T30) {
+ debug(" init_pllx: adjusting PLLP out freqs\n");
+ adjust_pllp_out_freqs();
+ }
+}
+
+void enable_cpu_clock(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 clk;
+
+ /*
+ * NOTE:
+ * Regardless of whether the request is to enable or disable the CPU
+ * clock, every processor in the CPU complex except the master (CPU 0)
+ * will have it's clock stopped because the AVP only talks to the
+ * master.
+ */
+
+ if (enable) {
+ /* Initialize PLLX */
+ init_pllx();
+
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+ writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+ }
+
+ /*
+ * Read the register containing the individual CPU clock enables and
+ * always stop the clocks to CPUs > 0.
+ */
+ clk = readl(&clkrst->crc_clk_cpu_cmplx);
+ clk |= 1 << CPU1_CLK_STP_SHIFT;
+#if defined(CONFIG_TEGRA30)
+ clk |= 1 << CPU2_CLK_STP_SHIFT;
+ clk |= 1 << CPU3_CLK_STP_SHIFT;
+#endif
+ /* Stop/Unstop the CPU clock */
+ clk &= ~CPU0_CLK_STP_MASK;
+ clk |= !enable << CPU0_CLK_STP_SHIFT;
+ writel(clk, &clkrst->crc_clk_cpu_cmplx);
+
+ clock_enable(PERIPH_ID_CPU);
+}
+
+static int is_cpu_powered(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
+}
+
+static void remove_cpu_io_clamps(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ /* Remove the clamps on the CPU I/O signals */
+ reg = readl(&pmc->pmc_remove_clamping);
+ reg |= CPU_CLMP;
+ writel(reg, &pmc->pmc_remove_clamping);
+
+ /* Give I/O signals time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+}
+
+void powerup_cpu(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+ int timeout = IO_STABILIZATION_DELAY;
+
+ if (!is_cpu_powered()) {
+ /* Toggle the CPU power state (OFF -> ON) */
+ reg = readl(&pmc->pmc_pwrgate_toggle);
+ reg &= PARTID_CP;
+ reg |= START_CP;
+ writel(reg, &pmc->pmc_pwrgate_toggle);
+
+ /* Wait for the power to come up */
+ while (!is_cpu_powered()) {
+ if (timeout-- == 0)
+ printf("CPU failed to power up!\n");
+ else
+ udelay(10);
+ }
+
+ /*
+ * Remove the I/O clamps from CPU power partition.
+ * Recommended only on a Warm boot, if the CPU partition gets
+ * power gated. Shouldn't cause any harm when called after a
+ * cold boot according to HW, probably just redundant.
+ */
+ remove_cpu_io_clamps();
+ }
+}
+
+void reset_A9_cpu(int reset)
+{
+ /*
+ * NOTE: Regardless of whether the request is to hold the CPU in reset
+ * or take it out of reset, every processor in the CPU complex
+ * except the master (CPU 0) will be held in reset because the
+ * AVP only talks to the master. The AVP does not know that there
+ * are multiple processors in the CPU complex.
+ */
+ int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
+ int num_cpus = get_num_cpus();
+ int cpu;
+
+ debug("reset_a9_cpu entry\n");
+ /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
+ for (cpu = 1; cpu < num_cpus; cpu++)
+ reset_cmplx_set_enable(cpu, mask, 1);
+ reset_cmplx_set_enable(0, mask, reset);
+
+ /* Enable/Disable master CPU reset */
+ reset_set_enable(PERIPH_ID_CPU, reset);
+}
+
+void clock_enable_coresight(int enable)
+{
+ u32 rst, src;
+
+ debug("clock_enable_coresight entry\n");
+ clock_set_enable(PERIPH_ID_CORESIGHT, enable);
+ reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
+
+ if (enable) {
+ /*
+ * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
+ * 1.5, giving an effective frequency of 144MHz.
+ * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
+ * (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
+ *
+ * Clock divider request for 204MHz would setup CSITE clock as
+ * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz
+ */
+ if (tegra_get_chip_type() == TEGRA_SOC_T30)
+ src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
+ else
+ src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
+ clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
+
+ /* Unlock the CPU CoreSight interfaces */
+ rst = CORESIGHT_UNLOCK;
+ writel(rst, CSITE_CPU_DBG0_LAR);
+ writel(rst, CSITE_CPU_DBG1_LAR);
+#if defined(CONFIG_TEGRA30)
+ writel(rst, CSITE_CPU_DBG2_LAR);
+ writel(rst, CSITE_CPU_DBG3_LAR);
+#endif
+ }
+}
+
+void halt_avp(void)
+{
+ for (;;) {
+ writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
+ | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
+ FLOW_CTLR_HALT_COP_EVENTS);
+ }
+}
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h
index 6804cd7..3e2ea3a 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h
@@ -26,7 +26,11 @@
#define PLL_STABILIZATION_DELAY (300)
#define IO_STABILIZATION_DELAY (1000)
+#if defined(CONFIG_TEGRA30)
+#define NVBL_PLLP_KHZ (408000)
+#else /* Tegra20 */
#define NVBL_PLLP_KHZ (216000)
+#endif
#define PLLX_ENABLED (1 << 30)
#define CCLK_BURST_POLICY 0x20008888
@@ -44,50 +48,11 @@
#define CORESIGHT_UNLOCK 0xC5ACCE55;
-/* AP20-Specific Base Addresses */
-
-/* AP20 Base physical address of SDRAM. */
-#define AP20_BASE_PA_SDRAM 0x00000000
-/* AP20 Base physical address of internal SRAM. */
-#define AP20_BASE_PA_SRAM 0x40000000
-/* AP20 Size of internal SRAM (256KB). */
-#define AP20_BASE_PA_SRAM_SIZE 0x00040000
-/* AP20 Base physical address of flash. */
-#define AP20_BASE_PA_NOR_FLASH 0xD0000000
-/* AP20 Base physical address of boot information table. */
-#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
-
-/*
- * Super-temporary stacks for EXTREMELY early startup. The values chosen for
- * these addresses must be valid on ALL SOCs because this value is used before
- * we are able to differentiate between the SOC types.
- *
- * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
- * stack is placed below the AVP stack. Once the CPU stack has been moved,
- * the AVP is free to use the IRAM the CPU stack previously occupied if
- * it should need to do so.
- *
- * NOTE: In multi-processor CPU complex configurations, each processor will have
- * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
- * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
- * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
- * CPU.
- */
-
-/* Common AVP early boot stack limit */
-#define AVP_EARLY_BOOT_STACK_LIMIT \
- (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
-/* Common AVP early boot stack size */
-#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
-/* Common CPU early boot stack limit */
-#define CPU_EARLY_BOOT_STACK_LIMIT \
- (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
-/* Common CPU early boot stack size */
-#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
-
#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
+#define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
+#define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
#define FLOW_MODE_STOP 2
@@ -95,6 +60,23 @@
#define HALT_COP_EVENT_IRQ_1 (1 << 11)
#define HALT_COP_EVENT_FIQ_1 (1 << 9)
-void start_cpu(u32 reset_vector);
-int ap20_cpu_is_cortexa9(void);
+#define FLOW_MODE_NONE 0
+
+#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
+
+struct clk_pll_table {
+ u16 n;
+ u16 m;
+ u8 p;
+ u8 cpcon;
+};
+
+void clock_enable_coresight(int enable);
+void enable_cpu_clock(int enable);
void halt_avp(void) __attribute__ ((noreturn));
+void init_pllx(void);
+void powerup_cpu(void);
+void reset_A9_cpu(int reset);
+void start_cpu(u32 reset_vector);
+int tegra_get_chip_type(void);
+void adjust_pllp_out_freqs(void);
diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c
index c280ab7..a9a1c39 100644
--- a/arch/arm/cpu/arm720t/tegra-common/spl.c
+++ b/arch/arm/cpu/arm720t/tegra-common/spl.c
@@ -23,7 +23,6 @@
* MA 02111-1307 USA
*/
#include <common.h>
-#include "cpu.h"
#include <spl.h>
#include <asm/io.h>
@@ -32,7 +31,7 @@
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch/spl.h>
-
+#include "cpu.h"
void spl_board_init(void)
{
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/cpu/arm720t/tegra20/cpu.c
index ef7f375..2533899 100644
--- a/arch/arm/cpu/arm720t/tegra20/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra20/cpu.c
@@ -1,160 +1,25 @@
/*
-* (C) Copyright 2010-2011
-* NVIDIA Corporation <www.nvidia.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/scu.h>
#include "../tegra-common/cpu.h"
-/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
-int ap20_cpu_is_cortexa9(void)
-{
- u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
- return id == (PG_UP_TAG_0_PID_CPU & 0xff);
-}
-
-void init_pllx(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
- u32 reg;
-
- /* If PLLX is already enabled, just return */
- if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
- return;
-
- /* Set PLLX_MISC */
- writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
-
- /* Use 12MHz clock here */
- reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
- reg |= 1000 << PLL_DIVN_SHIFT;
- writel(reg, &pll->pll_base);
-
- reg |= PLL_ENABLE_MASK;
- writel(reg, &pll->pll_base);
-
- reg &= ~PLL_BYPASS_MASK;
- writel(reg, &pll->pll_base);
-}
-
-static void enable_cpu_clock(int enable)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 clk;
-
- /*
- * NOTE:
- * Regardless of whether the request is to enable or disable the CPU
- * clock, every processor in the CPU complex except the master (CPU 0)
- * will have it's clock stopped because the AVP only talks to the
- * master. The AVP does not know (nor does it need to know) that there
- * are multiple processors in the CPU complex.
- */
-
- if (enable) {
- /* Initialize PLLX */
- init_pllx();
-
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
- }
-
- /*
- * Read the register containing the individual CPU clock enables and
- * always stop the clock to CPU 1.
- */
- clk = readl(&clkrst->crc_clk_cpu_cmplx);
- clk |= 1 << CPU1_CLK_STP_SHIFT;
-
- /* Stop/Unstop the CPU clock */
- clk &= ~CPU0_CLK_STP_MASK;
- clk |= !enable << CPU0_CLK_STP_SHIFT;
- writel(clk, &clkrst->crc_clk_cpu_cmplx);
-
- clock_enable(PERIPH_ID_CPU);
-}
-
-static int is_cpu_powered(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
-}
-
-static void remove_cpu_io_clamps(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- /* Remove the clamps on the CPU I/O signals */
- reg = readl(&pmc->pmc_remove_clamping);
- reg |= CPU_CLMP;
- writel(reg, &pmc->pmc_remove_clamping);
-
- /* Give I/O signals time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
-}
-
-static void powerup_cpu(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
- int timeout = IO_STABILIZATION_DELAY;
-
- if (!is_cpu_powered()) {
- /* Toggle the CPU power state (OFF -> ON) */
- reg = readl(&pmc->pmc_pwrgate_toggle);
- reg &= PARTID_CP;
- reg |= START_CP;
- writel(reg, &pmc->pmc_pwrgate_toggle);
-
- /* Wait for the power to come up */
- while (!is_cpu_powered()) {
- if (timeout-- == 0)
- printf("CPU failed to power up!\n");
- else
- udelay(10);
- }
-
- /*
- * Remove the I/O clamps from CPU power partition.
- * Recommended only on a Warm boot, if the CPU partition gets
- * power gated. Shouldn't cause any harm when called after a
- * cold boot according to HW, probably just redundant.
- */
- remove_cpu_io_clamps();
- }
-}
-
static void enable_cpu_power_rail(void)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
@@ -173,49 +38,6 @@ static void enable_cpu_power_rail(void)
udelay(3750);
}
-static void reset_A9_cpu(int reset)
-{
- /*
- * NOTE: Regardless of whether the request is to hold the CPU in reset
- * or take it out of reset, every processor in the CPU complex
- * except the master (CPU 0) will be held in reset because the
- * AVP only talks to the master. The AVP does not know that there
- * are multiple processors in the CPU complex.
- */
-
- /* Hold CPU 1 in reset, and CPU 0 if asked */
- reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
- reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
- reset);
-
- /* Enable/Disable master CPU reset */
- reset_set_enable(PERIPH_ID_CPU, reset);
-}
-
-static void clock_enable_coresight(int enable)
-{
- u32 rst, src;
-
- clock_set_enable(PERIPH_ID_CORESIGHT, enable);
- reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
-
- if (enable) {
- /*
- * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
- * 1.5, giving an effective frequency of 144MHz.
- * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
- * (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
- */
- src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
- clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
-
- /* Unlock the CPU CoreSight interfaces */
- rst = 0xC5ACCE55;
- writel(rst, CSITE_CPU_DBG0_LAR);
- writel(rst, CSITE_CPU_DBG1_LAR);
- }
-}
-
void start_cpu(u32 reset_vector)
{
/* Enable VDD_CPU */
@@ -246,13 +68,3 @@ void start_cpu(u32 reset_vector)
/* Take the CPU out of reset */
reset_A9_cpu(0);
}
-
-
-void halt_avp(void)
-{
- for (;;) {
- writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
- | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
- FLOW_CTLR_HALT_COP_EVENTS);
- }
-}
diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/arm720t/tegra30/Makefile
new file mode 100644
index 0000000..bd96997
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra30/Makefile
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y += cpu.o
+
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm720t/tegra30/config.mk b/arch/arm/cpu/arm720t/tegra30/config.mk
new file mode 100644
index 0000000..2388c56
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra30/config.mk
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
new file mode 100644
index 0000000..dedcdd9
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra30-specific CPU init code */
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(addr, ®->cmd_addr0);
+ writel(config, ®->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(data, ®->cmd_data1);
+ writel(config, ®->cnfg);
+}
+
+#define TPS65911_I2C_ADDR 0x5A
+#define TPS65911_VDDCTRL_OP_REG 0x28
+#define TPS65911_VDDCTRL_SR_REG 0x27
+#define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
+#define I2C_SEND_2_BYTES 0x0A02
+
+static void enable_cpu_power_rail(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ debug("enable_cpu_power_rail entry\n");
+ reg = readl(&pmc->pmc_cntrl);
+ reg |= CPUPWRREQ_OE;
+ writel(reg, &pmc->pmc_cntrl);
+
+ /*
+ * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+ * First set VDD to 1.4V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
+ udelay(1000);
+ tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
+ udelay(10 * 1000);
+}
+
+/**
+ * The T30 requires some special clock initialization, including setting up
+ * the dvc i2c, turning on mselect and selecting the G CPU cluster
+ */
+void t30_init_clocks(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+ u32 val;
+
+ debug("t30_init_clocks entry\n");
+ /* Set active CPU cluster to G */
+ clrbits_le32(flow->cluster_control, 1 << 0);
+
+ /*
+ * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
+ *@108 MHz. This is glitch free as only the source is changed, no
+ * special precaution needed.
+ */
+ val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+ (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+ (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+ (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+ (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
+ writel(val, &clkrst->crc_sclk_brst_pol);
+
+ writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
+
+ val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
+ (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
+ (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
+ (0 << CLK_SYS_RATE_APB_RATE_SHIFT);
+ writel(val, &clkrst->crc_clk_sys_rate);
+
+ /* Put i2c, mselect in reset and enable clocks */
+ reset_set_enable(PERIPH_ID_DVC_I2C, 1);
+ clock_set_enable(PERIPH_ID_DVC_I2C, 1);
+ reset_set_enable(PERIPH_ID_MSELECT, 1);
+ clock_set_enable(PERIPH_ID_MSELECT, 1);
+
+ /* Switch MSELECT clock to PLLP (00) */
+ clock_ll_set_source(PERIPH_ID_MSELECT, 0);
+
+ /*
+ * Our high-level clock routines are not available prior to
+ * relocation. We use the low-level functions which require a
+ * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
+ */
+ clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
+
+ /*
+ * Give clocks time to stabilize, then take i2c and mselect out of
+ * reset
+ */
+ udelay(1000);
+ reset_set_enable(PERIPH_ID_DVC_I2C, 0);
+ reset_set_enable(PERIPH_ID_MSELECT, 0);
+}
+
+static void set_cpu_running(int run)
+{
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+
+ debug("set_cpu_running entry, run = %d\n", run);
+ writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
+}
+
+void start_cpu(u32 reset_vector)
+{
+ debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+ t30_init_clocks();
+
+ /* Enable VDD_CPU */
+ enable_cpu_power_rail();
+
+ set_cpu_running(0);
+
+ /* Hold the CPUs in reset */
+ reset_A9_cpu(1);
+
+ /* Disable the CPU clock */
+ enable_cpu_clock(0);
+
+ /* Enable CoreSight */
+ clock_enable_coresight(1);
+
+ /*
+ * Set the entry point for CPU execution from reset,
+ * if it's a non-zero value.
+ */
+ if (reset_vector)
+ writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+ /* Enable the CPU clock */
+ enable_cpu_clock(1);
+
+ /* If the CPU doesn't already have power, power it up */
+ powerup_cpu();
+
+ /* Take the CPU out of reset */
+ reset_A9_cpu(0);
+
+ set_cpu_running(1);
+}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 2/7] Tegra30: Add AVP (arm720t) files
2012-12-11 23:34 ` [U-Boot] [PATCH V3 2/7] Tegra30: Add AVP (arm720t) files Tom Warren
@ 2012-12-12 0:40 ` Stephen Warren
2012-12-12 16:24 ` Tom Warren
2012-12-12 14:58 ` Simon Glass
1 sibling, 1 reply; 31+ messages in thread
From: Stephen Warren @ 2012-12-12 0:40 UTC (permalink / raw)
To: u-boot
On 12/11/2012 04:34 PM, Tom Warren wrote:
> This provides SPL support for T30 boards - AVP early init, plus
> CPU (A9) init/jump to main U-Boot.
>
> Some changes were made to Tegra20 cpu.c to move common routines
> into tegra-common/cpu.c and reduce code duplication.
> diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
> +struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
> + /* TEGRA_SOC2_SLOW: 312 MHz */
> + {{ 312, 13, 0, 12}, /* OSC 13M */
> + { 260, 16, 0, 8}, /* OSC 19.2M */
> + { 312, 12, 0, 12}, /* OSC 12M */
> + { 312, 26, 0, 12}, /* OSC 26M */
> + },
Given my comment on patch 1, I'd suggest dropping that table entry too.
Aside from that, this patch,
Reviewed-by: Stephen Warren <swarren@nvidia.com>
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 2/7] Tegra30: Add AVP (arm720t) files
2012-12-12 0:40 ` Stephen Warren
@ 2012-12-12 16:24 ` Tom Warren
0 siblings, 0 replies; 31+ messages in thread
From: Tom Warren @ 2012-12-12 16:24 UTC (permalink / raw)
To: u-boot
Stephen,
On Tue, Dec 11, 2012 at 5:40 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 12/11/2012 04:34 PM, Tom Warren wrote:
>> This provides SPL support for T30 boards - AVP early init, plus
>> CPU (A9) init/jump to main U-Boot.
>>
>> Some changes were made to Tegra20 cpu.c to move common routines
>> into tegra-common/cpu.c and reduce code duplication.
>
>> diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
>
>> +struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
>
>> + /* TEGRA_SOC2_SLOW: 312 MHz */
>> + {{ 312, 13, 0, 12}, /* OSC 13M */
>> + { 260, 16, 0, 8}, /* OSC 19.2M */
>> + { 312, 12, 0, 12}, /* OSC 12M */
>> + { 312, 26, 0, 12}, /* OSC 26M */
>> + },
>
> Given my comment on patch 1, I'd suggest dropping that table entry too.
Will do, in a future cleanup patchset.
>
> Aside from that, this patch,
> Reviewed-by: Stephen Warren <swarren@nvidia.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 2/7] Tegra30: Add AVP (arm720t) files
2012-12-11 23:34 ` [U-Boot] [PATCH V3 2/7] Tegra30: Add AVP (arm720t) files Tom Warren
2012-12-12 0:40 ` Stephen Warren
@ 2012-12-12 14:58 ` Simon Glass
1 sibling, 0 replies; 31+ messages in thread
From: Simon Glass @ 2012-12-12 14:58 UTC (permalink / raw)
To: u-boot
On Tue, Dec 11, 2012 at 3:34 PM, Tom Warren <twarren.nvidia@gmail.com> wrote:
> This provides SPL support for T30 boards - AVP early init, plus
> CPU (A9) init/jump to main U-Boot.
>
> Some changes were made to Tegra20 cpu.c to move common routines
> into tegra-common/cpu.c and reduce code duplication.
>
> Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 3/7] Tegra30: Add CPU (armv7) files
2012-12-11 23:34 [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Tom Warren
2012-12-11 23:34 ` [U-Boot] [PATCH V3 1/7] Tegra30: Add arch-tegra30 include files Tom Warren
2012-12-11 23:34 ` [U-Boot] [PATCH V3 2/7] Tegra30: Add AVP (arm720t) files Tom Warren
@ 2012-12-11 23:34 ` Tom Warren
2012-12-12 0:41 ` Stephen Warren
2012-12-11 23:34 ` [U-Boot] [PATCH V3 4/7] Tegra30: Add common CPU (shared) files Tom Warren
` (5 subsequent siblings)
8 siblings, 1 reply; 31+ messages in thread
From: Tom Warren @ 2012-12-11 23:34 UTC (permalink / raw)
To: u-boot
These files are for code that runs on the CPU (A9) on T30 boards.
At this time, there are no T30-specific ARMV7 files. As T30-specific
run-time code is added, it'll go here.
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
V2: Cleanup whitespace issues
V3: Change commit msg
arch/arm/cpu/armv7/tegra30/Makefile | 40 ++++++++++++++++++++++++++++++++++
arch/arm/cpu/armv7/tegra30/config.mk | 19 ++++++++++++++++
2 files changed, 59 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/tegra30/Makefile
create mode 100644 arch/arm/cpu/armv7/tegra30/config.mk
diff --git a/arch/arm/cpu/armv7/tegra30/Makefile b/arch/arm/cpu/armv7/tegra30/Makefile
new file mode 100644
index 0000000..04adb52
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra30/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/tegra30/config.mk b/arch/arm/cpu/armv7/tegra30/config.mk
new file mode 100644
index 0000000..719ca81
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra30/config.mk
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+CONFIG_ARCH_DEVICE_TREE := tegra30
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 4/7] Tegra30: Add common CPU (shared) files
2012-12-11 23:34 [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Tom Warren
` (2 preceding siblings ...)
2012-12-11 23:34 ` [U-Boot] [PATCH V3 3/7] Tegra30: Add CPU (armv7) files Tom Warren
@ 2012-12-11 23:34 ` Tom Warren
2012-12-12 0:45 ` Allen Martin
2012-12-12 22:09 ` Stephen Warren
2012-12-11 23:34 ` [U-Boot] [PATCH V3 5/7] Tegra30: Cardhu: Add DT files Tom Warren
` (4 subsequent siblings)
8 siblings, 2 replies; 31+ messages in thread
From: Tom Warren @ 2012-12-11 23:34 UTC (permalink / raw)
To: u-boot
These files are used by both SPL and main U-Boot.
Also made minor changes to shared Tegra code to support
T30 differences.
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
V2:
* Differentiate between T20 and T30 in ODMDATA and query_sdram_size.
* Fix numerous func entries in pingroup table as per Stephen.
* Added warning about LOCK bit in pinmux_set_lock.
V3:
* Always program PLLP to 408MHz
* Use generic SoC string in print_cpuinfo
arch/arm/cpu/tegra-common/ap.c | 14 +-
arch/arm/cpu/tegra-common/board.c | 41 ++-
arch/arm/cpu/tegra-common/sys_info.c | 16 +-
arch/arm/cpu/tegra20-common/warmboot.c | 2 +-
.../{arm720t/tegra30 => tegra30-common}/Makefile | 11 +-
.../cpu/{tegra20-common => tegra30-common}/clock.c | 516 +++++++++-----------
arch/arm/cpu/tegra30-common/funcmux.c | 57 +++
arch/arm/cpu/tegra30-common/pinmux.c | 506 +++++++++++++++++++
arch/arm/include/asm/arch-tegra/ap.h | 52 +--
9 files changed, 880 insertions(+), 335 deletions(-)
copy arch/arm/cpu/{arm720t/tegra30 => tegra30-common}/Makefile (80%)
copy arch/arm/cpu/{tegra20-common => tegra30-common}/clock.c (74%)
create mode 100644 arch/arm/cpu/tegra30-common/funcmux.c
create mode 100644 arch/arm/cpu/tegra30-common/pinmux.c
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index c4eb137..aebe29e 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -20,10 +20,14 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+
+/* Tegra AP (Application Processor) code */
+
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clock.h>
#include <asm/arch-tegra/fuse.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/scu.h>
@@ -58,6 +62,12 @@ int tegra_get_chip_type(void)
return TEGRA_SOC_T25;
}
break;
+ case CHIPID_TEGRA30:
+ switch (tegra_sku_id) {
+ case SKU_ID_T30:
+ return TEGRA_SOC_T30;
+ }
+ break;
}
/* unknown sku id */
return TEGRA_SOC_UNKNOWN;
@@ -93,7 +103,7 @@ static u32 get_odmdata(void)
u32 bct_start, odmdata;
- bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
+ bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
return odmdata;
@@ -127,5 +137,5 @@ void s_init(void)
"orr r0, r0, #0x41\n"
"mcr p15, 0, r0, c1, c0, 1\n");
- /* FIXME: should have ap20's L2 disabled too? */
+ /* FIXME: should have SoC's L2 disabled too? */
}
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
index b2e10c6..af1879c 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/cpu/tegra-common/board.c
@@ -54,16 +54,37 @@ unsigned int query_sdram_size(void)
reg = readl(&pmc->pmc_scratch20);
debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
- /* bits 31:28 in OdmData are used for RAM size */
+#if defined(CONFIG_TEGRA20)
+ /* bits 30:28 in OdmData are used for RAM size on T20 */
+ reg &= 0x70000000;
+
switch ((reg) >> 28) {
case 1:
return 0x10000000; /* 256 MB */
+ case 0:
case 2:
default:
return 0x20000000; /* 512 MB */
case 3:
return 0x40000000; /* 1GB */
}
+#else /* Tegra30 */
+ /* bits 31:28 in OdmData are used for RAM size on T30 */
+ switch ((reg) >> 28) {
+ case 0:
+ case 1:
+ default:
+ return 0x10000000; /* 256 MB */
+ case 2:
+ return 0x20000000; /* 512 MB */
+ case 3:
+ return 0x30000000; /* 768 MB */
+ case 4:
+ return 0x40000000; /* 1GB */
+ case 8:
+ return 0x7ff00000; /* 2GB - 1MB */
+ }
+#endif
}
int dram_init(void)
@@ -82,19 +103,27 @@ int checkboard(void)
#endif /* CONFIG_DISPLAY_BOARDINFO */
static int uart_configs[] = {
-#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
+#if defined(CONFIG_TEGRA20)
+ #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
FUNCMUX_UART1_UAA_UAB,
-#elif defined(CONFIG_TEGRA_UARTA_GPU)
+ #elif defined(CONFIG_TEGRA_UARTA_GPU)
FUNCMUX_UART1_GPU,
-#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
+ #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
FUNCMUX_UART1_SDIO1,
-#else
+ #else
FUNCMUX_UART1_IRRX_IRTX,
-#endif
+ #endif
FUNCMUX_UART2_IRDA,
-1,
FUNCMUX_UART4_GMC,
-1,
+#else /* Tegra30 */
+ FUNCMUX_UART1_ULPI, /* UARTA */
+ -1,
+ -1,
+ -1,
+ -1,
+#endif
};
/**
diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/cpu/tegra-common/sys_info.c
index 1a0bb56..4632f15 100644
--- a/arch/arm/cpu/tegra-common/sys_info.c
+++ b/arch/arm/cpu/tegra-common/sys_info.c
@@ -22,12 +22,26 @@
*/
#include <common.h>
+#include <linux/ctype.h>
#ifdef CONFIG_DISPLAY_CPUINFO
+void upstring(char *s)
+{
+ while (*s) {
+ *s = toupper(*s);
+ s++;
+ }
+}
+
/* Print CPU information */
int print_cpuinfo(void)
{
- puts("TEGRA20\n");
+ char soc_name[10];
+
+ strncpy(soc_name, CONFIG_SYS_SOC, 10);
+ upstring(soc_name);
+ puts(soc_name);
+ puts("\n");
/* TBD: Add printf of major/minor rev info, stepping, etc. */
return 0;
diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c
index 157b9ab..0d472cf 100644
--- a/arch/arm/cpu/tegra20-common/warmboot.c
+++ b/arch/arm/cpu/tegra20-common/warmboot.c
@@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
* This is the place in SRAM where the SDRAM parameters are stored. There
* are 4 blocks, one for each RAM code
*/
-#define SDRAM_PARAMS_BASE (AP20_BASE_PA_SRAM + 0x188)
+#define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
/* TODO: If we later add support for the Misc GP controller, refactor this */
union xm2cfga_reg {
diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/tegra30-common/Makefile
similarity index 80%
copy from arch/arm/cpu/arm720t/tegra30/Makefile
copy to arch/arm/cpu/tegra30-common/Makefile
index bd96997..75fef32 100644
--- a/arch/arm/cpu/arm720t/tegra30/Makefile
+++ b/arch/arm/cpu/tegra30-common/Makefile
@@ -19,12 +19,15 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).o
+# The AVP is ARMv4T architecture so we must use special compiler
+# flags for any startup files it might use.
-COBJS-y += cpu.o
+LIB = $(obj)lib$(SOC)-common.o
-SRCS := $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS-y))
+COBJS-y += clock.o funcmux.o pinmux.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)
diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c
similarity index 74%
copy from arch/arm/cpu/tegra20-common/clock.c
copy to arch/arm/cpu/tegra30-common/clock.c
index 12987a6..5db9d20 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -1,25 +1,20 @@
/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * See file CREDITS for list of people who contributed to this
- * project.
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
*
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
*
* You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-/* Tegra20 Clock control functions */
+/* Tegra30 Clock control functions */
#include <common.h>
#include <asm/io.h>
@@ -49,7 +44,7 @@ static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
};
/*
- * Clock types that we can use as a source. The Tegra20 has muxes for the
+ * Clock types that we can use as a source. The Tegra3 has muxes for the
* peripheral clocks, and in most cases there are four options for the clock
* source. This gives us a clock 'type' and exploits what commonality exists
* in the device.
@@ -68,9 +63,11 @@ enum clock_type_id {
CLOCK_TYPE_MCPT,
CLOCK_TYPE_PCM,
CLOCK_TYPE_PCMT,
- CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
- CLOCK_TYPE_PCXTS,
CLOCK_TYPE_PDCT,
+ CLOCK_TYPE_ACPT,
+ CLOCK_TYPE_ASPTE,
+ CLOCK_TYPE_PMDACD2T,
+ CLOCK_TYPE_PCST,
CLOCK_TYPE_COUNT,
CLOCK_TYPE_NONE = -1, /* invalid clock type */
@@ -83,113 +80,55 @@ enum clock_type_id {
char pllp_valid = 1; /* PLLP is set up correctly */
enum {
- CLOCK_MAX_MUX = 4 /* number of source options for each clock */
+ CLOCK_MAX_MUX = 8 /* number of source options for each clock */
};
-/*
- * Clock source mux for each clock type. This just converts our enum into
- * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
- * is special as it has 5 sources. Since it also has a different number of
- * bits in its register for the source, we just handle it with a special
- * case in the code.
- */
-#define CLK(x) CLOCK_ID_ ## x
-static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
- { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
- { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
- { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
+enum {
+ MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
+ MASK_BITS_31_29,
+ MASK_BITS_29_28,
};
/*
- * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
- * not in the header file since it is for purely internal use - we want
- * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
- * confusion bewteen PERIPH_ID_... and PERIPHC_...
- *
- * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
- * confusing.
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
*
- * Note to SOC vendors: perhaps define a unified numbering for peripherals and
- * use it for reset, clock enable, clock source/divider and even pinmuxing
- * if you can.
+ * Note:
+ * The extra column in each clock source array is used to store the mask
+ * bits in its register for the source.
*/
-enum periphc_internal_id {
- /* 0x00 */
- PERIPHC_I2S1,
- PERIPHC_I2S2,
- PERIPHC_SPDIF_OUT,
- PERIPHC_SPDIF_IN,
- PERIPHC_PWM,
- PERIPHC_SPI1,
- PERIPHC_SPI2,
- PERIPHC_SPI3,
-
- /* 0x08 */
- PERIPHC_XIO,
- PERIPHC_I2C1,
- PERIPHC_DVC_I2C,
- PERIPHC_TWC,
- PERIPHC_0c,
- PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
- PERIPHC_DISP1,
- PERIPHC_DISP2,
-
- /* 0x10 */
- PERIPHC_CVE,
- PERIPHC_IDE0,
- PERIPHC_VI,
- PERIPHC_1c,
- PERIPHC_SDMMC1,
- PERIPHC_SDMMC2,
- PERIPHC_G3D,
- PERIPHC_G2D,
-
- /* 0x18 */
- PERIPHC_NDFLASH,
- PERIPHC_SDMMC4,
- PERIPHC_VFIR,
- PERIPHC_EPP,
- PERIPHC_MPE,
- PERIPHC_MIPI,
- PERIPHC_UART1,
- PERIPHC_UART2,
-
- /* 0x20 */
- PERIPHC_HOST1X,
- PERIPHC_21,
- PERIPHC_TVO,
- PERIPHC_HDMI,
- PERIPHC_24,
- PERIPHC_TVDAC,
- PERIPHC_I2C2,
- PERIPHC_EMC,
-
- /* 0x28 */
- PERIPHC_UART3,
- PERIPHC_29,
- PERIPHC_VI_SENSOR,
- PERIPHC_2b,
- PERIPHC_2c,
- PERIPHC_SPI4,
- PERIPHC_I2C3,
- PERIPHC_SDMMC3,
-
- /* 0x30 */
- PERIPHC_UART4,
- PERIPHC_UART5,
- PERIPHC_VDE,
- PERIPHC_OWR,
- PERIPHC_NOR,
- PERIPHC_CSITE,
-
- PERIPHC_COUNT,
-
- PERIPHC_NONE = -1,
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+ { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
+ CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
+ CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_29_28}
};
/* return 1 if a periphc_internal_id is in range */
@@ -207,24 +146,24 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
- TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
- TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
/* 0x08 */
- TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
+ TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
/* 0x10 */
TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
@@ -246,10 +185,10 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
+ TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
/* 0x28 */
@@ -258,8 +197,8 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
/* 0x30 */
@@ -269,6 +208,43 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+
+ /* 0x38h */
+ TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCM),
+ TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
+
+ /* 0x40 */
+ TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCM),
+ TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+ /* 0x48 */
+ TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+
+ /* 0x50 */
+ TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
};
/*
@@ -284,15 +260,15 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
/* Low word: 31:0 */
NONE(CPU),
- NONE(RESERVED1),
- NONE(RESERVED2),
- NONE(AC97),
- NONE(RTC),
+ NONE(COP),
+ NONE(TRIGSYS),
+ NONE(RESERVED3),
+ NONE(RESERVED4),
NONE(TMR),
PERIPHC_UART1,
PERIPHC_UART2, /* and vfir 0x68 */
- /* 0x08 */
+ /* 8 */
NONE(GPIO),
PERIPHC_SDMMC2,
NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
@@ -302,8 +278,8 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
PERIPHC_SDMMC1,
PERIPHC_SDMMC4,
- /* 0x10 */
- PERIPHC_TWC,
+ /* 16 */
+ NONE(RESERVED16),
PERIPHC_PWM,
PERIPHC_I2S2,
PERIPHC_EPP,
@@ -312,14 +288,14 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
NONE(USBD),
NONE(ISP),
- /* 0x18 */
+ /* 24 */
PERIPHC_G3D,
- PERIPHC_IDE0,
+ NONE(RESERVED25),
PERIPHC_DISP2,
PERIPHC_DISP1,
PERIPHC_HOST1X,
NONE(VCP),
- NONE(RESERVED30),
+ PERIPHC_I2S0,
NONE(CACHE2),
/* Middle word: 63:32 */
@@ -327,32 +303,32 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
NONE(AHBDMA),
NONE(APBDMA),
NONE(RESERVED35),
- NONE(KBC),
+ NONE(RESERVED36),
NONE(STAT_MON),
- NONE(PMC),
- NONE(FUSE),
+ NONE(RESERVED38),
+ NONE(RESERVED39),
- /* 0x28 */
+ /* 40 */
NONE(KFUSE),
NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
PERIPHC_NOR,
- PERIPHC_SPI1,
- PERIPHC_SPI2,
- PERIPHC_XIO,
- PERIPHC_SPI3,
+ NONE(RESERVED43),
+ PERIPHC_SBC2,
+ NONE(RESERVED45),
+ PERIPHC_SBC3,
PERIPHC_DVC_I2C,
- /* 0x30 */
+ /* 48 */
NONE(DSI),
PERIPHC_TVO, /* also CVE 0x40 */
PERIPHC_MIPI,
PERIPHC_HDMI,
- PERIPHC_CSITE,
+ NONE(CSI),
PERIPHC_TVDAC,
PERIPHC_I2C2,
PERIPHC_UART3,
- /* 0x38 */
+ /* 56 */
NONE(RESERVED56),
PERIPHC_EMC,
NONE(USB2),
@@ -363,47 +339,104 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
NONE(BSEV),
/* Upper word 95:64 */
- NONE(SPEEDO),
+ PERIPHC_SPEEDO,
PERIPHC_UART4,
PERIPHC_UART5,
PERIPHC_I2C3,
- PERIPHC_SPI4,
+ PERIPHC_SBC4,
PERIPHC_SDMMC3,
NONE(PCIE),
PERIPHC_OWR,
- /* 0x48 */
+ /* 72 */
NONE(AFI),
- NONE(CORESIGHT),
- NONE(RESERVED74),
+ PERIPHC_CSITE,
+ NONE(PCIEXCLK),
NONE(AVPUCQ),
NONE(RESERVED76),
NONE(RESERVED77),
NONE(RESERVED78),
- NONE(RESERVED79),
+ NONE(DTV),
- /* 0x50 */
- NONE(RESERVED80),
- NONE(RESERVED81),
- NONE(RESERVED82),
+ /* 80 */
+ PERIPHC_NANDSPEED,
+ PERIPHC_I2CSLOW,
+ NONE(DSIB),
NONE(RESERVED83),
NONE(IRAMA),
NONE(IRAMB),
NONE(IRAMC),
NONE(IRAMD),
- /* 0x58 */
+ /* 88 */
NONE(CRAM2),
-};
-
-/* number of clock outputs of a PLL */
-static const u8 pll_num_clkouts[] = {
- 1, /* PLLC */
- 1, /* PLLM */
- 4, /* PLLP */
- 1, /* PLLA */
- 0, /* PLLU */
- 0, /* PLLD */
+ NONE(RESERVED89),
+ NONE(MDOUBLER),
+ NONE(RESERVED91),
+ NONE(SUSOUT),
+ NONE(RESERVED93),
+ NONE(RESERVED94),
+ NONE(RESERVED95),
+
+ /* V word: 31:0 */
+ NONE(CPUG),
+ NONE(CPULP),
+ PERIPHC_G3D2,
+ PERIPHC_MSELECT,
+ PERIPHC_TSENSOR,
+ PERIPHC_I2S3,
+ PERIPHC_I2S4,
+ PERIPHC_I2C4,
+
+ /* 08 */
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+ PERIPHC_AUDIO,
+ NONE(APBIF),
+ PERIPHC_DAM0,
+ PERIPHC_DAM1,
+ PERIPHC_DAM2,
+ PERIPHC_HDA2CODEC2X,
+
+ /* 16 */
+ NONE(ATOMICS),
+ NONE(RESERVED17),
+ NONE(RESERVED18),
+ NONE(RESERVED19),
+ NONE(RESERVED20),
+ NONE(RESERVED21),
+ NONE(RESERVED22),
+ PERIPHC_ACTMON,
+
+ /* 24 */
+ NONE(RESERVED24),
+ NONE(RESERVED25),
+ NONE(RESERVED26),
+ NONE(RESERVED27),
+ PERIPHC_SATA,
+ PERIPHC_HDA,
+ NONE(RESERVED30),
+ NONE(RESERVED31),
+
+ /* W word: 31:0 */
+ NONE(HDA2HDMICODEC),
+ NONE(SATACOLD),
+ NONE(RESERVED0_PCIERX0),
+ NONE(RESERVED1_PCIERX1),
+ NONE(RESERVED2_PCIERX2),
+ NONE(RESERVED3_PCIERX3),
+ NONE(RESERVED4_PCIERX4),
+ NONE(RESERVED5_PCIERX5),
+
+ /* 40 */
+ NONE(CEC),
+ NONE(RESERVED6_PCIE2),
+ NONE(RESERVED7_EMC),
+ NONE(RESERVED8_HDMI),
+ NONE(RESERVED9_SATA),
+ NONE(RESERVED10_MIPI),
+ NONE(EX_RESERVED46),
+ NONE(EX_RESERVED47),
};
/*
@@ -458,7 +491,6 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
data = readl(&pll->pll_misc);
*cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
*lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
-
return 0;
}
@@ -491,37 +523,6 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
}
-/* return 1 if a peripheral ID is in range and valid */
-static int clock_periph_id_isvalid(enum periph_id id)
-{
- if (id < PERIPH_ID_FIRST || id >= PERIPH_ID_COUNT)
- printf("Peripheral id %d out of range\n", id);
- else {
- switch (id) {
- case PERIPH_ID_RESERVED1:
- case PERIPH_ID_RESERVED2:
- case PERIPH_ID_RESERVED30:
- case PERIPH_ID_RESERVED35:
- case PERIPH_ID_RESERVED56:
- case PERIPH_ID_RESERVED74:
- case PERIPH_ID_RESERVED76:
- case PERIPH_ID_RESERVED77:
- case PERIPH_ID_RESERVED78:
- case PERIPH_ID_RESERVED79:
- case PERIPH_ID_RESERVED80:
- case PERIPH_ID_RESERVED81:
- case PERIPH_ID_RESERVED82:
- case PERIPH_ID_RESERVED83:
- case PERIPH_ID_RESERVED91:
- printf("Peripheral id %d is reserved\n", id);
- break;
- default:
- return 1;
- }
- }
- return 0;
-}
-
/* Returns a pointer to the clock source register for a peripheral */
static u32 *get_periph_source_reg(enum periph_id periph_id)
{
@@ -529,10 +530,18 @@ static u32 *get_periph_source_reg(enum periph_id periph_id)
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
enum periphc_internal_id internal_id;
- assert(clock_periph_id_isvalid(periph_id));
+ /* Coresight is a special case */
+ if (periph_id == PERIPH_ID_CSI)
+ return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+ assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
internal_id = periph_id_to_internal_id[periph_id];
assert(internal_id != -1);
- return &clkrst->crc_clk_src[internal_id];
+ if (internal_id >= PERIPHC_VW_FIRST) {
+ internal_id -= PERIPHC_VW_FIRST;
+ return &clkrst->crc_clk_src_vw[internal_id];
+ } else
+ return &clkrst->crc_clk_src[internal_id];
}
void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
@@ -614,34 +623,6 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
}
-int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
-{
- struct clk_pll *pll = get_pll(clkid);
- int data = 0, div = 0, offset = 0;
-
- if (!clock_id_is_pll(clkid))
- return -1;
-
- if (pllout + 1 > pll_num_clkouts[clkid])
- return -1;
-
- div = clk_get_divider(8, pll_rate[clkid], rate);
-
- if (div < 0)
- return -1;
-
- /* out2 and out4 are in the high part of the register */
- if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
- offset = 16;
-
- data = (div << PLL_OUT_RATIO_SHIFT) |
- PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
- clrsetbits_le32(&pll->pll_out[pllout >> 1],
- PLL_OUT_RATIO_MASK << offset, data << offset);
-
- return 0;
-}
-
/**
* Find the best available 7.1 format divisor given a parent clock rate and
* required child clock rate. This function assumes that a second-stage
@@ -710,33 +691,12 @@ static int get_periph_clock_source(enum periph_id periph_id,
type = clock_periph_type[internal_id];
assert(clock_type_id_isvalid(type));
- /*
- * Special cases here for the clock with a 4-bit source mux and I2C
- * with its 16-bit divisor
- */
- if (type == CLOCK_TYPE_PCXTS)
- *mux_bits = 4;
- else
- *mux_bits = 2;
- if (type == CLOCK_TYPE_PCMT16)
- *divider_bits = 16;
- else
- *divider_bits = 8;
+ *mux_bits = clock_source[type][CLOCK_MAX_MUX];
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
return mux;
- /*
- * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
- * which is not in our table. If not, then they are asking for a
- * source which this peripheral can't access through its mux.
- */
- assert(type == CLOCK_TYPE_PCXTS);
- assert(parent == CLOCK_ID_SFROM32KHZ);
- if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
- return 4; /* mux value for this clock */
-
/* if we get here, either us or the caller has made a mistake */
printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
parent);
@@ -780,8 +740,8 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
enum clock_id parent, unsigned rate, int *extra_div)
{
unsigned effective_rate;
- int mux_bits, divider_bits, source;
- int divider;
+ int mux_bits, source;
+ int divider, divider_bits = 0;
/* work out the source clock and set it */
source = get_periph_clock_source(periph_id, parent, &mux_bits,
@@ -829,11 +789,15 @@ void clock_set_enable(enum periph_id periph_id, int enable)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+ u32 *clk;
u32 reg;
/* Enable/disable the clock to this peripheral */
assert(clock_periph_id_isvalid(periph_id));
+ if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+ clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+ else
+ clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
reg = readl(clk);
if (enable)
reg |= PERIPH_MASK(periph_id);
@@ -856,11 +820,15 @@ void reset_set_enable(enum periph_id periph_id, int enable)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+ u32 *reset;
u32 reg;
/* Enable/disable reset to the peripheral */
assert(clock_periph_id_isvalid(periph_id));
+ if (periph_id < PERIPH_ID_VW_FIRST)
+ reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+ else
+ reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
reg = readl(reset);
if (enable)
reg |= PERIPH_MASK(periph_id);
@@ -887,8 +855,8 @@ void reset_cmplx_set_enable(int cpu, int which, int reset)
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 mask;
- /* Form the mask, which depends on the cpu chosen. Tegra20 has 2 */
- assert(cpu >= 0 && cpu < 2);
+ /* Form the mask, which depends on the cpu chosen. Tegra3 has 4 */
+ assert(cpu >= 0 && cpu < 4);
mask = which << cpu;
/* either enable or disable those reset for that CPU */
@@ -1075,31 +1043,29 @@ int clock_verify(void)
printf("Warning: PLLP %x is not correct\n", reg);
return -1;
}
- debug("PLLX %x is correct\n", reg);
+ debug("PLLP %x is correct\n", reg);
return 0;
}
void clock_early_init(void)
{
/*
- * PLLP output frequency set to 216MHz
- * PLLC output frequency set to 600Mhz
- *
- * TODO: Can we calculate these values instead of hard-coding?
+ * PLLP output frequency set to 408Mhz
+ * PLLC output frequency set to 228Mhz
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
break;
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
break;
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
break;
case CLOCK_OSC_FREQ_19_2:
diff --git a/arch/arm/cpu/tegra30-common/funcmux.c b/arch/arm/cpu/tegra30-common/funcmux.c
new file mode 100644
index 0000000..e24c57e
--- /dev/null
+++ b/arch/arm/cpu/tegra30-common/funcmux.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+ int bad_config = config != FUNCMUX_DEFAULT;
+
+ switch (id) {
+ case PERIPH_ID_UART1:
+ switch (config) {
+ case FUNCMUX_UART1_ULPI:
+ pinmux_set_func(PINGRP_ULPI_DATA0, PMUX_FUNC_UARTA);
+ pinmux_set_func(PINGRP_ULPI_DATA1, PMUX_FUNC_UARTA);
+ pinmux_set_func(PINGRP_ULPI_DATA2, PMUX_FUNC_UARTA);
+ pinmux_set_func(PINGRP_ULPI_DATA3, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PINGRP_ULPI_DATA0);
+ pinmux_tristate_disable(PINGRP_ULPI_DATA1);
+ pinmux_tristate_disable(PINGRP_ULPI_DATA2);
+ pinmux_tristate_disable(PINGRP_ULPI_DATA3);
+ break;
+ }
+ break;
+
+ /* Add other periph IDs here as needed */
+
+ default:
+ debug("%s: invalid periph_id %d", __func__, id);
+ return -1;
+ }
+
+ if (bad_config) {
+ debug("%s: invalid config %d for periph_id %d", __func__,
+ config, id);
+ return -1;
+ }
+ return 0;
+}
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
new file mode 100644
index 0000000..122665f
--- /dev/null
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -0,0 +1,506 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 pin multiplexing functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+
+struct tegra_pingroup_desc {
+ const char *name;
+ enum pmux_func funcs[4];
+ enum pmux_func func_safe;
+ enum pmux_vddio vddio;
+ enum pmux_pin_io io;
+};
+
+#define PMUX_MUXCTL_SHIFT 0
+#define PMUX_PULL_SHIFT 2
+#define PMUX_TRISTATE_SHIFT 4
+#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
+#define PMUX_IO_SHIFT 5
+#define PMUX_OD_SHIFT 6
+#define PMUX_LOCK_SHIFT 7
+#define PMUX_IO_RESET_SHIFT 8
+
+/* Convenient macro for defining pin group properties */
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
+ { \
+ .vddio = PMUX_VDDIO_ ## vdd, \
+ .funcs = { \
+ PMUX_FUNC_ ## f0, \
+ PMUX_FUNC_ ## f1, \
+ PMUX_FUNC_ ## f2, \
+ PMUX_FUNC_ ## f3, \
+ }, \
+ .func_safe = PMUX_FUNC_RSVD1, \
+ .io = PMUX_PIN_ ## iod, \
+ }
+
+/* Input and output pins */
+#define PINI(pg_name, vdd, f0, f1, f2, f3) \
+ PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
+#define PINO(pg_name, vdd, f0, f1, f2, f3) \
+ PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+ /* NAME VDD f0 f1 f2 f3 */
+ PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI),
+ PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI),
+ PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI),
+ PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI),
+ PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB),
+ PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB),
+ PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB),
+ PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB),
+ PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
+ PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
+ PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
+ PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
+ PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
+ PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
+ PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
+ PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
+ PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP),
+ PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4),
+ PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP),
+ PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP),
+ PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4),
+ PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP),
+ PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP),
+ PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4),
+ PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4),
+ PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
+ PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
+ PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
+ PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4),
+ PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4),
+ PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4),
+ PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4),
+ PINI(VI_MCLK, VI, VI, VI, VI, VI),
+ PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4),
+ PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4),
+ PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
+ PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
+ PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4),
+ PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4),
+ PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4),
+ PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4),
+ PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4),
+ PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4),
+ PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4),
+ PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
+ PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
+ PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4),
+ PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4),
+ PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4),
+ PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4),
+ PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
+ PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
+ PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
+ PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV),
+ PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV),
+ PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
+ PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA),
+ PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT),
+ PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4),
+ PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4),
+ PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4),
+ PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4),
+ PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT),
+ PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV),
+ PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV),
+ PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4),
+ PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
+ PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4),
+ PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4),
+ PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4),
+ PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4),
+ PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
+ PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
+ PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
+ PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
+ PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4),
+ PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4),
+ PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4),
+ PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4),
+ PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4),
+ PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4),
+ PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
+ PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
+ PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4),
+ PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4),
+ PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4),
+ PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4),
+ PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4),
+ PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4),
+ PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
+ PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
+ PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4),
+ PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4),
+ PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4),
+ PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4),
+ PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4),
+ PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR),
+ PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST),
+ PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST),
+ PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4),
+ PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4),
+ PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4),
+ PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4),
+ PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO),
+ PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO),
+ PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4),
+ PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
+ PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
+ PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4),
+ PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
+ PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4),
+ PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2),
+ PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2),
+ PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2),
+ PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2),
+ PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4),
+ PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
+ PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2),
+ PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2),
+ PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI),
+ PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI),
+ PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI),
+ PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI),
+ PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI),
+ PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI),
+ PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI),
+ PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI),
+ PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
+ PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
+ PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
+ PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4),
+ PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
+ PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
+ PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3),
+ PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2),
+ PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
+ PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
+ PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3),
+ PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3),
+ PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2),
+ PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2),
+ PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
+ PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
+ PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
+};
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *tri = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin */
+ assert(pmux_pingrp_isvalid(pin));
+
+ reg = readl(tri);
+ if (enable)
+ reg |= PMUX_TRISTATE_MASK;
+ else
+ reg &= ~PMUX_TRISTATE_MASK;
+ writel(reg, tri);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, 1);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, 0);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pull = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and pupd */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_pupd_isvalid(pupd));
+
+ reg = readl(pull);
+ reg &= ~(0x3 << PMUX_PULL_SHIFT);
+ reg |= (pupd << PMUX_PULL_SHIFT);
+ writel(reg, pull);
+}
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *muxctl = &pmt->pmt_ctl[pin];
+ int i, mux = -1;
+ u32 reg;
+
+ /* Error check on pin and func */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_func_isvalid(func));
+
+ /* Handle special values */
+ if (func == PMUX_FUNC_SAFE)
+ func = tegra_soc_pingroups[pin].func_safe;
+
+ if (func & PMUX_FUNC_RSVD1) {
+ mux = func & 0x3;
+ } else {
+ /* Search for the appropriate function */
+ for (i = 0; i < 4; i++) {
+ if (tegra_soc_pingroups[pin].funcs[i] == func) {
+ mux = i;
+ break;
+ }
+ }
+ }
+ assert(mux != -1);
+
+ reg = readl(muxctl);
+ reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
+ reg |= (mux << PMUX_MUXCTL_SHIFT);
+ writel(reg, muxctl);
+
+}
+
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_io = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and io */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_io_isvalid(io));
+
+ reg = readl(pin_io);
+ reg &= ~(0x1 << PMUX_IO_SHIFT);
+ reg |= (io & 0x1) << PMUX_IO_SHIFT;
+ writel(reg, pin_io);
+}
+
+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_lock = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and lock */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_lock_isvalid(lock));
+
+ if (lock == PMUX_PIN_LOCK_DEFAULT)
+ return 0;
+
+ reg = readl(pin_lock);
+ reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+ if (lock == PMUX_PIN_LOCK_ENABLE)
+ reg |= (0x1 << PMUX_LOCK_SHIFT);
+ else {
+ /* lock == DISABLE, which isn't possible */
+ printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
+ __func__, lock);
+ }
+ writel(reg, pin_lock);
+
+ return 0;
+}
+
+static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_od = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and od */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_od_isvalid(od));
+
+ if (od == PMUX_PIN_OD_DEFAULT)
+ return 0;
+
+ reg = readl(pin_od);
+ reg &= ~(0x1 << PMUX_OD_SHIFT);
+ if (od == PMUX_PIN_OD_ENABLE)
+ reg |= (0x1 << PMUX_OD_SHIFT);
+ writel(reg, pin_od);
+
+ return 0;
+}
+
+static int pinmux_set_ioreset(enum pmux_pingrp pin,
+ enum pmux_pin_ioreset ioreset)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_ioreset = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and ioreset */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_ioreset_isvalid(ioreset));
+
+ if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+ return 0;
+
+ reg = readl(pin_ioreset);
+ reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
+ if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+ reg |= (0x1 << PMUX_IO_RESET_SHIFT);
+ writel(reg, pin_ioreset);
+
+ return 0;
+}
+
+void pinmux_config_pingroup(struct pingroup_config *config)
+{
+ enum pmux_pingrp pin = config->pingroup;
+
+ pinmux_set_func(pin, config->func);
+ pinmux_set_pullupdown(pin, config->pull);
+ pinmux_set_tristate(pin, config->tristate);
+ pinmux_set_io(pin, config->io);
+ pinmux_set_lock(pin, config->lock);
+ pinmux_set_od(pin, config->od);
+ pinmux_set_ioreset(pin, config->ioreset);
+}
+
+void pinmux_config_table(struct pingroup_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ pinmux_config_pingroup(&config[i]);
+}
diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h
index 70d94c5..73dfd39 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -23,67 +23,27 @@
#include <asm/types.h>
/* Stabilization delays, in usec */
-#define PLL_STABILIZATION_DELAY (300)
+#define PLL_STABILIZATION_DELAY (300)
#define IO_STABILIZATION_DELAY (1000)
-#define NVBL_PLLP_KHZ (216000)
-
#define PLLX_ENABLED (1 << 30)
#define CCLK_BURST_POLICY 0x20008888
#define SUPER_CCLK_DIVIDER 0x80000000
/* Calculate clock fractional divider value from ref and target frequencies */
-#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
+#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
/* Calculate clock frequency value from reference and clock divider value */
-#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
+#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
/* AVP/CPU ID */
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
-#define PG_UP_TAG_0 0x0
+#define PG_UP_TAG_0 0x0
#define CORESIGHT_UNLOCK 0xC5ACCE55;
-/* AP20-Specific Base Addresses */
-
-/* AP20 Base physical address of SDRAM. */
-#define AP20_BASE_PA_SDRAM 0x00000000
-/* AP20 Base physical address of internal SRAM. */
-#define AP20_BASE_PA_SRAM 0x40000000
-/* AP20 Size of internal SRAM (256KB). */
-#define AP20_BASE_PA_SRAM_SIZE 0x00040000
-/* AP20 Base physical address of flash. */
-#define AP20_BASE_PA_NOR_FLASH 0xD0000000
-/* AP20 Base physical address of boot information table. */
-#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
-
-/*
- * Super-temporary stacks for EXTREMELY early startup. The values chosen for
- * these addresses must be valid on ALL SOCs because this value is used before
- * we are able to differentiate between the SOC types.
- *
- * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
- * stack is placed below the AVP stack. Once the CPU stack has been moved,
- * the AVP is free to use the IRAM the CPU stack previously occupied if
- * it should need to do so.
- *
- * NOTE: In multi-processor CPU complex configurations, each processor will have
- * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
- * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
- * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
- * CPU.
- */
-
-/* Common AVP early boot stack limit */
-#define AVP_EARLY_BOOT_STACK_LIMIT \
- (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
-/* Common AVP early boot stack size */
-#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
-/* Common CPU early boot stack limit */
-#define CPU_EARLY_BOOT_STACK_LIMIT \
- (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
-/* Common CPU early boot stack size */
-#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
+/* AP base physical address of internal SRAM */
+#define NV_PA_BASE_SRAM 0x40000000
#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 4/7] Tegra30: Add common CPU (shared) files
2012-12-11 23:34 ` [U-Boot] [PATCH V3 4/7] Tegra30: Add common CPU (shared) files Tom Warren
@ 2012-12-12 0:45 ` Allen Martin
2012-12-12 16:14 ` Tom Warren
2012-12-12 22:09 ` Stephen Warren
1 sibling, 1 reply; 31+ messages in thread
From: Allen Martin @ 2012-12-12 0:45 UTC (permalink / raw)
To: u-boot
On Tue, Dec 11, 2012 at 03:34:15PM -0800, Tom Warren wrote:
> These files are used by both SPL and main U-Boot.
> Also made minor changes to shared Tegra code to support
> T30 differences.
>
> Signed-off-by: Tom Warren <twarren@nvidia.com>
> ---
> V2:
> * Differentiate between T20 and T30 in ODMDATA and query_sdram_size.
> * Fix numerous func entries in pingroup table as per Stephen.
> * Added warning about LOCK bit in pinmux_set_lock.
> V3:
> * Always program PLLP to 408MHz
> * Use generic SoC string in print_cpuinfo
>
> arch/arm/cpu/tegra-common/ap.c | 14 +-
> arch/arm/cpu/tegra-common/board.c | 41 ++-
> arch/arm/cpu/tegra-common/sys_info.c | 16 +-
> arch/arm/cpu/tegra20-common/warmboot.c | 2 +-
> .../{arm720t/tegra30 => tegra30-common}/Makefile | 11 +-
> .../cpu/{tegra20-common => tegra30-common}/clock.c | 516 +++++++++-----------
> arch/arm/cpu/tegra30-common/funcmux.c | 57 +++
> arch/arm/cpu/tegra30-common/pinmux.c | 506 +++++++++++++++++++
> arch/arm/include/asm/arch-tegra/ap.h | 52 +--
> 9 files changed, 880 insertions(+), 335 deletions(-)
> copy arch/arm/cpu/{arm720t/tegra30 => tegra30-common}/Makefile (80%)
> copy arch/arm/cpu/{tegra20-common => tegra30-common}/clock.c (74%)
> create mode 100644 arch/arm/cpu/tegra30-common/funcmux.c
> create mode 100644 arch/arm/cpu/tegra30-common/pinmux.c
>
> diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
> index c4eb137..aebe29e 100644
> --- a/arch/arm/cpu/tegra-common/ap.c
> +++ b/arch/arm/cpu/tegra-common/ap.c
> @@ -20,10 +20,14 @@
> * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> * MA 02111-1307 USA
> */
> +
> +/* Tegra AP (Application Processor) code */
> +
> #include <common.h>
> #include <asm/io.h>
> #include <asm/arch/gp_padctrl.h>
> #include <asm/arch-tegra/ap.h>
> +#include <asm/arch-tegra/clock.h>
> #include <asm/arch-tegra/fuse.h>
> #include <asm/arch-tegra/pmc.h>
> #include <asm/arch-tegra/scu.h>
> @@ -58,6 +62,12 @@ int tegra_get_chip_type(void)
> return TEGRA_SOC_T25;
> }
> break;
> + case CHIPID_TEGRA30:
> + switch (tegra_sku_id) {
> + case SKU_ID_T30:
> + return TEGRA_SOC_T30;
> + }
> + break;
> }
> /* unknown sku id */
> return TEGRA_SOC_UNKNOWN;
> @@ -93,7 +103,7 @@ static u32 get_odmdata(void)
>
> u32 bct_start, odmdata;
>
> - bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
> + bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
> odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
>
> return odmdata;
> @@ -127,5 +137,5 @@ void s_init(void)
> "orr r0, r0, #0x41\n"
> "mcr p15, 0, r0, c1, c0, 1\n");
>
> - /* FIXME: should have ap20's L2 disabled too? */
> + /* FIXME: should have SoC's L2 disabled too? */
We should probably just remove this README, I don't believe it applies
any more.
> }
> diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
> index b2e10c6..af1879c 100644
> --- a/arch/arm/cpu/tegra-common/board.c
> +++ b/arch/arm/cpu/tegra-common/board.c
> @@ -54,16 +54,37 @@ unsigned int query_sdram_size(void)
> reg = readl(&pmc->pmc_scratch20);
> debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
>
> - /* bits 31:28 in OdmData are used for RAM size */
> +#if defined(CONFIG_TEGRA20)
> + /* bits 30:28 in OdmData are used for RAM size on T20 */
> + reg &= 0x70000000;
> +
> switch ((reg) >> 28) {
> case 1:
> return 0x10000000; /* 256 MB */
> + case 0:
> case 2:
> default:
> return 0x20000000; /* 512 MB */
> case 3:
> return 0x40000000; /* 1GB */
> }
> +#else /* Tegra30 */
> + /* bits 31:28 in OdmData are used for RAM size on T30 */
> + switch ((reg) >> 28) {
> + case 0:
> + case 1:
> + default:
> + return 0x10000000; /* 256 MB */
> + case 2:
> + return 0x20000000; /* 512 MB */
> + case 3:
> + return 0x30000000; /* 768 MB */
> + case 4:
> + return 0x40000000; /* 1GB */
> + case 8:
> + return 0x7ff00000; /* 2GB - 1MB */
> + }
> +#endif
> }
>
> int dram_init(void)
> @@ -82,19 +103,27 @@ int checkboard(void)
> #endif /* CONFIG_DISPLAY_BOARDINFO */
>
> static int uart_configs[] = {
> -#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
> +#if defined(CONFIG_TEGRA20)
> + #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
> FUNCMUX_UART1_UAA_UAB,
> -#elif defined(CONFIG_TEGRA_UARTA_GPU)
> + #elif defined(CONFIG_TEGRA_UARTA_GPU)
> FUNCMUX_UART1_GPU,
> -#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
> + #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
> FUNCMUX_UART1_SDIO1,
> -#else
> + #else
> FUNCMUX_UART1_IRRX_IRTX,
> -#endif
> + #endif
> FUNCMUX_UART2_IRDA,
> -1,
> FUNCMUX_UART4_GMC,
> -1,
> +#else /* Tegra30 */
> + FUNCMUX_UART1_ULPI, /* UARTA */
> + -1,
> + -1,
> + -1,
> + -1,
Shouldn't there be entries for other UART selections here?
> +#endif
> };
>
> /**
> diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/cpu/tegra-common/sys_info.c
> index 1a0bb56..4632f15 100644
> --- a/arch/arm/cpu/tegra-common/sys_info.c
> +++ b/arch/arm/cpu/tegra-common/sys_info.c
> @@ -22,12 +22,26 @@
> */
>
> #include <common.h>
> +#include <linux/ctype.h>
>
> #ifdef CONFIG_DISPLAY_CPUINFO
> +void upstring(char *s)
> +{
> + while (*s) {
> + *s = toupper(*s);
> + s++;
> + }
> +}
> +
> /* Print CPU information */
> int print_cpuinfo(void)
> {
> - puts("TEGRA20\n");
> + char soc_name[10];
> +
> + strncpy(soc_name, CONFIG_SYS_SOC, 10);
> + upstring(soc_name);
> + puts(soc_name);
> + puts("\n");
>
> /* TBD: Add printf of major/minor rev info, stepping, etc. */
> return 0;
> diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c
> index 157b9ab..0d472cf 100644
> --- a/arch/arm/cpu/tegra20-common/warmboot.c
> +++ b/arch/arm/cpu/tegra20-common/warmboot.c
> @@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
> * This is the place in SRAM where the SDRAM parameters are stored. There
> * are 4 blocks, one for each RAM code
> */
> -#define SDRAM_PARAMS_BASE (AP20_BASE_PA_SRAM + 0x188)
> +#define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
>
> /* TODO: If we later add support for the Misc GP controller, refactor this */
> union xm2cfga_reg {
> diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/tegra30-common/Makefile
> similarity index 80%
> copy from arch/arm/cpu/arm720t/tegra30/Makefile
> copy to arch/arm/cpu/tegra30-common/Makefile
> index bd96997..75fef32 100644
> --- a/arch/arm/cpu/arm720t/tegra30/Makefile
> +++ b/arch/arm/cpu/tegra30-common/Makefile
> @@ -19,12 +19,15 @@
>
> include $(TOPDIR)/config.mk
>
> -LIB = $(obj)lib$(SOC).o
> +# The AVP is ARMv4T architecture so we must use special compiler
> +# flags for any startup files it might use.
The SPL build should make this transparent to this Makefile.
>
> -COBJS-y += cpu.o
> +LIB = $(obj)lib$(SOC)-common.o
>
> -SRCS := $(COBJS-y:.o=.c)
> -OBJS := $(addprefix $(obj),$(COBJS-y))
> +COBJS-y += clock.o funcmux.o pinmux.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
> +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
>
> all: $(obj).depend $(LIB)
>
> diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c
> similarity index 74%
> copy from arch/arm/cpu/tegra20-common/clock.c
> copy to arch/arm/cpu/tegra30-common/clock.c
> index 12987a6..5db9d20 100644
> --- a/arch/arm/cpu/tegra20-common/clock.c
> +++ b/arch/arm/cpu/tegra30-common/clock.c
> @@ -1,25 +1,20 @@
> /*
> - * Copyright (c) 2011 The Chromium OS Authors.
> - * See file CREDITS for list of people who contributed to this
> - * project.
> + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
> *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> *
> * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> -/* Tegra20 Clock control functions */
> +/* Tegra30 Clock control functions */
>
> #include <common.h>
> #include <asm/io.h>
> @@ -49,7 +44,7 @@ static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
> };
>
> /*
> - * Clock types that we can use as a source. The Tegra20 has muxes for the
> + * Clock types that we can use as a source. The Tegra3 has muxes for the
> * peripheral clocks, and in most cases there are four options for the clock
> * source. This gives us a clock 'type' and exploits what commonality exists
> * in the device.
> @@ -68,9 +63,11 @@ enum clock_type_id {
> CLOCK_TYPE_MCPT,
> CLOCK_TYPE_PCM,
> CLOCK_TYPE_PCMT,
> - CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
> - CLOCK_TYPE_PCXTS,
> CLOCK_TYPE_PDCT,
> + CLOCK_TYPE_ACPT,
> + CLOCK_TYPE_ASPTE,
> + CLOCK_TYPE_PMDACD2T,
> + CLOCK_TYPE_PCST,
>
> CLOCK_TYPE_COUNT,
> CLOCK_TYPE_NONE = -1, /* invalid clock type */
> @@ -83,113 +80,55 @@ enum clock_type_id {
> char pllp_valid = 1; /* PLLP is set up correctly */
>
> enum {
> - CLOCK_MAX_MUX = 4 /* number of source options for each clock */
> + CLOCK_MAX_MUX = 8 /* number of source options for each clock */
> };
>
> -/*
> - * Clock source mux for each clock type. This just converts our enum into
> - * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
> - * is special as it has 5 sources. Since it also has a different number of
> - * bits in its register for the source, we just handle it with a special
> - * case in the code.
> - */
> -#define CLK(x) CLOCK_ID_ ## x
> -static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
> - { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
> - { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
> - { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
> - { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
> - { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
> - { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
> - { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
> - { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
> +enum {
> + MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
> + MASK_BITS_31_29,
> + MASK_BITS_29_28,
> };
>
> /*
> - * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
> - * not in the header file since it is for purely internal use - we want
> - * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
> - * confusion bewteen PERIPH_ID_... and PERIPHC_...
> - *
> - * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
> - * confusing.
> + * Clock source mux for each clock type. This just converts our enum into
> + * a list of mux sources for use by the code.
> *
> - * Note to SOC vendors: perhaps define a unified numbering for peripherals and
> - * use it for reset, clock enable, clock source/divider and even pinmuxing
> - * if you can.
> + * Note:
> + * The extra column in each clock source array is used to store the mask
> + * bits in its register for the source.
> */
> -enum periphc_internal_id {
> - /* 0x00 */
> - PERIPHC_I2S1,
> - PERIPHC_I2S2,
> - PERIPHC_SPDIF_OUT,
> - PERIPHC_SPDIF_IN,
> - PERIPHC_PWM,
> - PERIPHC_SPI1,
> - PERIPHC_SPI2,
> - PERIPHC_SPI3,
> -
> - /* 0x08 */
> - PERIPHC_XIO,
> - PERIPHC_I2C1,
> - PERIPHC_DVC_I2C,
> - PERIPHC_TWC,
> - PERIPHC_0c,
> - PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
> - PERIPHC_DISP1,
> - PERIPHC_DISP2,
> -
> - /* 0x10 */
> - PERIPHC_CVE,
> - PERIPHC_IDE0,
> - PERIPHC_VI,
> - PERIPHC_1c,
> - PERIPHC_SDMMC1,
> - PERIPHC_SDMMC2,
> - PERIPHC_G3D,
> - PERIPHC_G2D,
> -
> - /* 0x18 */
> - PERIPHC_NDFLASH,
> - PERIPHC_SDMMC4,
> - PERIPHC_VFIR,
> - PERIPHC_EPP,
> - PERIPHC_MPE,
> - PERIPHC_MIPI,
> - PERIPHC_UART1,
> - PERIPHC_UART2,
> -
> - /* 0x20 */
> - PERIPHC_HOST1X,
> - PERIPHC_21,
> - PERIPHC_TVO,
> - PERIPHC_HDMI,
> - PERIPHC_24,
> - PERIPHC_TVDAC,
> - PERIPHC_I2C2,
> - PERIPHC_EMC,
> -
> - /* 0x28 */
> - PERIPHC_UART3,
> - PERIPHC_29,
> - PERIPHC_VI_SENSOR,
> - PERIPHC_2b,
> - PERIPHC_2c,
> - PERIPHC_SPI4,
> - PERIPHC_I2C3,
> - PERIPHC_SDMMC3,
> -
> - /* 0x30 */
> - PERIPHC_UART4,
> - PERIPHC_UART5,
> - PERIPHC_VDE,
> - PERIPHC_OWR,
> - PERIPHC_NOR,
> - PERIPHC_CSITE,
> -
> - PERIPHC_COUNT,
> -
> - PERIPHC_NONE = -1,
> +#define CLK(x) CLOCK_ID_ ## x
> +static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
> + { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
> + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
> + MASK_BITS_31_30},
> + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
> + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
> + MASK_BITS_31_30},
> + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
> + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
> + MASK_BITS_31_30},
> + { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
> + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
> + MASK_BITS_31_30},
> + { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
> + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
> + MASK_BITS_31_30},
> + { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
> + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
> + MASK_BITS_31_30},
> + { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
> + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
> + MASK_BITS_31_30},
> + { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
> + CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
> + MASK_BITS_31_29},
> + { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
> + CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
> + MASK_BITS_31_29},
> + { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
> + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
> + MASK_BITS_29_28}
> };
>
> /* return 1 if a periphc_internal_id is in range */
> @@ -207,24 +146,24 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
> TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
> TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
> TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
> - TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
> - TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
> - TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
> - TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST),
> + TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> + TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
>
> /* 0x08 */
> - TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
> - TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
> - TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
> - TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
> TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> - TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
> - TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
> - TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
> + TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> + TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> + TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
> + TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
>
> /* 0x10 */
> TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
> - TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
> TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
> @@ -246,10 +185,10 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
> TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
> TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
> - TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
> + TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
> TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
> - TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
> + TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT),
> TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
>
> /* 0x28 */
> @@ -258,8 +197,8 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
> TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
> TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> - TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
> - TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
> + TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT),
> TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
>
> /* 0x30 */
> @@ -269,6 +208,43 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
> TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
> TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
> TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
> + TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> +
> + /* 0x38h */
> + TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
> + TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCM),
> + TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
> + TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
> + TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
> +
> + /* 0x40 */
> + TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
> + TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> + TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
> + TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
> + TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
> + TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCM),
> + TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
> +
> + /* 0x48 */
> + TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
> + TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
> + TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
> + TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> + TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
> +
> + /* 0x50 */
> + TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
> + TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
> };
>
> /*
> @@ -284,15 +260,15 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
> static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
> /* Low word: 31:0 */
> NONE(CPU),
> - NONE(RESERVED1),
> - NONE(RESERVED2),
> - NONE(AC97),
> - NONE(RTC),
> + NONE(COP),
> + NONE(TRIGSYS),
> + NONE(RESERVED3),
> + NONE(RESERVED4),
> NONE(TMR),
> PERIPHC_UART1,
> PERIPHC_UART2, /* and vfir 0x68 */
>
> - /* 0x08 */
> + /* 8 */
> NONE(GPIO),
> PERIPHC_SDMMC2,
> NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
> @@ -302,8 +278,8 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
> PERIPHC_SDMMC1,
> PERIPHC_SDMMC4,
>
> - /* 0x10 */
> - PERIPHC_TWC,
> + /* 16 */
> + NONE(RESERVED16),
> PERIPHC_PWM,
> PERIPHC_I2S2,
> PERIPHC_EPP,
> @@ -312,14 +288,14 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
> NONE(USBD),
> NONE(ISP),
>
> - /* 0x18 */
> + /* 24 */
> PERIPHC_G3D,
> - PERIPHC_IDE0,
> + NONE(RESERVED25),
> PERIPHC_DISP2,
> PERIPHC_DISP1,
> PERIPHC_HOST1X,
> NONE(VCP),
> - NONE(RESERVED30),
> + PERIPHC_I2S0,
> NONE(CACHE2),
>
> /* Middle word: 63:32 */
> @@ -327,32 +303,32 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
> NONE(AHBDMA),
> NONE(APBDMA),
> NONE(RESERVED35),
> - NONE(KBC),
> + NONE(RESERVED36),
> NONE(STAT_MON),
> - NONE(PMC),
> - NONE(FUSE),
> + NONE(RESERVED38),
> + NONE(RESERVED39),
>
> - /* 0x28 */
> + /* 40 */
> NONE(KFUSE),
> NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
> PERIPHC_NOR,
> - PERIPHC_SPI1,
> - PERIPHC_SPI2,
> - PERIPHC_XIO,
> - PERIPHC_SPI3,
> + NONE(RESERVED43),
> + PERIPHC_SBC2,
> + NONE(RESERVED45),
> + PERIPHC_SBC3,
> PERIPHC_DVC_I2C,
>
> - /* 0x30 */
> + /* 48 */
> NONE(DSI),
> PERIPHC_TVO, /* also CVE 0x40 */
> PERIPHC_MIPI,
> PERIPHC_HDMI,
> - PERIPHC_CSITE,
> + NONE(CSI),
> PERIPHC_TVDAC,
> PERIPHC_I2C2,
> PERIPHC_UART3,
>
> - /* 0x38 */
> + /* 56 */
> NONE(RESERVED56),
> PERIPHC_EMC,
> NONE(USB2),
> @@ -363,47 +339,104 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
> NONE(BSEV),
>
> /* Upper word 95:64 */
> - NONE(SPEEDO),
> + PERIPHC_SPEEDO,
> PERIPHC_UART4,
> PERIPHC_UART5,
> PERIPHC_I2C3,
> - PERIPHC_SPI4,
> + PERIPHC_SBC4,
> PERIPHC_SDMMC3,
> NONE(PCIE),
> PERIPHC_OWR,
>
> - /* 0x48 */
> + /* 72 */
> NONE(AFI),
> - NONE(CORESIGHT),
> - NONE(RESERVED74),
> + PERIPHC_CSITE,
> + NONE(PCIEXCLK),
> NONE(AVPUCQ),
> NONE(RESERVED76),
> NONE(RESERVED77),
> NONE(RESERVED78),
> - NONE(RESERVED79),
> + NONE(DTV),
>
> - /* 0x50 */
> - NONE(RESERVED80),
> - NONE(RESERVED81),
> - NONE(RESERVED82),
> + /* 80 */
> + PERIPHC_NANDSPEED,
> + PERIPHC_I2CSLOW,
> + NONE(DSIB),
> NONE(RESERVED83),
> NONE(IRAMA),
> NONE(IRAMB),
> NONE(IRAMC),
> NONE(IRAMD),
>
> - /* 0x58 */
> + /* 88 */
> NONE(CRAM2),
> -};
> -
> -/* number of clock outputs of a PLL */
> -static const u8 pll_num_clkouts[] = {
> - 1, /* PLLC */
> - 1, /* PLLM */
> - 4, /* PLLP */
> - 1, /* PLLA */
> - 0, /* PLLU */
> - 0, /* PLLD */
> + NONE(RESERVED89),
> + NONE(MDOUBLER),
> + NONE(RESERVED91),
> + NONE(SUSOUT),
> + NONE(RESERVED93),
> + NONE(RESERVED94),
> + NONE(RESERVED95),
> +
> + /* V word: 31:0 */
> + NONE(CPUG),
> + NONE(CPULP),
> + PERIPHC_G3D2,
> + PERIPHC_MSELECT,
> + PERIPHC_TSENSOR,
> + PERIPHC_I2S3,
> + PERIPHC_I2S4,
> + PERIPHC_I2C4,
> +
> + /* 08 */
> + PERIPHC_SBC5,
> + PERIPHC_SBC6,
> + PERIPHC_AUDIO,
> + NONE(APBIF),
> + PERIPHC_DAM0,
> + PERIPHC_DAM1,
> + PERIPHC_DAM2,
> + PERIPHC_HDA2CODEC2X,
> +
> + /* 16 */
> + NONE(ATOMICS),
> + NONE(RESERVED17),
> + NONE(RESERVED18),
> + NONE(RESERVED19),
> + NONE(RESERVED20),
> + NONE(RESERVED21),
> + NONE(RESERVED22),
> + PERIPHC_ACTMON,
> +
> + /* 24 */
> + NONE(RESERVED24),
> + NONE(RESERVED25),
> + NONE(RESERVED26),
> + NONE(RESERVED27),
> + PERIPHC_SATA,
> + PERIPHC_HDA,
> + NONE(RESERVED30),
> + NONE(RESERVED31),
> +
> + /* W word: 31:0 */
> + NONE(HDA2HDMICODEC),
> + NONE(SATACOLD),
> + NONE(RESERVED0_PCIERX0),
> + NONE(RESERVED1_PCIERX1),
> + NONE(RESERVED2_PCIERX2),
> + NONE(RESERVED3_PCIERX3),
> + NONE(RESERVED4_PCIERX4),
> + NONE(RESERVED5_PCIERX5),
> +
> + /* 40 */
> + NONE(CEC),
> + NONE(RESERVED6_PCIE2),
> + NONE(RESERVED7_EMC),
> + NONE(RESERVED8_HDMI),
> + NONE(RESERVED9_SATA),
> + NONE(RESERVED10_MIPI),
> + NONE(EX_RESERVED46),
> + NONE(EX_RESERVED47),
> };
>
> /*
> @@ -458,7 +491,6 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
> data = readl(&pll->pll_misc);
> *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
> *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
> -
> return 0;
> }
>
> @@ -491,37 +523,6 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
> return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
> }
>
> -/* return 1 if a peripheral ID is in range and valid */
> -static int clock_periph_id_isvalid(enum periph_id id)
> -{
> - if (id < PERIPH_ID_FIRST || id >= PERIPH_ID_COUNT)
> - printf("Peripheral id %d out of range\n", id);
> - else {
> - switch (id) {
> - case PERIPH_ID_RESERVED1:
> - case PERIPH_ID_RESERVED2:
> - case PERIPH_ID_RESERVED30:
> - case PERIPH_ID_RESERVED35:
> - case PERIPH_ID_RESERVED56:
> - case PERIPH_ID_RESERVED74:
> - case PERIPH_ID_RESERVED76:
> - case PERIPH_ID_RESERVED77:
> - case PERIPH_ID_RESERVED78:
> - case PERIPH_ID_RESERVED79:
> - case PERIPH_ID_RESERVED80:
> - case PERIPH_ID_RESERVED81:
> - case PERIPH_ID_RESERVED82:
> - case PERIPH_ID_RESERVED83:
> - case PERIPH_ID_RESERVED91:
> - printf("Peripheral id %d is reserved\n", id);
> - break;
> - default:
> - return 1;
> - }
> - }
> - return 0;
> -}
> -
> /* Returns a pointer to the clock source register for a peripheral */
> static u32 *get_periph_source_reg(enum periph_id periph_id)
> {
> @@ -529,10 +530,18 @@ static u32 *get_periph_source_reg(enum periph_id periph_id)
> (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
> enum periphc_internal_id internal_id;
>
> - assert(clock_periph_id_isvalid(periph_id));
> + /* Coresight is a special case */
> + if (periph_id == PERIPH_ID_CSI)
> + return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
> +
> + assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
> internal_id = periph_id_to_internal_id[periph_id];
> assert(internal_id != -1);
> - return &clkrst->crc_clk_src[internal_id];
> + if (internal_id >= PERIPHC_VW_FIRST) {
> + internal_id -= PERIPHC_VW_FIRST;
> + return &clkrst->crc_clk_src_vw[internal_id];
> + } else
> + return &clkrst->crc_clk_src[internal_id];
> }
>
> void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
> @@ -614,34 +623,6 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
> (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
> }
>
> -int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
> -{
> - struct clk_pll *pll = get_pll(clkid);
> - int data = 0, div = 0, offset = 0;
> -
> - if (!clock_id_is_pll(clkid))
> - return -1;
> -
> - if (pllout + 1 > pll_num_clkouts[clkid])
> - return -1;
> -
> - div = clk_get_divider(8, pll_rate[clkid], rate);
> -
> - if (div < 0)
> - return -1;
> -
> - /* out2 and out4 are in the high part of the register */
> - if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
> - offset = 16;
> -
> - data = (div << PLL_OUT_RATIO_SHIFT) |
> - PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
> - clrsetbits_le32(&pll->pll_out[pllout >> 1],
> - PLL_OUT_RATIO_MASK << offset, data << offset);
> -
> - return 0;
> -}
> -
> /**
> * Find the best available 7.1 format divisor given a parent clock rate and
> * required child clock rate. This function assumes that a second-stage
> @@ -710,33 +691,12 @@ static int get_periph_clock_source(enum periph_id periph_id,
> type = clock_periph_type[internal_id];
> assert(clock_type_id_isvalid(type));
>
> - /*
> - * Special cases here for the clock with a 4-bit source mux and I2C
> - * with its 16-bit divisor
> - */
> - if (type == CLOCK_TYPE_PCXTS)
> - *mux_bits = 4;
> - else
> - *mux_bits = 2;
> - if (type == CLOCK_TYPE_PCMT16)
> - *divider_bits = 16;
> - else
> - *divider_bits = 8;
> + *mux_bits = clock_source[type][CLOCK_MAX_MUX];
>
> for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
> if (clock_source[type][mux] == parent)
> return mux;
>
> - /*
> - * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
> - * which is not in our table. If not, then they are asking for a
> - * source which this peripheral can't access through its mux.
> - */
> - assert(type == CLOCK_TYPE_PCXTS);
> - assert(parent == CLOCK_ID_SFROM32KHZ);
> - if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
> - return 4; /* mux value for this clock */
> -
> /* if we get here, either us or the caller has made a mistake */
> printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
> parent);
> @@ -780,8 +740,8 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
> enum clock_id parent, unsigned rate, int *extra_div)
> {
> unsigned effective_rate;
> - int mux_bits, divider_bits, source;
> - int divider;
> + int mux_bits, source;
> + int divider, divider_bits = 0;
>
> /* work out the source clock and set it */
> source = get_periph_clock_source(periph_id, parent, &mux_bits,
> @@ -829,11 +789,15 @@ void clock_set_enable(enum periph_id periph_id, int enable)
> {
> struct clk_rst_ctlr *clkrst =
> (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
> - u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
> + u32 *clk;
> u32 reg;
>
> /* Enable/disable the clock to this peripheral */
> assert(clock_periph_id_isvalid(periph_id));
> + if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
> + clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
> + else
> + clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
> reg = readl(clk);
> if (enable)
> reg |= PERIPH_MASK(periph_id);
> @@ -856,11 +820,15 @@ void reset_set_enable(enum periph_id periph_id, int enable)
> {
> struct clk_rst_ctlr *clkrst =
> (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
> - u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
> + u32 *reset;
> u32 reg;
>
> /* Enable/disable reset to the peripheral */
> assert(clock_periph_id_isvalid(periph_id));
> + if (periph_id < PERIPH_ID_VW_FIRST)
> + reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
> + else
> + reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
> reg = readl(reset);
> if (enable)
> reg |= PERIPH_MASK(periph_id);
> @@ -887,8 +855,8 @@ void reset_cmplx_set_enable(int cpu, int which, int reset)
> (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
> u32 mask;
>
> - /* Form the mask, which depends on the cpu chosen. Tegra20 has 2 */
> - assert(cpu >= 0 && cpu < 2);
> + /* Form the mask, which depends on the cpu chosen. Tegra3 has 4 */
> + assert(cpu >= 0 && cpu < 4);
> mask = which << cpu;
>
> /* either enable or disable those reset for that CPU */
> @@ -1075,31 +1043,29 @@ int clock_verify(void)
> printf("Warning: PLLP %x is not correct\n", reg);
> return -1;
> }
> - debug("PLLX %x is correct\n", reg);
> + debug("PLLP %x is correct\n", reg);
> return 0;
> }
>
> void clock_early_init(void)
> {
> /*
> - * PLLP output frequency set to 216MHz
> - * PLLC output frequency set to 600Mhz
> - *
> - * TODO: Can we calculate these values instead of hard-coding?
> + * PLLP output frequency set to 408Mhz
> + * PLLC output frequency set to 228Mhz
> */
> switch (clock_get_osc_freq()) {
> case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
> - clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
> - clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
> + clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
> + clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
> break;
>
> case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
> - clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
> + clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
> clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
> break;
>
> case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
> - clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
> + clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
> clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
> break;
> case CLOCK_OSC_FREQ_19_2:
> diff --git a/arch/arm/cpu/tegra30-common/funcmux.c b/arch/arm/cpu/tegra30-common/funcmux.c
> new file mode 100644
> index 0000000..e24c57e
> --- /dev/null
> +++ b/arch/arm/cpu/tegra30-common/funcmux.c
> @@ -0,0 +1,57 @@
> +/*
> + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/* Tegra30 high-level function multiplexing */
> +
> +#include <common.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/funcmux.h>
> +#include <asm/arch/pinmux.h>
> +
> +int funcmux_select(enum periph_id id, int config)
> +{
> + int bad_config = config != FUNCMUX_DEFAULT;
> +
> + switch (id) {
> + case PERIPH_ID_UART1:
> + switch (config) {
> + case FUNCMUX_UART1_ULPI:
> + pinmux_set_func(PINGRP_ULPI_DATA0, PMUX_FUNC_UARTA);
> + pinmux_set_func(PINGRP_ULPI_DATA1, PMUX_FUNC_UARTA);
> + pinmux_set_func(PINGRP_ULPI_DATA2, PMUX_FUNC_UARTA);
> + pinmux_set_func(PINGRP_ULPI_DATA3, PMUX_FUNC_UARTA);
> + pinmux_tristate_disable(PINGRP_ULPI_DATA0);
> + pinmux_tristate_disable(PINGRP_ULPI_DATA1);
> + pinmux_tristate_disable(PINGRP_ULPI_DATA2);
> + pinmux_tristate_disable(PINGRP_ULPI_DATA3);
> + break;
> + }
> + break;
> +
> + /* Add other periph IDs here as needed */
> +
> + default:
> + debug("%s: invalid periph_id %d", __func__, id);
> + return -1;
> + }
> +
> + if (bad_config) {
> + debug("%s: invalid config %d for periph_id %d", __func__,
> + config, id);
> + return -1;
> + }
> + return 0;
> +}
> diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
> new file mode 100644
> index 0000000..122665f
> --- /dev/null
> +++ b/arch/arm/cpu/tegra30-common/pinmux.c
> @@ -0,0 +1,506 @@
> +/*
> + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/* Tegra30 pin multiplexing functions */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/tegra.h>
> +#include <asm/arch/pinmux.h>
> +
> +struct tegra_pingroup_desc {
> + const char *name;
> + enum pmux_func funcs[4];
> + enum pmux_func func_safe;
> + enum pmux_vddio vddio;
> + enum pmux_pin_io io;
> +};
> +
> +#define PMUX_MUXCTL_SHIFT 0
> +#define PMUX_PULL_SHIFT 2
> +#define PMUX_TRISTATE_SHIFT 4
> +#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
> +#define PMUX_IO_SHIFT 5
> +#define PMUX_OD_SHIFT 6
> +#define PMUX_LOCK_SHIFT 7
> +#define PMUX_IO_RESET_SHIFT 8
> +
> +/* Convenient macro for defining pin group properties */
> +#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
> + { \
> + .vddio = PMUX_VDDIO_ ## vdd, \
> + .funcs = { \
> + PMUX_FUNC_ ## f0, \
> + PMUX_FUNC_ ## f1, \
> + PMUX_FUNC_ ## f2, \
> + PMUX_FUNC_ ## f3, \
> + }, \
> + .func_safe = PMUX_FUNC_RSVD1, \
> + .io = PMUX_PIN_ ## iod, \
> + }
> +
> +/* Input and output pins */
> +#define PINI(pg_name, vdd, f0, f1, f2, f3) \
> + PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
> +#define PINO(pg_name, vdd, f0, f1, f2, f3) \
> + PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
> +
> +const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
> + /* NAME VDD f0 f1 f2 f3 */
> + PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
> + PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
> + PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
> + PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
> + PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
> + PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
> + PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
> + PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
> + PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI),
> + PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI),
> + PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI),
> + PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI),
> + PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB),
> + PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB),
> + PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB),
> + PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB),
> + PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4),
> + PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
> + PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
> + PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
> + PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
> + PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
> + PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
> + PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
> + PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4),
> + PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
> + PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
> + PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
> + PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP),
> + PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4),
> + PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP),
> + PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP),
> + PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4),
> + PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP),
> + PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP),
> + PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4),
> + PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4),
> + PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4),
> + PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
> + PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
> + PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
> + PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
> + PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4),
> + PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4),
> + PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4),
> + PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4),
> + PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4),
> + PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4),
> + PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4),
> + PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4),
> + PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4),
> + PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4),
> + PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4),
> + PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4),
> + PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4),
> + PINI(VI_MCLK, VI, VI, VI, VI, VI),
> + PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4),
> + PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4),
> + PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
> + PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
> + PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4),
> + PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4),
> + PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4),
> + PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4),
> + PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4),
> + PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4),
> + PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4),
> + PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4),
> + PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4),
> + PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4),
> + PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4),
> + PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4),
> + PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4),
> + PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
> + PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
> + PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4),
> + PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4),
> + PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4),
> + PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4),
> + PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
> + PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
> + PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
> + PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV),
> + PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV),
> + PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
> + PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA),
> + PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT),
> + PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4),
> + PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4),
> + PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4),
> + PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4),
> + PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT),
> + PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV),
> + PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV),
> + PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4),
> + PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4),
> + PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
> + PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4),
> + PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4),
> + PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4),
> + PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4),
> + PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
> + PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
> + PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
> + PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
> + PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4),
> + PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4),
> + PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4),
> + PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4),
> + PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4),
> + PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4),
> + PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
> + PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
> + PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4),
> + PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4),
> + PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4),
> + PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4),
> + PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4),
> + PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4),
> + PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
> + PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
> + PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
> + PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
> + PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
> + PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4),
> + PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4),
> + PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4),
> + PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4),
> + PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4),
> + PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR),
> + PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO),
> + PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO),
> + PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO),
> + PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO),
> + PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO),
> + PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO),
> + PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO),
> + PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO),
> + PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO),
> + PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO),
> + PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST),
> + PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST),
> + PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4),
> + PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4),
> + PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4),
> + PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4),
> + PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO),
> + PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO),
> + PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4),
> + PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
> + PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
> + PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
> + PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4),
> + PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
> + PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4),
> + PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2),
> + PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2),
> + PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2),
> + PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2),
> + PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4),
> + PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
> + PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2),
> + PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2),
> + PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI),
> + PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI),
> + PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI),
> + PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI),
> + PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI),
> + PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI),
> + PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI),
> + PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI),
> + PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
> + PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
> + PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
> + PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4),
> + PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
> + PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
> + PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3),
> + PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2),
> + PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
> + PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
> + PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3),
> + PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3),
> + PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2),
> + PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2),
> + PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
> + PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
> + PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
> + PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
> + PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
> + PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
> + PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
> + PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
> + PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
> + PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
> + PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
> + PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
> + PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
> +};
> +
> +void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
> +{
> + struct pmux_tri_ctlr *pmt =
> + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
> + u32 *tri = &pmt->pmt_ctl[pin];
> + u32 reg;
> +
> + /* Error check on pin */
> + assert(pmux_pingrp_isvalid(pin));
> +
> + reg = readl(tri);
> + if (enable)
> + reg |= PMUX_TRISTATE_MASK;
> + else
> + reg &= ~PMUX_TRISTATE_MASK;
> + writel(reg, tri);
> +}
> +
> +void pinmux_tristate_enable(enum pmux_pingrp pin)
> +{
> + pinmux_set_tristate(pin, 1);
> +}
> +
> +void pinmux_tristate_disable(enum pmux_pingrp pin)
> +{
> + pinmux_set_tristate(pin, 0);
> +}
> +
> +void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
> +{
> + struct pmux_tri_ctlr *pmt =
> + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
> + u32 *pull = &pmt->pmt_ctl[pin];
> + u32 reg;
> +
> + /* Error check on pin and pupd */
> + assert(pmux_pingrp_isvalid(pin));
> + assert(pmux_pin_pupd_isvalid(pupd));
> +
> + reg = readl(pull);
> + reg &= ~(0x3 << PMUX_PULL_SHIFT);
> + reg |= (pupd << PMUX_PULL_SHIFT);
> + writel(reg, pull);
> +}
> +
> +void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
> +{
> + struct pmux_tri_ctlr *pmt =
> + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
> + u32 *muxctl = &pmt->pmt_ctl[pin];
> + int i, mux = -1;
> + u32 reg;
> +
> + /* Error check on pin and func */
> + assert(pmux_pingrp_isvalid(pin));
> + assert(pmux_func_isvalid(func));
> +
> + /* Handle special values */
> + if (func == PMUX_FUNC_SAFE)
> + func = tegra_soc_pingroups[pin].func_safe;
> +
> + if (func & PMUX_FUNC_RSVD1) {
> + mux = func & 0x3;
> + } else {
> + /* Search for the appropriate function */
> + for (i = 0; i < 4; i++) {
> + if (tegra_soc_pingroups[pin].funcs[i] == func) {
> + mux = i;
> + break;
> + }
> + }
> + }
> + assert(mux != -1);
> +
> + reg = readl(muxctl);
> + reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
> + reg |= (mux << PMUX_MUXCTL_SHIFT);
> + writel(reg, muxctl);
> +
> +}
> +
> +void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
> +{
> + struct pmux_tri_ctlr *pmt =
> + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
> + u32 *pin_io = &pmt->pmt_ctl[pin];
> + u32 reg;
> +
> + /* Error check on pin and io */
> + assert(pmux_pingrp_isvalid(pin));
> + assert(pmux_pin_io_isvalid(io));
> +
> + reg = readl(pin_io);
> + reg &= ~(0x1 << PMUX_IO_SHIFT);
> + reg |= (io & 0x1) << PMUX_IO_SHIFT;
> + writel(reg, pin_io);
> +}
> +
> +static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
> +{
> + struct pmux_tri_ctlr *pmt =
> + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
> + u32 *pin_lock = &pmt->pmt_ctl[pin];
> + u32 reg;
> +
> + /* Error check on pin and lock */
> + assert(pmux_pingrp_isvalid(pin));
> + assert(pmux_pin_lock_isvalid(lock));
> +
> + if (lock == PMUX_PIN_LOCK_DEFAULT)
> + return 0;
> +
> + reg = readl(pin_lock);
> + reg &= ~(0x1 << PMUX_LOCK_SHIFT);
> + if (lock == PMUX_PIN_LOCK_ENABLE)
> + reg |= (0x1 << PMUX_LOCK_SHIFT);
> + else {
> + /* lock == DISABLE, which isn't possible */
> + printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
> + __func__, lock);
> + }
> + writel(reg, pin_lock);
> +
> + return 0;
> +}
> +
> +static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
> +{
> + struct pmux_tri_ctlr *pmt =
> + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
> + u32 *pin_od = &pmt->pmt_ctl[pin];
> + u32 reg;
> +
> + /* Error check on pin and od */
> + assert(pmux_pingrp_isvalid(pin));
> + assert(pmux_pin_od_isvalid(od));
> +
> + if (od == PMUX_PIN_OD_DEFAULT)
> + return 0;
> +
> + reg = readl(pin_od);
> + reg &= ~(0x1 << PMUX_OD_SHIFT);
> + if (od == PMUX_PIN_OD_ENABLE)
> + reg |= (0x1 << PMUX_OD_SHIFT);
> + writel(reg, pin_od);
> +
> + return 0;
> +}
> +
> +static int pinmux_set_ioreset(enum pmux_pingrp pin,
> + enum pmux_pin_ioreset ioreset)
> +{
> + struct pmux_tri_ctlr *pmt =
> + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
> + u32 *pin_ioreset = &pmt->pmt_ctl[pin];
> + u32 reg;
> +
> + /* Error check on pin and ioreset */
> + assert(pmux_pingrp_isvalid(pin));
> + assert(pmux_pin_ioreset_isvalid(ioreset));
> +
> + if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
> + return 0;
> +
> + reg = readl(pin_ioreset);
> + reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
> + if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
> + reg |= (0x1 << PMUX_IO_RESET_SHIFT);
> + writel(reg, pin_ioreset);
> +
> + return 0;
> +}
> +
> +void pinmux_config_pingroup(struct pingroup_config *config)
> +{
> + enum pmux_pingrp pin = config->pingroup;
> +
> + pinmux_set_func(pin, config->func);
> + pinmux_set_pullupdown(pin, config->pull);
> + pinmux_set_tristate(pin, config->tristate);
> + pinmux_set_io(pin, config->io);
> + pinmux_set_lock(pin, config->lock);
> + pinmux_set_od(pin, config->od);
> + pinmux_set_ioreset(pin, config->ioreset);
> +}
> +
> +void pinmux_config_table(struct pingroup_config *config, int len)
> +{
> + int i;
> +
> + for (i = 0; i < len; i++)
> + pinmux_config_pingroup(&config[i]);
> +}
> diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h
> index 70d94c5..73dfd39 100644
> --- a/arch/arm/include/asm/arch-tegra/ap.h
> +++ b/arch/arm/include/asm/arch-tegra/ap.h
> @@ -23,67 +23,27 @@
> #include <asm/types.h>
>
> /* Stabilization delays, in usec */
> -#define PLL_STABILIZATION_DELAY (300)
> +#define PLL_STABILIZATION_DELAY (300)
> #define IO_STABILIZATION_DELAY (1000)
>
> -#define NVBL_PLLP_KHZ (216000)
> -
> #define PLLX_ENABLED (1 << 30)
> #define CCLK_BURST_POLICY 0x20008888
> #define SUPER_CCLK_DIVIDER 0x80000000
>
> /* Calculate clock fractional divider value from ref and target frequencies */
> -#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
> +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
>
> /* Calculate clock frequency value from reference and clock divider value */
> -#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
> +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
>
> /* AVP/CPU ID */
> #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
> -#define PG_UP_TAG_0 0x0
> +#define PG_UP_TAG_0 0x0
>
> #define CORESIGHT_UNLOCK 0xC5ACCE55;
>
> -/* AP20-Specific Base Addresses */
> -
> -/* AP20 Base physical address of SDRAM. */
> -#define AP20_BASE_PA_SDRAM 0x00000000
> -/* AP20 Base physical address of internal SRAM. */
> -#define AP20_BASE_PA_SRAM 0x40000000
> -/* AP20 Size of internal SRAM (256KB). */
> -#define AP20_BASE_PA_SRAM_SIZE 0x00040000
> -/* AP20 Base physical address of flash. */
> -#define AP20_BASE_PA_NOR_FLASH 0xD0000000
> -/* AP20 Base physical address of boot information table. */
> -#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
> -
> -/*
> - * Super-temporary stacks for EXTREMELY early startup. The values chosen for
> - * these addresses must be valid on ALL SOCs because this value is used before
> - * we are able to differentiate between the SOC types.
> - *
> - * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
> - * stack is placed below the AVP stack. Once the CPU stack has been moved,
> - * the AVP is free to use the IRAM the CPU stack previously occupied if
> - * it should need to do so.
> - *
> - * NOTE: In multi-processor CPU complex configurations, each processor will have
> - * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
> - * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
> - * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
> - * CPU.
> - */
> -
> -/* Common AVP early boot stack limit */
> -#define AVP_EARLY_BOOT_STACK_LIMIT \
> - (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
> -/* Common AVP early boot stack size */
> -#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
> -/* Common CPU early boot stack limit */
> -#define CPU_EARLY_BOOT_STACK_LIMIT \
> - (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
> -/* Common CPU early boot stack size */
> -#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
> +/* AP base physical address of internal SRAM */
> +#define NV_PA_BASE_SRAM 0x40000000
>
> #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
> #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
> --
> 1.7.0.4
>
--
nvpublic
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 4/7] Tegra30: Add common CPU (shared) files
2012-12-12 0:45 ` Allen Martin
@ 2012-12-12 16:14 ` Tom Warren
2012-12-12 22:06 ` Stephen Warren
0 siblings, 1 reply; 31+ messages in thread
From: Tom Warren @ 2012-12-12 16:14 UTC (permalink / raw)
To: u-boot
Allen,
On Tue, Dec 11, 2012 at 5:45 PM, Allen Martin <amartin@nvidia.com> wrote:
> On Tue, Dec 11, 2012 at 03:34:15PM -0800, Tom Warren wrote:
>> These files are used by both SPL and main U-Boot.
>> Also made minor changes to shared Tegra code to support
>> T30 differences.
>>
>> Signed-off-by: Tom Warren <twarren@nvidia.com>
>> ---
>> V2:
>> * Differentiate between T20 and T30 in ODMDATA and query_sdram_size.
>> * Fix numerous func entries in pingroup table as per Stephen.
>> * Added warning about LOCK bit in pinmux_set_lock.
>> V3:
>> * Always program PLLP to 408MHz
>> * Use generic SoC string in print_cpuinfo
>>
<snip>
>>
>> - bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
>> + bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
>> odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
>>
>> return odmdata;
>> @@ -127,5 +137,5 @@ void s_init(void)
>> "orr r0, r0, #0x41\n"
>> "mcr p15, 0, r0, c1, c0, 1\n");
>>
>> - /* FIXME: should have ap20's L2 disabled too? */
>> + /* FIXME: should have SoC's L2 disabled too? */
>
> We should probably just remove this README, I don't believe it applies
> any more.
By README, you mean FIXME? It can be removed, but only if I'm forced
to do a V4 patchset for more substantive changes. Otherwise I'll put
it in my list of 'cleanup' items.
>
>> }
>> diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
>> index b2e10c6..af1879c 100644
>> --- a/arch/arm/cpu/tegra-common/board.c
>> +++ b/arch/arm/cpu/tegra-common/board.c
<snip>
>>
>> int dram_init(void)
>> @@ -82,19 +103,27 @@ int checkboard(void)
>> #endif /* CONFIG_DISPLAY_BOARDINFO */
>>
>> static int uart_configs[] = {
>> -#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
>> +#if defined(CONFIG_TEGRA20)
>> + #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
>> FUNCMUX_UART1_UAA_UAB,
>> -#elif defined(CONFIG_TEGRA_UARTA_GPU)
>> + #elif defined(CONFIG_TEGRA_UARTA_GPU)
>> FUNCMUX_UART1_GPU,
>> -#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
>> + #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
>> FUNCMUX_UART1_SDIO1,
>> -#else
>> + #else
>> FUNCMUX_UART1_IRRX_IRTX,
>> -#endif
>> + #endif
>> FUNCMUX_UART2_IRDA,
>> -1,
>> FUNCMUX_UART4_GMC,
>> -1,
>> +#else /* Tegra30 */
>> + FUNCMUX_UART1_ULPI, /* UARTA */
>> + -1,
>> + -1,
>> + -1,
>> + -1,
>
> Shouldn't there be entries for other UART selections here?
Right now, there are no other T30 boards in my possession with any
other UARTs used for debug output. Stephen's soon-to-be-adopted
ODMDATA/ODMDATA2 changes will hopefully remove the need for these
tables.
<snip>
>> diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/tegra30-common/Makefile
>> similarity index 80%
>> copy from arch/arm/cpu/arm720t/tegra30/Makefile
>> copy to arch/arm/cpu/tegra30-common/Makefile
>> index bd96997..75fef32 100644
>> --- a/arch/arm/cpu/arm720t/tegra30/Makefile
>> +++ b/arch/arm/cpu/tegra30-common/Makefile
>> @@ -19,12 +19,15 @@
>>
>> include $(TOPDIR)/config.mk
>>
>> -LIB = $(obj)lib$(SOC).o
>> +# The AVP is ARMv4T architecture so we must use special compiler
>> +# flags for any startup files it might use.
>
> The SPL build should make this transparent to this Makefile.
I"ll remove the comment if I do a V4 patchset, otherwise it'll go in
the 'cleanup' patchset.
Thanks,
Tom
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 4/7] Tegra30: Add common CPU (shared) files
2012-12-12 16:14 ` Tom Warren
@ 2012-12-12 22:06 ` Stephen Warren
2012-12-12 23:07 ` Tom Warren
0 siblings, 1 reply; 31+ messages in thread
From: Stephen Warren @ 2012-12-12 22:06 UTC (permalink / raw)
To: u-boot
On 12/12/2012 09:14 AM, Tom Warren wrote:
> Allen,
>
> On Tue, Dec 11, 2012 at 5:45 PM, Allen Martin <amartin@nvidia.com> wrote:
>> On Tue, Dec 11, 2012 at 03:34:15PM -0800, Tom Warren wrote:
>>> These files are used by both SPL and main U-Boot.
>>> Also made minor changes to shared Tegra code to support
>>> T30 differences.
>>>
>>> Signed-off-by: Tom Warren <twarren@nvidia.com>
>>> ---
>>> V2:
>>> * Differentiate between T20 and T30 in ODMDATA and query_sdram_size.
>>> * Fix numerous func entries in pingroup table as per Stephen.
>>> * Added warning about LOCK bit in pinmux_set_lock.
>>> V3:
>>> * Always program PLLP to 408MHz
>>> * Use generic SoC string in print_cpuinfo
>>>
> <snip>
>>>
>>> - bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
>>> + bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
>>> odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
>>>
>>> return odmdata;
>>> @@ -127,5 +137,5 @@ void s_init(void)
>>> "orr r0, r0, #0x41\n"
>>> "mcr p15, 0, r0, c1, c0, 1\n");
>>>
>>> - /* FIXME: should have ap20's L2 disabled too? */
>>> + /* FIXME: should have SoC's L2 disabled too? */
>>
>> We should probably just remove this README, I don't believe it applies
>> any more.
>
> By README, you mean FIXME? It can be removed, but only if I'm forced
> to do a V4 patchset for more substantive changes. Otherwise I'll put
> it in my list of 'cleanup' items.
In my opinion at least, for very minor stuff like this, you can just
implement the review feedback and apply the patches without the need to
actually repost it. Anything much more than editing a comment, removing
a stale comment or removing some added lines from the patch that
shouldn't be added would warrant a repost though.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 4/7] Tegra30: Add common CPU (shared) files
2012-12-12 22:06 ` Stephen Warren
@ 2012-12-12 23:07 ` Tom Warren
0 siblings, 0 replies; 31+ messages in thread
From: Tom Warren @ 2012-12-12 23:07 UTC (permalink / raw)
To: u-boot
Stephen,
On Wed, Dec 12, 2012 at 3:06 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 12/12/2012 09:14 AM, Tom Warren wrote:
>> Allen,
>>
>> On Tue, Dec 11, 2012 at 5:45 PM, Allen Martin <amartin@nvidia.com> wrote:
>>> On Tue, Dec 11, 2012 at 03:34:15PM -0800, Tom Warren wrote:
>>>> These files are used by both SPL and main U-Boot.
>>>> Also made minor changes to shared Tegra code to support
>>>> T30 differences.
>>>>
>>>> Signed-off-by: Tom Warren <twarren@nvidia.com>
>>>> ---
>>>> V2:
>>>> * Differentiate between T20 and T30 in ODMDATA and query_sdram_size.
>>>> * Fix numerous func entries in pingroup table as per Stephen.
>>>> * Added warning about LOCK bit in pinmux_set_lock.
>>>> V3:
>>>> * Always program PLLP to 408MHz
>>>> * Use generic SoC string in print_cpuinfo
>>>>
>> <snip>
>>>>
>>>> - bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
>>>> + bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
>>>> odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
>>>>
>>>> return odmdata;
>>>> @@ -127,5 +137,5 @@ void s_init(void)
>>>> "orr r0, r0, #0x41\n"
>>>> "mcr p15, 0, r0, c1, c0, 1\n");
>>>>
>>>> - /* FIXME: should have ap20's L2 disabled too? */
>>>> + /* FIXME: should have SoC's L2 disabled too? */
>>>
>>> We should probably just remove this README, I don't believe it applies
>>> any more.
>>
>> By README, you mean FIXME? It can be removed, but only if I'm forced
>> to do a V4 patchset for more substantive changes. Otherwise I'll put
>> it in my list of 'cleanup' items.
>
> In my opinion at least, for very minor stuff like this, you can just
> implement the review feedback and apply the patches without the need to
> actually repost it. Anything much more than editing a comment, removing
> a stale comment or removing some added lines from the patch that
> shouldn't be added would warrant a repost though.
I see - another good point. I'd always been really anal about patches
and bumped another Vx for even minor stuff.
I can drop the stuff you and Allen mentioned when I apply these to
u-boot-tegra/next. Thanks.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 4/7] Tegra30: Add common CPU (shared) files
2012-12-11 23:34 ` [U-Boot] [PATCH V3 4/7] Tegra30: Add common CPU (shared) files Tom Warren
2012-12-12 0:45 ` Allen Martin
@ 2012-12-12 22:09 ` Stephen Warren
1 sibling, 0 replies; 31+ messages in thread
From: Stephen Warren @ 2012-12-12 22:09 UTC (permalink / raw)
To: u-boot
On 12/11/2012 04:34 PM, Tom Warren wrote:
> These files are used by both SPL and main U-Boot.
> Also made minor changes to shared Tegra code to support
> T30 differences.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
(briefly!)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 5/7] Tegra30: Cardhu: Add DT files
2012-12-11 23:34 [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Tom Warren
` (3 preceding siblings ...)
2012-12-11 23:34 ` [U-Boot] [PATCH V3 4/7] Tegra30: Add common CPU (shared) files Tom Warren
@ 2012-12-11 23:34 ` Tom Warren
2012-12-12 22:10 ` Stephen Warren
2012-12-11 23:34 ` [U-Boot] [PATCH V3 6/7] Tegra30: Add generic Tegra30 build support Tom Warren
` (3 subsequent siblings)
8 siblings, 1 reply; 31+ messages in thread
From: Tom Warren @ 2012-12-11 23:34 UTC (permalink / raw)
To: u-boot
These are stripped down for bringup, They'll be filled out later
to match-up with the kernel DT contents, and/or as devices are
brought up (mmc, usb, spi, etc.).
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
V2: Reduce to the minimum needed to build/boot to cmd prompt
V3: Remove model= from .dtsi, fix memory length in .dts
arch/arm/dts/tegra30.dtsi | 5 +++++
board/nvidia/dts/tegra30-cardhu.dts | 14 ++++++++++++++
2 files changed, 19 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/dts/tegra30.dtsi
create mode 100644 board/nvidia/dts/tegra30-cardhu.dts
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
new file mode 100644
index 0000000..f568d44
--- /dev/null
+++ b/arch/arm/dts/tegra30.dtsi
@@ -0,0 +1,5 @@
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "nvidia,tegra30";
+};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
new file mode 100644
index 0000000..3012534
--- /dev/null
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "NVIDIA Cardhu";
+ compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 5/7] Tegra30: Cardhu: Add DT files
2012-12-11 23:34 ` [U-Boot] [PATCH V3 5/7] Tegra30: Cardhu: Add DT files Tom Warren
@ 2012-12-12 22:10 ` Stephen Warren
2012-12-12 23:11 ` Tom Warren
0 siblings, 1 reply; 31+ messages in thread
From: Stephen Warren @ 2012-12-12 22:10 UTC (permalink / raw)
To: u-boot
On 12/11/2012 04:34 PM, Tom Warren wrote:
> These are stripped down for bringup, They'll be filled out later
> to match-up with the kernel DT contents, and/or as devices are
> brought up (mmc, usb, spi, etc.).
> diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
> +/memreserve/ 0x1c000000 0x04000000;
We should drop that line. Aside from that,
Reviewed-by: Stephen Warren <swarren@nvidia.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 5/7] Tegra30: Cardhu: Add DT files
2012-12-12 22:10 ` Stephen Warren
@ 2012-12-12 23:11 ` Tom Warren
0 siblings, 0 replies; 31+ messages in thread
From: Tom Warren @ 2012-12-12 23:11 UTC (permalink / raw)
To: u-boot
Stephen,
On Wed, Dec 12, 2012 at 3:10 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 12/11/2012 04:34 PM, Tom Warren wrote:
>> These are stripped down for bringup, They'll be filled out later
>> to match-up with the kernel DT contents, and/or as devices are
>> brought up (mmc, usb, spi, etc.).
>
>> diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
>
>> +/memreserve/ 0x1c000000 0x04000000;
>
> We should drop that line. Aside from that,
I thought I had dropped it, but it must have crept back in. I'll
remove it. Thanks
>
> Reviewed-by: Stephen Warren <swarren@nvidia.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 6/7] Tegra30: Add generic Tegra30 build support
2012-12-11 23:34 [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Tom Warren
` (4 preceding siblings ...)
2012-12-11 23:34 ` [U-Boot] [PATCH V3 5/7] Tegra30: Cardhu: Add DT files Tom Warren
@ 2012-12-11 23:34 ` Tom Warren
2012-12-12 22:13 ` Stephen Warren
2012-12-11 23:34 ` [U-Boot] [PATCH V3 7/7] Tegra30: Add/enable Cardhu build (T30 reference board) Tom Warren
` (2 subsequent siblings)
8 siblings, 1 reply; 31+ messages in thread
From: Tom Warren @ 2012-12-11 23:34 UTC (permalink / raw)
To: u-boot
This patch adds basic Tegra30 (T30) build support - no specific
board is targeted.
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
V2:
* Use generic CONFIG_TEGRA in Makefile instead of specific SOC test
* Cleanup a couple of include files due to T20/T30 build differences
* Move pinmux_init to board code
V3:
* No changes
Makefile | 6 +++---
arch/arm/cpu/armv7/Makefile | 2 +-
arch/arm/cpu/armv7/start.S | 4 ++--
board/nvidia/common/board.c | 17 ++++++++++++++---
include/serial.h | 2 +-
spl/Makefile | 2 +-
6 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/Makefile b/Makefile
index 8a04727..5bbfbaf 100644
--- a/Makefile
+++ b/Makefile
@@ -344,7 +344,7 @@ endif
ifeq ($(SOC),exynos)
LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
endif
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
@@ -408,7 +408,7 @@ ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
# enable combined SPL/u-boot/dtb rules for tegra
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
ifeq ($(CONFIG_OF_SEPARATE),y)
ALL-y += $(obj)u-boot-dtb-tegra.bin
else
@@ -515,7 +515,7 @@ $(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
conv=notrunc 2>/dev/null
cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
ifeq ($(CONFIG_OF_SEPARATE),y)
nodtb=dtb
dtbfile=$(obj)u-boot.dtb
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..ee8c2b3 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS += cache_v7.o
COBJS += cpu.o
COBJS += syslib.o
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),)
SOBJS += lowlevel_init.o
endif
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 7df97c5..213f452 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -272,12 +272,12 @@ jump_2_ram:
/*
* Move vector table
*/
-#if !defined(CONFIG_TEGRA20)
+#if !defined(CONFIG_TEGRA)
/* Set vector address in CP15 VBAR register */
ldr r0, =_start
add r0, r0, r9
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
-#endif /* !Tegra20 */
+#endif /* !Tegra */
ldr r0, _board_init_r_ofs
adr r1, _start
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 819c120..a4af539 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -26,22 +26,30 @@
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#ifdef CONFIG_LCD
#include <asm/arch/display.h>
-#include <asm/arch/emc.h>
+#endif
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/pmu.h>
+#ifdef CONFIG_PWM_TEGRA
#include <asm/arch/pwm.h>
+#endif
#include <asm/arch/tegra.h>
-#include <asm/arch/usb.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/sys_proto.h>
#include <asm/arch-tegra/uart.h>
#include <asm/arch-tegra/warmboot.h>
-#include <spi.h>
+#ifdef CONFIG_TEGRA_CLOCK_SCALING
+#include <asm/arch/emc.h>
+#endif
+#ifdef CONFIG_USB_EHCI_TEGRA
+#include <asm/arch/usb.h>
+#endif
#include <i2c.h>
+#include <spi.h>
#include "emc.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -188,6 +196,9 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
int board_early_init_f(void)
{
+#if defined(CONFIG_TEGRA30)
+ pinmux_init();
+#endif
board_init_uart_f();
/* Initialize periph GPIOs */
diff --git a/include/serial.h b/include/serial.h
index 14f863e..f6bb2b9 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -32,7 +32,7 @@ extern struct serial_device *default_serial_console(void);
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
- defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) || \
+ defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
defined(CONFIG_MICROBLAZE)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
diff --git a/spl/Makefile b/spl/Makefile
index 6a79c3c..8dee4e0 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -65,7 +65,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 7/7] Tegra30: Add/enable Cardhu build (T30 reference board)
2012-12-11 23:34 [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Tom Warren
` (5 preceding siblings ...)
2012-12-11 23:34 ` [U-Boot] [PATCH V3 6/7] Tegra30: Add generic Tegra30 build support Tom Warren
@ 2012-12-11 23:34 ` Tom Warren
2012-12-12 22:21 ` Stephen Warren
2012-12-12 1:09 ` [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Allen Martin
2012-12-12 3:05 ` Allen Martin
8 siblings, 1 reply; 31+ messages in thread
From: Tom Warren @ 2012-12-11 23:34 UTC (permalink / raw)
To: u-boot
This build is stripped down. It boots to the command prompt.
GPIO is the only peripheral supported. Others TBD.
include/configs/tegra-common.h now holds common config options
for Tegra SoCs.
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
---
V2:
* Move pinmux_init to cardhu.c, move pinmux-config header here, too.
* tegra-common.h holds CONFIG options/defines commmon to all Tegra SoCs.
V3:
* Remove REALTEK HDA section in pinmux-config header
* Use 408MHz UART clock on T30 (still 216MHz on T20)
* Remove CONFIG_SYS_CPU_OSC_FREQUENCY (unused)
* Move MEM_LAYOUT_ENV settings to tegraXX-common.h
board/nvidia/cardhu/Makefile | 44 +++
board/nvidia/cardhu/cardhu.c | 39 +++
board/nvidia/cardhu/pinmux-config-cardhu.h | 329 ++++++++++++++++++++
boards.cfg | 1 +
include/configs/cardhu.h | 45 +++
include/configs/tegra-common-post.h | 27 --
.../configs/{tegra20-common.h => tegra-common.h} | 59 +----
include/configs/tegra20-common.h | 199 ++++---------
include/configs/tegra30-common.h | 86 +++++
9 files changed, 602 insertions(+), 227 deletions(-)
create mode 100644 board/nvidia/cardhu/Makefile
create mode 100644 board/nvidia/cardhu/cardhu.c
create mode 100644 board/nvidia/cardhu/pinmux-config-cardhu.h
create mode 100644 include/configs/cardhu.h
copy include/configs/{tegra20-common.h => tegra-common.h} (72%)
create mode 100644 include/configs/tegra30-common.h
diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile
new file mode 100644
index 0000000..913f1ce
--- /dev/null
+++ b/board/nvidia/cardhu/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
new file mode 100644
index 0000000..df4cb6b
--- /dev/null
+++ b/board/nvidia/cardhu/cardhu.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-cardhu.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_table(tegra3_pinmux_common,
+ ARRAY_SIZE(tegra3_pinmux_common));
+
+ pinmux_config_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
+}
diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h
new file mode 100644
index 0000000..3162219
--- /dev/null
+++ b/board/nvidia/cardhu/pinmux-config-cardhu.h
@@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_CARDHU_H_
+#define _PINMUX_CONFIG_CARDHU_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+static struct pingroup_config tegra3_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C2 pinmux */
+ I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C3 pinmux */
+ I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C4 pinmux */
+ I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* Power I2C pinmux */
+ I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+ LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
+ DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+ DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+ DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+ /* KBC keys */
+ DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ /* GPIOs */
+ /* SDMMC1 CD gpio */
+ DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
+ /* SDMMC1 WP gpio */
+ LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* Touch panel GPIO */
+ /* Touch IRQ */
+ DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT),
+
+ /* Touch RESET */
+ DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
+
+ /* Power rails GPIO */
+ DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
+
+ LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+#endif /* _PINMUX_CONFIG_CARDHU_H_ */
diff --git a/boards.cfg b/boards.cfg
index 6f21af0..01fd77f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -287,6 +287,7 @@ harmony arm armv7:arm720t harmony nvidia
seaboard arm armv7:arm720t seaboard nvidia tegra20
ventana arm armv7:arm720t ventana nvidia tegra20
whistler arm armv7:arm720t whistler nvidia tegra20
+cardhu arm armv7:arm720t cardhu nvidia tegra30
colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20
u8500_href arm armv7 u8500 st-ericsson u8500
snowball arm armv7 snowball st-ericsson u8500
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
new file mode 100644
index 0000000..471df6e
--- /dev/null
+++ b/include/configs/cardhu.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+
+#include "tegra30-common.h"
+
+/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT "Tegra30 (Cardhu) # "
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ENV_IS_NOWHERE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index c9c49d9..dee96da 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -119,33 +119,6 @@
#endif
-/*
- * Memory layout for where various images get loaded by boot scripts:
- *
- * scriptaddr can be pretty much anywhere that doesn't conflict with something
- * else. Put it above BOOTMAPSZ to eliminate conflicts.
- *
- * kernel_addr_r must be within the first 128M of RAM in order for the
- * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
- * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
- * should not overlap that area, or the kernel will have to copy itself
- * somewhere else before decompression. Similarly, the address of any other
- * data passed to the kernel shouldn't overlap the start of RAM. Pushing
- * this up to 16M allows for a sizable kernel to be decompressed below the
- * compressed load address.
- *
- * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
- * the compressed kernel to be up to 16M too.
- *
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
- * for the FDT/DTB to be up to 1M, which is hopefully plenty.
- */
-#define MEM_LAYOUT_ENV_SETTINGS \
- "scriptaddr=0x10000000\0" \
- "kernel_addr_r=0x01000000\0" \
- "fdt_addr_r=0x02000000\0" \
- "ramdisk_addr_r=0x02100000\0" \
-
#ifndef TEGRA_DEVICE_SETTINGS
#ifdef CONFIG_TEGRA_KEYBOARD
#define STDIN_KBD_KBC ",tegra-kbc"
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra-common.h
similarity index 72%
copy from include/configs/tegra20-common.h
copy to include/configs/tegra-common.h
index efd92e0..80c846c 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra-common.h
@@ -21,8 +21,8 @@
* MA 02111-1307 USA
*/
-#ifndef __TEGRA20_COMMON_H
-#define __TEGRA20_COMMON_H
+#ifndef _TEGRA_COMMON_H_
+#define _TEGRA_COMMON_H_
#include <asm/sizes.h>
#include <linux/stringify.h>
@@ -30,7 +30,6 @@
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
-#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
#define CONFIG_TEGRA /* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
@@ -38,9 +37,6 @@
#include <asm/arch/tegra.h> /* get chip and board defs */
-/* Align LCD to 1MB boundary */
-#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
-
/*
* Display CPU and Board information
*/
@@ -50,16 +46,6 @@
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
-#ifdef CONFIG_TEGRA_LP0
-#define TEGRA_LP0_ADDR 0x1C406000
-#define TEGRA_LP0_SIZE 0x2000
-#define TEGRA_LP0_VEC \
- "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
- "@" __stringify(TEGRA_LP0_ADDR) " "
-#else
-#define TEGRA_LP0_VEC
-#endif
-
/* Environment */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
@@ -70,15 +56,8 @@
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
/*
- * PllX Configuration
- */
-#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
-
-/*
* NS16550 Configuration
*/
-#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
-
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
@@ -92,26 +71,9 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/*
- * This parameter affects a TXFILLTUNING field that controls how much data is
- * sent to the latency fifo before it is sent to the wire. Without this
- * parameter, the default (2) causes occasional Data Buffer Errors in OUT
- * packets depending on the buffer address and size.
- */
-#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_EHCI_DCACHE
-
-/* Total I2C ports on Tegra20 */
-#define TEGRA_I2C_NUM_CONTROLLERS 4
/* include default commands */
#include <config_cmd_default.h>
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
/* remove unused commands */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
@@ -130,8 +92,6 @@
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
/*
@@ -155,11 +115,8 @@
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
-#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
#define CONFIG_SYS_HZ 1000
-#define CONFIG_STACKBASE 0x2800000 /* 40MB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
@@ -167,11 +124,10 @@
#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_TEXT_BASE 0x0010c000
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
@@ -190,20 +146,13 @@
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE 0x00108000
#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
-#define CONFIG_SPL_STACK 0x000ffffc
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
-
-#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#endif /* __TEGRA20_COMMON_H */
+#endif /* _TEGRA_COMMON_H_ */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index efd92e0..5143b64 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -21,34 +21,70 @@
* MA 02111-1307 USA
*/
-#ifndef __TEGRA20_COMMON_H
-#define __TEGRA20_COMMON_H
-#include <asm/sizes.h>
-#include <linux/stringify.h>
+#ifndef _TEGRA20_COMMON_H_
+#define _TEGRA20_COMMON_H_
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
-#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
-#define CONFIG_TEGRA /* which is a Tegra generic machine */
-#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
+#define CONFIG_TEGRA20 /* NVidia Tegra20 core */
-#define CONFIG_SYS_CACHELINE_SIZE 32
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
-#include <asm/arch/tegra.h> /* get chip and board defs */
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
+#define CONFIG_STACKBASE 0x2800000 /* 40MB */
-/* Align LCD to 1MB boundary */
-#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE 0x0010E000
/*
- * Display CPU and Board information
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ * the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=0x10000000\0" \
+ "kernel_addr_r=0x01000000\0" \
+ "fdt_addr_r=0x02000000\0" \
+ "ramdisk_addr_r=0x02100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE 0x00108000
+#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
+#define CONFIG_SPL_STACK 0x000ffffc
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
+
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
#ifdef CONFIG_TEGRA_LP0
#define TEGRA_LP0_ADDR 0x1C406000
@@ -60,41 +96,6 @@
#define TEGRA_LP0_VEC
#endif
-/* Environment */
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
-
-/*
- * PllX Configuration
- */
-#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
/*
* This parameter affects a TXFILLTUNING field that controls how much data is
* sent to the latency fifo before it is sent to the wire. Without this
@@ -108,102 +109,10 @@
/* Total I2C ports on Tegra20 */
#define TEGRA_I2C_NUM_CONTROLLERS 4
-/* include default commands */
-#include <config_cmd_default.h>
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
-/* remove unused commands */
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration support */
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NFS /* NFS support */
-#undef CONFIG_CMD_NET /* network support */
-
-/* turn on command-line edit/hist/auto */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
-
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
-#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT V_PROMPT
-/*
- * Increasing the size of the IO buffer as default nfsargs size is more
- * than 256 and so it is not possible to edit it
- */
-#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
-
-#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
-#define CONFIG_SYS_HZ 1000
-
-#define CONFIG_STACKBASE 0x2800000 /* 40MB */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
-
-#define CONFIG_SYS_TEXT_BASE 0x0010c000
-#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_TEGRA_GPIO
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_ENTERRCM
-#define CONFIG_CMD_BOOTZ
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE 0x00108000
-#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
- CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
-#define CONFIG_SPL_STACK 0x000ffffc
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
-
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#endif /* __TEGRA20_COMMON_H */
+#endif /* _TEGRA20_COMMON_H_ */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
new file mode 100644
index 0000000..282caec
--- /dev/null
+++ b/include/configs/tegra30-common.h
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA30_COMMON_H_
+#define _TEGRA30_COMMON_H_
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
+#define CONFIG_STACKBASE 0x82800000 /* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE 0x8010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ * the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=0x90000000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x82000000\0" \
+ "ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE 0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
+#define CONFIG_SPL_STACK 0x800ffffc
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra30/u-boot-spl.lds"
+
+#endif /* _TEGRA30_COMMON_H_ */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC
2012-12-11 23:34 [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Tom Warren
` (6 preceding siblings ...)
2012-12-11 23:34 ` [U-Boot] [PATCH V3 7/7] Tegra30: Add/enable Cardhu build (T30 reference board) Tom Warren
@ 2012-12-12 1:09 ` Allen Martin
2012-12-12 2:47 ` Allen Martin
2012-12-12 3:05 ` Allen Martin
8 siblings, 1 reply; 31+ messages in thread
From: Allen Martin @ 2012-12-12 1:09 UTC (permalink / raw)
To: u-boot
On Tue, Dec 11, 2012 at 03:34:11PM -0800, Tom Warren wrote:
> This patch series adds basic (boot to cmd prompt) support for Tegra30.
> This is based on the Tegra20 SPL, which initializes the AVP (ARM7TDMI)
> boot proc) first, then control is transferred to the CPU (A9 quad cluster).
> It is based on current u-boot-tegra/next. Some Tegra20 files were
I wasn't able to get these to apply cleanly to u-boot-tegra/next. It
failed on the first patch:
$ git am ~/twarren
Applying: Tegra30: Add arch-tegra30 include files
error: patch failed: arch/arm/include/asm/arch-tegra/clk_rst.h:37
error: arch/arm/include/asm/arch-tegra/clk_rst.h: patch does not apply
error: patch failed: arch/arm/include/asm/arch-tegra/clock.h:136
error: arch/arm/include/asm/arch-tegra/clock.h: patch does not apply
error: patch failed: arch/arm/include/asm/arch-tegra/tegra.h:72
error: arch/arm/include/asm/arch-tegra/tegra.h: patch does not apply
error: patch failed: arch/arm/include/asm/arch-tegra20/funcmux.h:62
error: arch/arm/include/asm/arch-tegra20/funcmux.h: patch does not apply
error: patch failed: arch/arm/include/asm/arch-tegra20/gp_padctrl.h:61
error: arch/arm/include/asm/arch-tegra20/gp_padctrl.h: patch does not apply
Patch failed at 0001 Tegra30: Add arch-tegra30 include files
When you have resolved this problem run "git am --resolved".
If you would prefer to skip this patch, instead run "git am --skip".
To restore the original branch and stop patching run "git am --abort".
--
nvpublic
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC
2012-12-12 1:09 ` [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Allen Martin
@ 2012-12-12 2:47 ` Allen Martin
0 siblings, 0 replies; 31+ messages in thread
From: Allen Martin @ 2012-12-12 2:47 UTC (permalink / raw)
To: u-boot
On Tue, Dec 11, 2012 at 05:09:45PM -0800, Allen Martin wrote:
> On Tue, Dec 11, 2012 at 03:34:11PM -0800, Tom Warren wrote:
> > This patch series adds basic (boot to cmd prompt) support for Tegra30.
> > This is based on the Tegra20 SPL, which initializes the AVP (ARM7TDMI)
> > boot proc) first, then control is transferred to the CPU (A9 quad cluster).
> > It is based on current u-boot-tegra/next. Some Tegra20 files were
>
> I wasn't able to get these to apply cleanly to u-boot-tegra/next. It
> failed on the first patch:
>
My bad, I pulled the patches from patchwork and they apply cleanly, so
I must have mangled them somehow.
-Allen
--
nvpublic
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC
2012-12-11 23:34 [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Tom Warren
` (7 preceding siblings ...)
2012-12-12 1:09 ` [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC Allen Martin
@ 2012-12-12 3:05 ` Allen Martin
2012-12-12 22:40 ` Simon Glass
8 siblings, 1 reply; 31+ messages in thread
From: Allen Martin @ 2012-12-12 3:05 UTC (permalink / raw)
To: u-boot
On Tue, Dec 11, 2012 at 03:34:11PM -0800, Tom Warren wrote:
> This patch series adds basic (boot to cmd prompt) support for Tegra30.
> This is based on the Tegra20 SPL, which initializes the AVP (ARM7TDMI)
> boot proc) first, then control is transferred to the CPU (A9 quad cluster).
> It is based on current u-boot-tegra/next. Some Tegra20 files were
> changed or moved to enable use of common code/headers.
>
> Future patches will add support/drivers for MMC, USB, I2C, SPI, NAND
> and other peripherals. The Cardhu T30 boards is supported initially.
>
Booted to command prompt on cardhu with the series, so:
Tested-by: Allen Martin <amartin@nvidia.com>
--
nvpublic
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC
2012-12-12 3:05 ` Allen Martin
@ 2012-12-12 22:40 ` Simon Glass
2012-12-12 23:12 ` Tom Warren
0 siblings, 1 reply; 31+ messages in thread
From: Simon Glass @ 2012-12-12 22:40 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Tue, Dec 11, 2012 at 7:05 PM, Allen Martin <amartin@nvidia.com> wrote:
> On Tue, Dec 11, 2012 at 03:34:11PM -0800, Tom Warren wrote:
>> This patch series adds basic (boot to cmd prompt) support for Tegra30.
>> This is based on the Tegra20 SPL, which initializes the AVP (ARM7TDMI)
>> boot proc) first, then control is transferred to the CPU (A9 quad cluster).
>> It is based on current u-boot-tegra/next. Some Tegra20 files were
>> changed or moved to enable use of common code/headers.
>>
>> Future patches will add support/drivers for MMC, USB, I2C, SPI, NAND
>> and other peripherals. The Cardhu T30 boards is supported initially.
>>
>
> Booted to command prompt on cardhu with the series, so:
>
> Tested-by: Allen Martin <amartin@nvidia.com>
I read through the series fairly briefly and it looks good to me -
less duplication and should be a good base for the near future. Aside
from the nits already mentioned by Tom/Allen, the series:
Acked-by: Simon Glass <sjg@chromium.org>
Regards,
Simon
>
> --
> nvpublic
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH V3 0/7] Add support for NVIDIA Tegra30 SoC
2012-12-12 22:40 ` Simon Glass
@ 2012-12-12 23:12 ` Tom Warren
0 siblings, 0 replies; 31+ messages in thread
From: Tom Warren @ 2012-12-12 23:12 UTC (permalink / raw)
To: u-boot
Simon,
On Wed, Dec 12, 2012 at 3:40 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi Tom,
>
> On Tue, Dec 11, 2012 at 7:05 PM, Allen Martin <amartin@nvidia.com> wrote:
>> On Tue, Dec 11, 2012 at 03:34:11PM -0800, Tom Warren wrote:
>>> This patch series adds basic (boot to cmd prompt) support for Tegra30.
>>> This is based on the Tegra20 SPL, which initializes the AVP (ARM7TDMI)
>>> boot proc) first, then control is transferred to the CPU (A9 quad cluster).
>>> It is based on current u-boot-tegra/next. Some Tegra20 files were
>>> changed or moved to enable use of common code/headers.
>>>
>>> Future patches will add support/drivers for MMC, USB, I2C, SPI, NAND
>>> and other peripherals. The Cardhu T30 boards is supported initially.
>>>
>>
>> Booted to command prompt on cardhu with the series, so:
>>
>> Tested-by: Allen Martin <amartin@nvidia.com>
>
> I read through the series fairly briefly and it looks good to me -
> less duplication and should be a good base for the near future. Aside
> from the nits already mentioned by Tom/Allen, the series:
>
> Acked-by: Simon Glass <sjg@chromium.org>
Thanks, Appreciate your quick response.
Tom
>
> Regards,
> Simon
>
>>
>> --
>> nvpublic
^ permalink raw reply [flat|nested] 31+ messages in thread