From mboxrd@z Thu Jan 1 00:00:00 1970 From: Donghwa Lee Date: Mon, 17 Dec 2012 10:12:08 +0900 Subject: [U-Boot] [PATCH V2 1/4] EXYNOS5: Change parent clock of FIMD to MPLL In-Reply-To: <50CC0700.6040308@samsung.com> References: <1355398167-24845-1-git-send-email-ajaykumar.rs@samsung.com> <1355398167-24845-2-git-send-email-ajaykumar.rs@samsung.com> <50CC0700.6040308@samsung.com> Message-ID: <50CE7168.9060808@samsung.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 2012? 12? 15? 14:13, Minkyu Kang wrote: > Dear Donghwa, > > On 13/12/12 20:29, Ajay Kumar wrote: >> With VPLL as source clock to FIMD, >> Exynos DP Initializaton was failing sometimes with unstable clock. >> Changing FIMD source to MPLL resolves this issue. >> >> Signed-off-by: Ajay Kumar >> Acked-by: Simon Glass >> --- >> arch/arm/cpu/armv7/exynos/clock.c | 2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c >> index fe61f88..bfcd5f7 100644 >> --- a/arch/arm/cpu/armv7/exynos/clock.c >> +++ b/arch/arm/cpu/armv7/exynos/clock.c >> @@ -603,7 +603,7 @@ void exynos5_set_lcd_clk(void) >> */ >> cfg = readl(&clk->src_disp1_0); >> cfg &= ~(0xf); >> - cfg |= 0x8; >> + cfg |= 0x6; > Please check it. In order to use the configured refresh rate as closely as possible, it is more proper value(MPLL: 0x6) than using VPLL as source clock. Thank you, Donghwa Lee