From mboxrd@z Thu Jan 1 00:00:00 1970 From: Donghwa Lee Date: Fri, 21 Dec 2012 10:46:25 +0900 Subject: [U-Boot] [PATCH RESEND V2 1/4] EXYNOS5: Change parent clock of FIMD to MPLL In-Reply-To: <1356006906-31510-2-git-send-email-ajaykumar.rs@samsung.com> References: <1356006906-31510-1-git-send-email-ajaykumar.rs@samsung.com> <1356006906-31510-2-git-send-email-ajaykumar.rs@samsung.com> Message-ID: <50D3BF71.5060509@samsung.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 2012? 12? 20? 21:35, Ajay Kumar wrote: > With VPLL as source clock to FIMD, > Exynos DP Initializaton was failing sometimes with unstable clock. > Changing FIMD source to MPLL resolves this issue. > > Signed-off-by: Ajay Kumar > Acked-by: Simon Glass > --- > arch/arm/cpu/armv7/exynos/clock.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c > index fe61f88..bfcd5f7 100644 > --- a/arch/arm/cpu/armv7/exynos/clock.c > +++ b/arch/arm/cpu/armv7/exynos/clock.c > @@ -603,7 +603,7 @@ void exynos5_set_lcd_clk(void) > */ > cfg = readl(&clk->src_disp1_0); > cfg &= ~(0xf); > - cfg |= 0x8; > + cfg |= 0x6; > writel(cfg, &clk->src_disp1_0); > > /* It looks good to me. Acked-by: Donghwa Lee Thank you, Donghwa Lee