[U-Boot] [PATCH 2/3] Tegra30: fdt: Update DT files with I2C info for T30/Cardhu

Tom Warren
2012-12-22T00:16:38Z

Note that T30 does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
DVC_I2C is still used to designate the controller intended for
power control (PWR_I2C in the schematics). On Cardhu, it's used
to access the PMU and EEPROM, as well as the audio codec, temp
sensor, and fuel gauge devices from the OS.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
arch/arm/dts/tegra30.dtsi | 61 +++++++++++++++++++++++++++++++++++
board/nvidia/dts/tegra30-cardhu.dts | 41 +++++++++++++++++++++++
2 files changed, 102 insertions(+), 0 deletions(-)

diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index f568d44..664c397 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -2,4 +2,65 @@

/ {
compatible = "nvidia,tegra30";
+
+ tegra_car: clock at 60006000 {
+ compatible = "nvidia,tegra30-car", "nvidia,tegra20-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ i2c at 7000c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000C000 0x100>;
+ /* PERIPH_ID_I2C1, CLK_M */
+ clocks = <&tegra_car 12>;
+ };
+
+ i2c at 7000c400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000C400 0x100>;
+ /* PERIPH_ID_I2C2, CLK_M */
+ clocks = <&tegra_car 54>;
+ };
+
+ i2c at 7000c500 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000C500 0x100>;
+ /* PERIPH_ID_I2C3, CLK_M */
+ clocks = <&tegra_car 67>;
+ };
+
+ i2c at 7000c700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000C700 0x100>;
+ /* PERIPH_ID_I2C4, CLK_M */
+ clocks = <&tegra_car 103>;
+ };
+
+ i2c at 7000d000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000D000 0x100>;
+ /* PERIPH_ID_I2C_DVC, CLK_M */
+ clocks = <&tegra_car 47>;
+ };
};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
index 2345766..4eddde6 100644
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -6,8 +6,49 @@
model = "NVIDIA Cardhu";
compatible = "nvidia,cardhu", "nvidia,tegra30";

+ aliases {
+ i2c0 = "/i2c at 7000d000";
+ i2c1 = "/i2c at 7000c000";
+ i2c2 = "/i2c at 7000c400";
+ i2c3 = "/i2c at 7000c500";
+ i2c4 = "/i2c at 7000c700";
+ };
+
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
+
+ clocks {
+ clk_32k: clk_32K {
+ clock-frequency = <32768>;
+ };
+ osc {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ clock at 60006000 {
+ clocks = <&clk_32k &osc>;
+ };
+
+ i2c at 7000c000 {
+ clock-frequency = <100000>;
+ };
+
+ i2c at 7000c400 {
+ clock-frequency = <100000>;
+ };
+
+ i2c at 7000c500 {
+ clock-frequency = <100000>;
+ };
+
+ i2c at 7000c700 {
+ clock-frequency = <100000>;
+ };
+
+ i2c at 7000d000 {
+ clock-frequency = <100000>;
+ };
};
--
1.7.0.4