From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jaehoon Chung Date: Fri, 11 Jan 2013 12:52:19 +0900 Subject: [U-Boot] [PATCH V4 5/9] EXYNOS5: DWMMC: API to set mmc clock divisor In-Reply-To: References: <1357292050-12137-1-git-send-email-amarendra.xt@samsung.com> <1357292050-12137-6-git-send-email-amarendra.xt@samsung.com> Message-ID: <50EF8C73.8010004@samsung.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 01/11/2013 12:35 AM, Simon Glass wrote: > Hi Amar, > > On Fri, Jan 4, 2013 at 1:34 AM, Amar wrote: >> This API computes the divisor value based on MPLL clock and >> writes it into the FSYS1 register. >> >> Changes from V1: >> 1)Updated the function exynos5_mmc_set_clk_div() to receive >> 'device_i'd as input parameter instead of 'index'. >> >> Changes from V2: >> 1)Updation of commit message and resubmition of proper patch set. >> >> Changes from V3: >> 1)Removed the new API exynos5_mmc_set_clk_div() from clock.c, >> because existing API set_mmc_clk() can be used to set mmc clock. >> >> Signed-off-by: Amar >> --- >> arch/arm/cpu/armv7/exynos/clock.c | 4 ++-- >> arch/arm/include/asm/arch-exynos/clk.h | 3 +++ >> 2 files changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c >> index 973b84e..89574ba 100644 >> --- a/arch/arm/cpu/armv7/exynos/clock.c >> +++ b/arch/arm/cpu/armv7/exynos/clock.c >> @@ -490,7 +490,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) >> (struct exynos4_clock *)samsung_get_base_clock(); >> unsigned long uclk, sclk; >> unsigned int sel, ratio, pre_ratio; >> - int shift; >> + int shift = 0; > > Is this fixing a warning? Maybe..fix the compiler warning.. > >> >> sel = readl(&clk->src_fsys); >> sel = (sel >> (dev_index << 2)) & 0xf; >> @@ -539,7 +539,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) >> (struct exynos5_clock *)samsung_get_base_clock(); >> unsigned long uclk, sclk; >> unsigned int sel, ratio, pre_ratio; >> - int shift; >> + int shift = 0; >> >> sel = readl(&clk->src_fsys); >> sel = (sel >> (dev_index << 2)) & 0xf; >> diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h >> index 1935b0b..a4d5b4e 100644 >> --- a/arch/arm/include/asm/arch-exynos/clk.h >> +++ b/arch/arm/include/asm/arch-exynos/clk.h >> @@ -29,6 +29,9 @@ >> #define VPLL 4 >> #define BPLL 5 >> >> +#define FSYS1_MMC0_DIV_MASK 0xff0f >> +#define FSYS1_MMC0_DIV_VAL 0x0701 > > What is this used for? I don't see it in this patch. > > Overall it is not clear what this patch is for. This define didn't need. That value is not static value, isn't? Best Regards, Jaehoon Chung > >> + >> unsigned long get_pll_clk(int pllreg); >> unsigned long get_arm_clk(void); >> unsigned long get_i2c_clk(void); >> -- >> 1.8.0 >> > > Regards, > Simon >