From mboxrd@z Thu Jan 1 00:00:00 1970 From: R Sricharan Date: Fri, 11 Jan 2013 13:29:02 +0530 Subject: [U-Boot] [PATCH v2 01/10] arm: move flush_dcache_all() to just before disable cache In-Reply-To: <1354316484-23515-1-git-send-email-sjg@chromium.org> References: <1354316484-23515-1-git-send-email-sjg@chromium.org> Message-ID: <50EFC646.3080404@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, On Saturday 01 December 2012 04:31 AM, Simon Glass wrote: > From: Arun Mankuzhi > > In Cortex-A15 architecture, when we run cache invalidate > the cache clean operation executes automatically. > So if there are any dirty cache lines before disabling the L2 cache > these will be synchronized with the main memory when > invalidate_dcache_all() runs in the last part of U-boot > > The two functions after flush_dcache_all is using the stack. So this > data will be on the cache. After disable when invalidate is called the > data will be flushed from cache to memory. This corrupts the stack in > invalida_dcache_all. So this change is required to avoid the u-boot > hang. > > So flush has to be done just before clearing CR_C bit > > Signed-off-by: Arun Mankuzhi > Signed-off-by: Simon Glass > --- > Changes in v2: None > > arch/arm/lib/cache-cp15.c | 5 ++++- > 1 files changed, 4 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c > index 939de10..06119c8 100644 > --- a/arch/arm/lib/cache-cp15.c > +++ b/arch/arm/lib/cache-cp15.c > @@ -124,8 +124,11 @@ static void cache_disable(uint32_t cache_bit) > return; > /* if disabling data cache, disable mmu too */ > cache_bit |= CR_M; > - flush_dcache_all(); > } > + reg = get_cr(); > + cp_delay(); > + if (cache_bit == (CR_C | CR_M)) > + flush_dcache_all(); > set_cr(reg & ~cache_bit); Sorry for the late question. But are the two functions that is after flush_dcache_all currently ? There is only set_cr, which does not use the stack. Regards, Sricharan