[U-Boot] [PATCH 2/7] tegra: spi: add fdt support to tegra SPI SFLASH driver

[Stephen Warren <swarren@wwwdotorg.org>]

On 01/11/2013 11:44 AM, Allen Martin wrote:
> Add support for configuring tegra SPI driver from devicetree.
> Support is keyed off CONFIG_OF_CONTROL.  Add entry in seaboard dts
> file for spi controller to describe seaboard spi.

> diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi

.dtsi changes would typically be in a separate patch.

> +	spi at 7000c380 {
> +		compatible = "nvidia,tegra20-sflash";
> +		reg = <0x7000c380 0x80>;
> +		interrupts = <0 39 0x04>;
> +		nvidia,dma-request-selector = <&apbdma 11>;

> +		spi-max-frequency = <25000000>;

spi-max-frequency is board-specific; it should appear in the board .dts
file not the SoC .dtsi file.

> diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c

> @@ -85,7 +91,41 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
>  	spi->slave.bus = bus;
>  	spi->slave.cs = cs;
>  	spi->freq = max_hz;
> +#ifdef CONFIG_OF_CONTROL
> +	int node = fdtdec_next_compatible(gd->fdt_blob, 0,
> +					  COMPAT_NVIDIA_TEGRA20_SFLASH);

I assume this function gets called once, and hence the line above simply
finds the first sflash node in the device tree. What if there's more
than one node? There certainly can be more than one SPI controller,
although perhaps the sflash controller only has one instance on any
current chip and it's the other IP block ("SPI") that has multiple
instances in practice.