From mboxrd@z Thu Jan  1 00:00:00 1970
From: Vipin Kumar <vipin.kumar@st.com>
Date: Wed, 23 Jan 2013 15:46:31 +0530
Subject: [U-Boot] [PATCH 1/2] drivers/net/designware,
 do an explicit memory access instead of implicit,
 re-written assignments to use readl() and writel(),
 all of this as preperation for making the driver able to work in a cached
 environment (I$D$ support).
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On 1/23/2013 12:25 PM, Albert ARIBAUD wrote:
> Hi Vipin,
>
>> My first feeling is that the descriptors are allocated as Normal
>> Cachabale memory and it would not help to access them using readl/writel
>>
>> Should the desciptors be allocated as non-cachable memory. If yes then
>> how to do that in u-boot
>>
>> I suppose the rest of the code would be better reviewed if we know about
>> this
>>
>> Vipin
>
> I would say that yes, descriptors are allocated in DRAM, so they are
> cacheable.
>
> And no, we don't need to allocate them non-cacheable, although in this
> case we need to use cache flush and invalidate calls. I would suggest
> doing so rather than allocating the descriptors non cacheable, because
> using non-cacheable memory makes the dependency between the driver and
> cache codes implicit (and thus more prone to improperly thought out
> changes in either code) and the memory usage more complex, while
> explicit cache operations make the relationship explicit.
>

Yes, got it. Thanks Albert

Frank, so in that case rather changing the code to use readl/writel, 
cache flush and invalidate operations need to be performed at 
appropriate places

Regards
Vipin

> One can always not cache descriptors if you one wants to, without this
> decision breaking driver functionality.
>
> Amicalement,