From: Gabor Juhos <juhosg@openwrt.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 02/10] MIPS: qemu-malta: add reset support
Date: Sun, 03 Feb 2013 09:02:25 +0100 [thread overview]
Message-ID: <510E1991.10408@openwrt.org> (raw)
In-Reply-To: <CACUy__VWg3LC28qBOpQJSNq49aqb68zA8hTW5Lbg-p6mPQC2xw@mail.gmail.com>
2013.02.02. 20:35 keltez?ssel, Daniel Schwierzeck ?rta:
>> diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c
>> index 9ba711d..9333242 100644
>> --- a/board/qemu-malta/qemu-malta.c
>> +++ b/board/qemu-malta/qemu-malta.c
>> @@ -8,6 +8,9 @@
>>
>> #include <common.h>
>>
>> +#include <asm/io.h>
>> +#include <asm/malta.h>
>> +
>> phys_size_t initdram(int board_type)
>> {
>> return CONFIG_SYS_MEM_SIZE;
>> @@ -18,3 +21,11 @@ int checkboard(void)
>> puts("Board: MIPS Malta CoreLV (Qemu)\n");
>> return 0;
>> }
>> +
>> +void _machine_restart(void)
>> +{
>> + void __iomem *reset_base;
>> +
>> + reset_base = (void __iomem *) CKSEG1ADDR(MALTA_RESET_BASE);
>> + __raw_writel(le32_to_cpu(GORESET), reset_base);
>
> don't you need to swap from CPU endianess to register/bus endinaness?
> I think regisers/bus are always BE and only CPU changes between LE/BE.
> So we either need __raw_writel(cpu_to_be32(v),a) or writel_be32(v,a).
The register uses the same endianness as the CPU, so we have to write either a
LE or BE value depending on the CPU endianness.
This means that we should use the __raw_writel accessor with a plain GORESET
value. That method works in Linux but does not work in U-Boot.
The Malta board needs the CONFIG_SWAP_IO_SPACE for PCI device acccess. If this
config options is set then the __raw_writel accessor will swap the given value
on BE systems. So I have to pre-swap the value with le32_to_cpu to make it
working correctly.
The relevant definitions from 'arch/mips/include/asm/io.h':
> #if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
>
> #define __ioswab8(x) (x)
> #define __ioswab16(x) swab16(x)
> #define __ioswab32(x) swab32(x)
>
> #else
> ...
> #define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b)
> #define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b))
> #define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b))
> #define __raw_writeb writeb
> #define __raw_writew writew
> #define __raw_writel writel
Maybe here is the time to fix these accessors in asm/io.h?
-Gabor
next prev parent reply other threads:[~2013-02-03 8:02 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-02 16:05 [U-Boot] [PATCH v2 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
2013-02-02 16:05 ` [U-Boot] [PATCH v2 01/10] MIPS: qemu-malta: add support for emulated MIPS " Gabor Juhos
2013-02-02 19:34 ` Daniel Schwierzeck
2013-02-03 7:19 ` Gabor Juhos
2013-02-02 16:05 ` [U-Boot] [PATCH v2 02/10] MIPS: qemu-malta: add reset support Gabor Juhos
2013-02-02 19:35 ` Daniel Schwierzeck
2013-02-03 8:02 ` Gabor Juhos [this message]
2013-02-02 16:05 ` [U-Boot] [PATCH v2 03/10] MIPS: qemu-malta: enable flash support Gabor Juhos
2013-02-02 16:06 ` [U-Boot] [PATCH v2 04/10] MIPS: import gt64120.h header from Linux 3.8-rc3 Gabor Juhos
2013-02-02 16:06 ` [U-Boot] [PATCH v2 05/10] MIPS: qemu-malta: setup GT64120 registers as done by YAMON Gabor Juhos
2013-02-02 19:39 ` Daniel Schwierzeck
2013-02-03 8:15 ` Gabor Juhos
2013-02-02 16:06 ` [U-Boot] [PATCH v2 06/10] MIPS: qemu-malta: add PCI support Gabor Juhos
2013-02-02 19:37 ` Daniel Schwierzeck
2013-02-03 8:25 ` Gabor Juhos
2013-02-02 16:06 ` [U-Boot] [PATCH v2 07/10] net: pcnet: use pci_virt_to_mem to obtain buffer addresses Gabor Juhos
2013-02-02 19:42 ` Daniel Schwierzeck
2013-02-05 1:29 ` Nobuhiro Iwamatsu
2013-02-02 16:06 ` [U-Boot] [PATCH v2 08/10] MIPS: qemu-malta: bring up ethernet Gabor Juhos
2013-02-02 16:06 ` [U-Boot] [PATCH v2 09/10] MIPS: bootm.c: add YAMON style Linux preparation/jump code Gabor Juhos
2013-02-02 16:06 ` [U-Boot] [PATCH v2 10/10] MIPS: start.S: emulate REVISION register for qemu-malta Gabor Juhos
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