From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gabor Juhos Date: Sun, 03 Feb 2013 09:15:53 +0100 Subject: [U-Boot] [PATCH v2 05/10] MIPS: qemu-malta: setup GT64120 registers as done by YAMON In-Reply-To: References: <1359821166-32352-1-git-send-email-juhosg@openwrt.org> <1359821166-32352-6-git-send-email-juhosg@openwrt.org> Message-ID: <510E1CB9.9030205@openwrt.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de 2013.02.02. 20:39 keltez?ssel, Daniel Schwierzeck ?rta: > 2013/2/2 Gabor Juhos : >> Move the GT64120 register base to 0x1be00000 >> and setup PCI BAR registers as done by the >> original YAMON bootloader. >> >> This is needed for running Linux kernel. >> >> Signed-off-by: Gabor Juhos >> Cc: Daniel Schwierzeck >> --- >> Changes since v1: >> - rebased against mips/testing >> >> Changes since RFC: --- >> --- >> arch/mips/include/asm/malta.h | 4 ++- >> board/qemu-malta/lowlevel_init.S | 51 ++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 54 insertions(+), 1 deletion(-) >> >> diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h >> index ab951e6..d4d44a2 100644 >> --- a/arch/mips/include/asm/malta.h >> +++ b/arch/mips/include/asm/malta.h >> @@ -9,10 +9,12 @@ >> #ifndef _MIPS_ASM_MALTA_H >> #define _MIPS_ASM_MALTA_H >> >> -#define MALTA_IO_PORT_BASE 0x10000000 >> +#define MALTA_IO_PORT_BASE 0x18000000 >> >> #define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8) >> >> +#define MALTA_GT_BASE 0x1be00000 >> + >> #define MALTA_RESET_BASE 0x1f000500 >> #define GORESET 0x42 >> >> diff --git a/board/qemu-malta/lowlevel_init.S b/board/qemu-malta/lowlevel_init.S >> index c5c5bd9..11544a8 100644 >> --- a/board/qemu-malta/lowlevel_init.S >> +++ b/board/qemu-malta/lowlevel_init.S >> @@ -6,7 +6,19 @@ >> * by the Free Software Foundation. >> */ >> >> +#include >> +#include >> #include >> +#include >> +#include >> + >> +#ifdef CONFIG_SYS_BIG_ENDIAN >> +#define CPU_TO_GT32(_x) ((_x)) >> +#else >> +#define CPU_TO_GT32(_x) ( \ >> + (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ >> + (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) >> +#endif >> >> .text >> .set noreorder >> @@ -15,5 +27,44 @@ >> .globl lowlevel_init >> lowlevel_init: >> >> + /* >> + * Load BAR registers of GT64120 as done by YAMON >> + * >> + * based on a patch sent by Antony Pavlov >> + * to the barebox mailing list. >> + * The subject of the original patch: >> + * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' >> + * URL: >> + * http://www.mail-archive.com/barebox at lists.infradead.org/msg06128.html >> + * >> + * based on write_bootloader() in qemu.git/hw/mips_malta.c >> + * see GT64120 manual and qemu.git/hw/gt64xxx.c for details >> + */ >> + >> + /* move GT64120 registers from 0x14000000 to 0x1be00000 */ >> + li t1, KSEG1ADDR(GT_DEF_BASE) >> + li t0, CPU_TO_GT32(0xdf000000) >> + sw t0, GT_ISD_OFS(t1) >> + >> + /* setup MEM-to-PCI0 mapping */ >> + li t1, KSEG1ADDR(MALTA_GT_BASE) >> + >> + /* setup PCI0 io window to 0x18000000-0x181fffff */ >> + li t0, CPU_TO_GT32(0xc0000000) >> + sw t0, GT_PCI0IOLD_OFS(t1) >> + li t0, CPU_TO_GT32(0x40000000) >> + sw t0, GT_PCI0IOHD_OFS(t1) >> + >> + /* setup PCI0 mem windows */ >> + li t0, CPU_TO_GT32(0x80000000) >> + sw t0, GT_PCI0M0LD_OFS(t1) >> + li t0, CPU_TO_GT32(0x3f000000) >> + sw t0, GT_PCI0M0HD_OFS(t1) >> + >> + li t0, CPU_TO_GT32(0xc1000000) >> + sw t0, GT_PCI0M1LD_OFS(t1) >> + li t0, CPU_TO_GT32(0x5e000000) >> + sw t0, GT_PCI0M1HD_OFS(t1) >> + >> jr ra >> nop >> -- >> 1.7.10 >> > > is this initialization really needed before relocation? If not this should be > moved to pci_init_board() After this initialization, the UART uses a different base address. If we want UART output before the relocation then we have to initialize it here. -Gabor