From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laxman Dewangan Date: Tue, 12 Feb 2013 17:32:26 +0530 Subject: [U-Boot] [PATCH v3 2/3] Tegra114: fdt: Update DT files with I2C info for T114/Dalmore In-Reply-To: <51153E16.7010805@wwwdotorg.org> References: <1360344332-14664-1-git-send-email-twarren@nvidia.com> <1360344332-14664-3-git-send-email-twarren@nvidia.com> <51153E16.7010805@wwwdotorg.org> Message-ID: <511A2F52.2050606@nvidia.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Friday 08 February 2013 11:34 PM, Stephen Warren wrote: > On 02/08/2013 10:25 AM, Tom Warren wrote: >> T114, like T30, does not have a separate/different DVC (power I2C) >> controller like T20 - all 5 I2C controllers are identical, but >> I2C5 is used to designate the controller intended for power >> control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz. >> diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts >> + aliases { >> + }; >> + > There's no point adding an empty aliases node here. Feel free to fix > that up when you apply it rather than reposting if you want. > > I'd like too see Laxman sign-off on the "*2" question he had earlier > before actually checking this in. > We do not require *2 as the i2c clock divider is DIVU16 type. There was bug in early code on kernel also which we fixed in dowstream long back. Possibly uboot have not fixed this yet. ----------------------------------------------------------------------------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. -----------------------------------------------------------------------------------