From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Tue, 12 Feb 2013 13:53:46 +0100 Subject: [U-Boot] [PATCH 1/6] imx: mx6q DDR3 init: Fix tMRD In-Reply-To: <1359580758-20743-1-git-send-email-benoit.thebaudeau@advansee.com> References: <1359580758-20743-1-git-send-email-benoit.thebaudeau@advansee.com> Message-ID: <511A3B5A.5080604@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 30/01/2013 22:19, Beno?t Th?baudeau wrote: > MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3. > > For all DDR3 speed bins: > tMRD(min) = 4 nCK > tMOD(min) = max(12 nCK, 15 ns) > > Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK > at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5]. > > Signed-off-by: Beno?t Th?baudeau > --- > board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg > index c86cd40..9ac8027 100644 > --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg > +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg > @@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740 > > DATA 4 0x021b001c 0x00008000 > DATA 4 0x021b000c 0x555A7975 > -DATA 4 0x021b0010 0xFF538E64 > +DATA 4 0x021b0010 0xFF538F64 > DATA 4 0x021b0014 0x01FF00DB > DATA 4 0x021b002c 0x000026D2 > Applied (whole series) to u-boot-imx, thanks. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================