[U-Boot] [PATCH 4/6] imx: mx6q DDR3 init: Fix RST_to_CKE

Benoît Thébaudeau
2013-01-30T21:19:16Z

MMDC1_MDOR.RST_to_CKE should be set to 500 ?s according to the JEDEC
specification for DDR3. With a cycle of 15.258 ?s, this gives 33 cycles encoded
as 0x23 for the bit-field MMDC1_MDOR[5:0].

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 73317b5..51f8c35 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b002c 0x000026D2

-DATA 4 0x021b0030 0x005A1021
+DATA 4 0x021b0030 0x005A1023
DATA 4 0x021b0008 0x09444040
DATA 4 0x021b0004 0x00025576
DATA 4 0x021b0040 0x00000027
--
1.7.10.4