[U-Boot] [PATCH v5 0/4] Tegra: MMC: Add DT support for MMC to T20 boards

[U-Boot] [PATCH v5 0/4] Tegra: MMC: Add DT support for MMC to T20 boards

[Tom Warren]

This patchset adds device-tree support to the Tegra MMC driver.
All device config is done via properties in the DT files instead
of hard-coded config options/function arguments.

I've tested this on my Seaboard and everything works fine,
including card detect. For the other T20 boards, I've used
the Linux kernel DTS files for the sdhci nodes where there
wasn't one already, or expanded the info that was already
there. Everything builds fine, but I haven't tested anything
but Seaboard.

v2: Changes as per Stephen's & Simon's review
v3: Changes as per Stephen/Lucas/Thierry/Simon's feedback
v4: Additional changes as per Stephen/Lucas/Thierry/Simon
v5: Additional changes as per Stephen/Lucas/Andy

Tom Warren (4):
  fdt: add dts/dtsi arch & board include paths to DTS_CPPFLAGS
  Tegra: fdt: tamonten: Add common tamonten.dtsi file from linux
  Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files
  Tegra: MMC: Add DT support to MMC driver for all T20 boards

 arch/arm/dts/tegra114.dtsi                        |    2 +-
 arch/arm/dts/tegra20.dtsi                         |   18 +-
 arch/arm/dts/tegra30.dtsi                         |    2 +-
 arch/arm/include/asm/arch-tegra/mmc.h             |    2 +-
 arch/arm/include/asm/arch-tegra/tegra_mmc.h       |   13 +-
 board/avionic-design/common/tamonten.c            |   19 +-
 board/avionic-design/dts/tegra20-medcom-wide.dts  |    3 +-
 board/avionic-design/dts/tegra20-plutux.dts       |    3 +-
 board/avionic-design/dts/tegra20-tamonten.dtsi    |  489 +++++++++++++++++++++
 board/avionic-design/dts/tegra20-tec.dts          |    3 +-
 board/compal/dts/tegra20-paz00.dts                |   21 +-
 board/compal/paz00/paz00.c                        |   26 +-
 board/compulab/dts/tegra20-trimslice.dts          |   16 +-
 board/compulab/trimslice/trimslice.c              |   23 +-
 board/nvidia/common/board.c                       |   25 +
 board/nvidia/dts/tegra114-dalmore.dts             |    2 +-
 board/nvidia/dts/tegra20-harmony.dts              |   20 +-
 board/nvidia/dts/tegra20-seaboard.dts             |   12 +-
 board/nvidia/dts/tegra20-ventana.dts              |   17 +-
 board/nvidia/dts/tegra20-whistler.dts             |   15 +-
 board/nvidia/dts/tegra30-cardhu.dts               |    2 +-
 board/nvidia/harmony/harmony.c                    |   26 +-
 board/nvidia/seaboard/seaboard.c                  |   25 +-
 board/nvidia/whistler/whistler.c                  |   30 +-
 board/toradex/colibri_t20_iris/colibri_t20_iris.c |   11 +-
 board/toradex/dts/tegra20-colibri_t20_iris.dts    |    9 +-
 drivers/mmc/tegra_mmc.c                           |  179 +++++---
 dts/Makefile                                      |    3 +-
 include/fdtdec.h                                  |    1 +
 lib/fdtdec.c                                      |    1 +
 30 files changed, 785 insertions(+), 233 deletions(-)
 create mode 100644 board/avionic-design/dts/tegra20-tamonten.dtsi

[U-Boot] [PATCH v5 1/4] fdt: Add dts/dtsi arch & board include paths to DTS_CPPFLAGS

[Tom Warren]

This allows the use of '#include "xyz"' in the dts/dtsi file which
helps the C preprocessor find common dtsi include files.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
v4: new
v5: Add dts/dtsi paths to DTS_CPPFLAGS instead of DTC command line

 dts/Makefile |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/dts/Makefile b/dts/Makefile
index 922c78c..6f36153 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -38,7 +38,8 @@ Please define CONFIG_ARCH_DEVICE_TREE))
 # We preprocess the device tree file provide a useful define
 DTS_CPPFLAGS := -x assembler-with-cpp \
 		-DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" \
-		-DBOARD_DTS=\"$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\"
+		-DBOARD_DTS=\"$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\" \
+		-I$(SRCTREE)/board/$(VENDOR)/dts -I$(SRCTREE)/arch/$(ARCH)/dts
 
 all:	$(obj).depend $(LIB)
 
-- 
1.7.0.4

[U-Boot] [PATCH v5 2/4] Tegra: fdt: tamonten: Add common tamonten.dtsi file from linux

[Tom Warren]

Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Thierry Reding <thierry.reding@avionic-design.de>
---
v3: new
v4: no change
v5: change /include/ to #include

 board/avionic-design/dts/tegra20-tamonten.dtsi |  489 ++++++++++++++++++++++++
 1 files changed, 489 insertions(+), 0 deletions(-)
 create mode 100644 board/avionic-design/dts/tegra20-tamonten.dtsi

diff --git a/board/avionic-design/dts/tegra20-tamonten.dtsi b/board/avionic-design/dts/tegra20-tamonten.dtsi
new file mode 100644
index 0000000..073ac04
--- /dev/null
+++ b/board/avionic-design/dts/tegra20-tamonten.dtsi
@@ -0,0 +1,489 @@
+#include ARCH_CPU_DTS
+
+/ {
+	model = "Avionic Design Tamonten SOM";
+	compatible = "ad,tamonten", "nvidia,tegra20";
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	host1x {
+		hdmi {
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+		};
+	};
+
+	pinmux {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+					"spia", "spib", "spic";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			dta {
+				nvidia,pins = "dta", "dtd";
+				nvidia,function = "sdio2";
+			};
+			dtb {
+				nvidia,pins = "dtb", "dtc", "dte";
+				nvidia,function = "rsvd1";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uarta";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+					"ld3", "ld4", "ld5", "ld6", "ld7",
+					"ld8", "ld9", "ld10", "ld11", "ld12",
+					"ld13", "ld14", "ld15", "ld16", "ld17",
+					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
+					"lhs", "lm0", "lm1", "lpp", "lpw0",
+					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
+					"lvs";
+				nvidia,function = "displaya";
+			};
+			owc {
+				nvidia,pins = "owc", "spdi", "spdo", "uac";
+				nvidia,function = "rsvd2";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "pwm";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxc {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "spdif";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+					"cdev1", "cdev2", "dap1", "dtb", "gma",
+					"gmb", "gmc", "gmd", "gme", "gpu7",
+					"gpv", "i2cp", "pta", "rm", "slxa",
+					"slxk", "spia", "spib", "uac";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <0>;
+			};
+			conf_csus {
+				nvidia,pins = "csus", "spid", "spif";
+				nvidia,pull = <1>;
+				nvidia,tristate = <1>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+					"dtc", "dte", "dtf", "gpu", "sdio1",
+					"slxc", "slxd", "spdi", "spdo", "spig",
+					"uda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			conf_ddc {
+				nvidia,pins = "ddc", "dta", "dtd", "kbca",
+					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+					"sdc";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
+					"lvp0", "owc", "sdb";
+				nvidia,tristate = <1>;
+			};
+			conf_irrx {
+				nvidia,pins = "irrx", "irtx", "sdd", "spic",
+					"spie", "spih", "uaa", "uab", "uad",
+					"uca", "ucb";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <2>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+					"lvs", "pmc";
+				nvidia,tristate = <0>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <1>;
+			};
+		};
+
+		state_i2cmux_ddc: pinmux_i2cmux_ddc {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+			};
+		};
+
+		state_i2cmux_pta: pinmux_i2cmux_pta {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "i2c2";
+			};
+		};
+
+		state_i2cmux_idle: pinmux_i2cmux_idle {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+			};
+		};
+	};
+
+	i2s at 70002800 {
+		status = "okay";
+	};
+
+	serial at 70006300 {
+		status = "okay";
+	};
+
+	i2c at 7000c000 {
+		clock-frequency = <400000>;
+		status = "okay";
+	};
+
+	i2c at 7000c400 {
+		clock-frequency = <100000>;
+		status = "okay";
+	};
+
+	i2cmux {
+		compatible = "i2c-mux-pinctrl";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c-parent = <&{/i2c@7000c400}>;
+
+		pinctrl-names = "ddc", "pta", "idle";
+		pinctrl-0 = <&state_i2cmux_ddc>;
+		pinctrl-1 = <&state_i2cmux_pta>;
+		pinctrl-2 = <&state_i2cmux_idle>;
+
+		hdmi_ddc: i2c at 0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c at 1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	i2c at 7000d000 {
+		clock-frequency = <400000>;
+		status = "okay";
+
+		pmic: tps6586x at 34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <0 86 0x4>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				sys_reg: sys {
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				sm0 {
+					regulator-name = "vdd_sys_sm0,vdd_core";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				sm1 {
+					regulator-name = "vdd_sys_sm1,vdd_cpu";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: sm2 {
+					regulator-name = "vdd_sys_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				ldo0 {
+					regulator-name = "vdd_ldo0,vddio_pex_clk";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				ldo1 {
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				ldo2 {
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				ldo3 {
+					regulator-name = "vdd_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo4 {
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5 {
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+				};
+
+				ldo6 {
+					regulator-name = "vdd_ldo6,avdd_vdac";
+					/*
+					 * According to the Tegra 2 Automotive
+					 * DataSheet, a typical value for this
+					 * would be 2.8V, but the PMIC only
+					 * supports 2.85V.
+					 */
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+				};
+
+				hdmi_vdd_reg: ldo7 {
+					regulator-name = "vdd_ldo7,avdd_hdmi";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				hdmi_pll_reg: ldo8 {
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo9 {
+					regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
+					/*
+					 * According to the Tegra 2 Automotive
+					 * DataSheet, a typical value for this
+					 * would be 2.8V, but the PMIC only
+					 * supports 2.85V.
+					 */
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo_rtc {
+					regulator-name = "vdd_rtc_out";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		temperature-sensor at 4c {
+			compatible = "onnn,nct1008";
+			reg = <0x4c>;
+		};
+	};
+
+	pmc {
+		nvidia,invert-interrupt;
+	};
+
+	usb at c5008000 {
+		status = "okay";
+	};
+
+	sdhci at c8000600 {
+		cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+		bus-width = <4>;
+		status = "okay";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator at 0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+	};
+};
-- 
1.7.0.4

[U-Boot] [PATCH v5 3/4] Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files

[Tom Warren]

Linux dts files were used for those boards that didn't already
have sdhci info populated. Tamonten has their own dtsi file with
common sdhci nodes (sourced from Linux).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
---
v2:
- cleanup comments in dts files/match w/kernel files
- add sdhci aliases in all dts files
- use tegra20-tamonten.dtsi from the kernel for AD boards
v3:
- include tamonten.dtsi file directly in AD dts files
- fix Seaboard power-gpios flags
- add cd-gpios for Colibri T20 Iris
- add include paths to DTC command
v4:
- move dts Makefile change to separate patch
v5:
- change /include/ to #include, allows C preprocessor to find files

 arch/arm/dts/tegra114.dtsi                       |    2 +-
 arch/arm/dts/tegra20.dtsi                        |   18 +++++++++++++-----
 arch/arm/dts/tegra30.dtsi                        |    2 +-
 board/avionic-design/dts/tegra20-medcom-wide.dts |    3 ++-
 board/avionic-design/dts/tegra20-plutux.dts      |    3 ++-
 board/avionic-design/dts/tegra20-tec.dts         |    3 ++-
 board/compal/dts/tegra20-paz00.dts               |   21 ++++++++++++++++++---
 board/compulab/dts/tegra20-trimslice.dts         |   16 +++++++++++++++-
 board/nvidia/dts/tegra114-dalmore.dts            |    2 +-
 board/nvidia/dts/tegra20-harmony.dts             |   20 +++++++++++++++++++-
 board/nvidia/dts/tegra20-seaboard.dts            |   12 ++++++++----
 board/nvidia/dts/tegra20-ventana.dts             |   17 ++++++++++++++++-
 board/nvidia/dts/tegra20-whistler.dts            |   15 ++++++++++++++-
 board/nvidia/dts/tegra30-cardhu.dts              |    2 +-
 board/toradex/dts/tegra20-colibri_t20_iris.dts   |    9 ++++++++-
 15 files changed, 121 insertions(+), 24 deletions(-)

diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index d06cd12..ee08962 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "nvidia,tegra114";
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 9a89685..3805750 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "nvidia,tegra20";
@@ -318,24 +318,32 @@
 	sdhci at c8000000 {
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000000 0x200>;
-		interrupts = < 46 >;
+		interrupts = <0 14 0x04>;
+		clocks = <&tegra_car 14>;
+		status = "disabled";
 	};
 
 	sdhci at c8000200 {
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000200 0x200>;
-		interrupts = < 47 >;
+		interrupts = <0 15 0x04>;
+		clocks = <&tegra_car 9>;
+		status = "disabled";
 	};
 
 	sdhci at c8000400 {
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000400 0x200>;
-		interrupts = < 51 >;
+		interrupts = <0 19 0x04>;
+		clocks = <&tegra_car 69>;
+		status = "disabled";
 	};
 
 	sdhci at c8000600 {
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000600 0x200>;
-		interrupts = < 63 >;
+		interrupts = <0 31 0x04>;
+		clocks = <&tegra_car 15>;
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index 7b8126f..561c617 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "nvidia,tegra30";
diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts
index e46afbe..a9a07f9 100644
--- a/board/avionic-design/dts/tegra20-medcom-wide.dts
+++ b/board/avionic-design/dts/tegra20-medcom-wide.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20-tamonten.dtsi"
 
 / {
 	model = "Avionic Design Medcom-Wide";
@@ -8,6 +8,7 @@
 
 	aliases {
 		usb0 = "/usb at c5008000";
+		sdhci0 = "/sdhci at c8000600";
 	};
 
 	memory {
diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts
index 3e6cce0..20016f2 100644
--- a/board/avionic-design/dts/tegra20-plutux.dts
+++ b/board/avionic-design/dts/tegra20-plutux.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20-tamonten.dtsi"
 
 / {
 	model = "Avionic Design Plutux";
@@ -8,6 +8,7 @@
 
 	aliases {
 		usb0 = "/usb at c5008000";
+		sdhci0 = "/sdhci at c8000600";
 	};
 
 	memory {
diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts
index bf3ff1d..1d7cf89 100644
--- a/board/avionic-design/dts/tegra20-tec.dts
+++ b/board/avionic-design/dts/tegra20-tec.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20-tamonten.dtsi"
 
 / {
 	model = "Avionic Design Tamonten Evaluation Carrier";
@@ -8,6 +8,7 @@
 
 	aliases {
 		usb0 = "/usb at c5008000";
+		sdhci0 = "/sdhci at c8000600";
 	};
 
 	memory {
diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts
index 31b064d..6041f29 100644
--- a/board/compal/dts/tegra20-paz00.dts
+++ b/board/compal/dts/tegra20-paz00.dts
@@ -1,13 +1,15 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include ARCH_CPU_DTS
 
 / {
-        model = "Toshiba AC100 / Dynabook AZ";
-        compatible = "compal,paz00", "nvidia,tegra20";
+	model = "Toshiba AC100 / Dynabook AZ";
+	compatible = "compal,paz00", "nvidia,tegra20";
 
 	aliases {
 		usb0 = "/usb at c5008000";
+		sdhci0 = "/sdhci at c8000600";
+		sdhci1 = "/sdhci at c8000000";
 	};
 
 	memory {
@@ -53,6 +55,19 @@
 		status = "disabled";
 	};
 
+	sdhci at c8000000 {
+		status = "okay";
+		cd-gpios = <&gpio 173 0>; /* gpio PV5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 169 0>; /* gpio PV1 */
+		bus-width = <4>;
+	};
+
+	sdhci at c8000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
 	lcd_panel: panel {
 		/* PAZ00 has 1024x600 */
 		clock = <54030000>;
diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts
index 7aeed67..929e12e 100644
--- a/board/compulab/dts/tegra20-trimslice.dts
+++ b/board/compulab/dts/tegra20-trimslice.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include ARCH_CPU_DTS
 
 / {
 	model = "Compulab TrimSlice board";
@@ -9,6 +9,8 @@
 	aliases {
 		usb0 = "/usb at c5008000";
 		usb1 = "/usb at c5000000";
+		sdhci0 = "/sdhci at c8000600";
+		sdhci1 = "/sdhci at c8000000";
 	};
 
 	memory {
@@ -47,4 +49,16 @@
 	usb at c5004000 {
 		status = "disabled";
 	};
+
+	sdhci at c8000000 {
+		status = "okay";
+		bus-width = <4>;
+	};
+
+	sdhci at c8000600 {
+		status = "okay";
+		cd-gpios = <&gpio 121 0>; /* gpio PP1 */
+		wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+		bus-width = <4>;
+	};
 };
diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts
index 7315577..a3e7863 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include ARCH_CPU_DTS
 
 / {
 	model = "NVIDIA Dalmore";
diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts
index aeda3a1..d2952f8 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include ARCH_CPU_DTS
 
 / {
 	model = "NVIDIA Tegra20 Harmony evaluation board";
@@ -9,6 +9,8 @@
 	aliases {
 		usb0 = "/usb at c5008000";
 		usb1 = "/usb at c5004000";
+		sdhci0 = "/sdhci at c8000600";
+		sdhci1 = "/sdhci at c8000200";
 	};
 
 	memory {
@@ -52,4 +54,20 @@
 	usb at c5004000 {
 		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
 	};
+
+	sdhci at c8000200 {
+		status = "okay";
+		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 155 0>; /* gpio PT3 */
+		bus-width = <4>;
+	};
+
+	sdhci at c8000600 {
+		status = "okay";
+		cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		bus-width = <8>;
+	};
 };
diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
index 527a296..9e96761 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
 /memreserve/ 0x1c000000 0x04000000;
-/include/ ARCH_CPU_DTS
+#include ARCH_CPU_DTS
 
 / {
 	model = "NVIDIA Seaboard";
@@ -12,14 +12,15 @@
 	};
 
 	aliases {
-		/* This defines the order of our USB ports */
+		/* This defines the order of our ports */
 		usb0 = "/usb at c5008000";
 		usb1 = "/usb at c5000000";
-
 		i2c0 = "/i2c at 7000d000";
 		i2c1 = "/i2c at 7000c000";
 		i2c2 = "/i2c at 7000c400";
 		i2c3 = "/i2c at 7000c500";
+		sdhci0 = "/sdhci at c8000600";
+		sdhci1 = "/sdhci at c8000400";
 	};
 
 	memory {
@@ -156,13 +157,16 @@
 	};
 
 	sdhci at c8000400 {
+		status = "okay";
 		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		bus-width = <4>;
 	};
 
 	sdhci at c8000600 {
-		support-8bit;
+		status = "okay";
+		bus-width = <8>;
 	};
 
 	lcd_panel: panel {
diff --git a/board/nvidia/dts/tegra20-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts
index 3e5e39d..86dfcc7 100644
--- a/board/nvidia/dts/tegra20-ventana.dts
+++ b/board/nvidia/dts/tegra20-ventana.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include ARCH_CPU_DTS
 
 / {
 	model = "NVIDIA Tegra20 Ventana evaluation board";
@@ -8,6 +8,8 @@
 
 	aliases {
 		usb0 = "/usb at c5008000";
+		sdhci0 = "/sdhci at c8000600";
+		sdhci1 = "/sdhci at c8000400";
 	};
 
 	memory {
@@ -41,4 +43,17 @@
 	usb at c5004000 {
 		status = "disabled";
 	};
+
+	sdhci at c8000400 {
+		status = "okay";
+		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		bus-width = <4>;
+	};
+
+	sdhci at c8000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
 };
diff --git a/board/nvidia/dts/tegra20-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts
index 4579557..47063f1 100644
--- a/board/nvidia/dts/tegra20-whistler.dts
+++ b/board/nvidia/dts/tegra20-whistler.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include ARCH_CPU_DTS
 
 / {
 	model = "NVIDIA Tegra20 Whistler evaluation board";
@@ -9,6 +9,8 @@
 	aliases {
 		i2c0 = "/i2c at 7000d000";
 		usb0 = "/usb at c5008000";
+		sdhci0 = "/sdhci at c8000600";
+		sdhci1 = "/sdhci at c8000400";
 	};
 
 	memory {
@@ -57,4 +59,15 @@
 	usb at c5004000 {
 		status = "disabled";
 	};
+
+	sdhci at c8000400 {
+		status = "okay";
+		wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+		bus-width = <8>;
+	};
+
+	sdhci at c8000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
 };
diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
index f9f80c5..f7ea07a 100644
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
 /memreserve/ 0x1c000000 0x04000000;
-/include/ ARCH_CPU_DTS
+#include ARCH_CPU_DTS
 
 / {
 	model = "NVIDIA Cardhu";
diff --git a/board/toradex/dts/tegra20-colibri_t20_iris.dts b/board/toradex/dts/tegra20-colibri_t20_iris.dts
index c29b43a..4e915c7 100644
--- a/board/toradex/dts/tegra20-colibri_t20_iris.dts
+++ b/board/toradex/dts/tegra20-colibri_t20_iris.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include ARCH_CPU_DTS
 
 / {
 	model = "Toradex Colibri T20";
@@ -10,6 +10,7 @@
 		usb0 = "/usb at c5008000";
 		usb1 = "/usb at c5000000";
 		usb2 = "/usb at c5004000";
+		sdhci0 = "/sdhci at c8000600";
 	};
 
 	usb at c5000000 {
@@ -35,4 +36,10 @@
 			compatible = "nand-flash";
 		};
 	};
+
+	sdhci at c8000600 {
+		status = "okay";
+		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+		bus-width = <4>;
+	};
 };
-- 
1.7.0.4

[U-Boot] [PATCH v5 4/4] Tegra: MMC: Add DT support to MMC driver for all T20 boards

[Tom Warren]

tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc.
Tested on Seaboard, fully functional.

Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
---
v2:
- all boards now call tegra_mmc_init once, w/no params
- count MMC controllers, not aliases
- AD boards (medcom/plutux/tec) use common tegra20-tamonten.dtsi
v3:
- move any power init inside board's pin_mux_mmc function, and/or
 create pin_mux_mmc function if necessary.
- move board_mmc_init out of each board file and into ../common/board.c
v4:
- remove #ifdef CONFIG_TEGRA_MMC from trimslice.c
- fix minor whitespace issue in board/nvidia/common/board.c
- remove marking of used node_list entries in MMC driver, not needed
v5:
- restore previous debug statements, remove any new ones
- fix pwr_gpio/cd_gpio initialization in do_mmc_init
- update copyright to 2013

 arch/arm/include/asm/arch-tegra/mmc.h             |    2 +-
 arch/arm/include/asm/arch-tegra/tegra_mmc.h       |   13 +-
 board/avionic-design/common/tamonten.c            |   19 +--
 board/compal/paz00/paz00.c                        |   26 +---
 board/compulab/trimslice/trimslice.c              |   23 +---
 board/nvidia/common/board.c                       |   25 +++
 board/nvidia/harmony/harmony.c                    |   26 +---
 board/nvidia/seaboard/seaboard.c                  |   25 +---
 board/nvidia/whistler/whistler.c                  |   30 +---
 board/toradex/colibri_t20_iris/colibri_t20_iris.c |   11 +-
 drivers/mmc/tegra_mmc.c                           |  179 ++++++++++++++-------
 include/fdtdec.h                                  |    1 +
 lib/fdtdec.c                                      |    1 +
 13 files changed, 173 insertions(+), 208 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra/mmc.h b/arch/arm/include/asm/arch-tegra/mmc.h
index 5c95047..71ad407 100644
--- a/arch/arm/include/asm/arch-tegra/mmc.h
+++ b/arch/arm/include/asm/arch-tegra/mmc.h
@@ -22,6 +22,6 @@
 #ifndef _TEGRA_MMC_H_
 #define _TEGRA_MMC_H_
 
-int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
+void tegra_mmc_init(void);
 
 #endif /* _TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index dd746ca..bd18f5f 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -27,6 +27,8 @@
 #define TEGRA_SDMMC3_BASE	0xC8000400
 #define TEGRA_SDMMC4_BASE	0xC8000600
 
+#define MAX_HOSTS		4	/* Max number of 'hosts'/controllers */
+
 #ifndef __ASSEMBLY__
 struct tegra_mmc {
 	unsigned int	sysad;		/* _SYSTEM_ADDRESS_0 */
@@ -119,12 +121,15 @@ struct tegra_mmc {
 
 struct mmc_host {
 	struct tegra_mmc *reg;
+	int id;			/* device id/number, 0-3 */
+	int enabled;		/* 1 to enable, 0 to disable */
+	int width;		/* Bus Width, 1, 4 or 8 */
+	enum periph_id mmc_id;	/* Peripheral ID: PERIPH_ID_... */
+	struct fdt_gpio_state cd_gpio;		/* Change Detect GPIO */
+	struct fdt_gpio_state pwr_gpio;		/* Power GPIO */
+	struct fdt_gpio_state wp_gpio;		/* Write Protect GPIO */
 	unsigned int version;	/* SDHCI spec. version */
 	unsigned int clock;	/* Current clock (MHz) */
-	unsigned int base;	/* Base address, SDMMC1/2/3/4 */
-	enum periph_id mmc_id;	/* Peripheral ID: PERIPH_ID_... */
-	int pwr_gpio;		/* Power GPIO */
-	int cd_gpio;		/* Change Detect GPIO */
 };
 
 #endif	/* __ASSEMBLY__ */
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index e6a932e..ea95e43 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -33,13 +33,8 @@
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/arch-tegra/sys_proto.h>
 #include <asm/arch-tegra/uart.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
-
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 void gpio_early_init(void)
@@ -54,7 +49,7 @@ void gpio_early_init(void)
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
+void pin_mux_mmc(void)
 {
 	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
 	/* for write-protect GPIO PI6 */
@@ -62,16 +57,4 @@ static void pin_mux_mmc(void)
 	/* for CD GPIO PH2 */
 	pinmux_tristate_disable(PINGRP_ATD);
 }
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-	/* Enable muxes, etc. for SDMMC controllers */
-	pin_mux_mmc();
-
-	/* init dev 0, SD slot, with 4-bit bus */
-	tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
-
-	return 0;
-}
 #endif
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index 1447f47..d6e5c37 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -18,19 +18,14 @@
 #include <asm/io.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/gpio.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
-
 
 #ifdef CONFIG_TEGRA_MMC
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
+void pin_mux_mmc(void)
 {
 	/* SDMMC4: config 3, x8 on 2nd set of pins */
 	pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
@@ -51,25 +46,6 @@ static void pin_mux_mmc(void)
 	/* For CD GPIO PV5 */
 	pinmux_tristate_disable(PINGRP_GPV);
 }
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-	debug("board_mmc_init called\n");
-
-	/* Enable muxes, etc. for SDMMC controllers */
-	pin_mux_mmc();
-
-	debug("board_mmc_init: init eMMC\n");
-	/* init dev 0, eMMC chip, with 8-bit bus */
-	tegra_mmc_init(0, 8, -1, -1);
-
-	debug("board_mmc_init: init SD slot\n");
-	/* init dev 3, SD slot, with 4-bit bus */
-	tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
-
-	return 0;
-}
 #endif
 
 #ifdef CONFIG_LCD
diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c
index 8f4dd09..8401100 100644
--- a/board/compulab/trimslice/trimslice.c
+++ b/board/compulab/trimslice/trimslice.c
@@ -27,12 +27,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/gpio.h>
 #include <i2c.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
 
 void pin_mux_usb(void)
 {
@@ -52,7 +48,7 @@ void pin_mux_spi(void)
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
+void pin_mux_mmc(void)
 {
 	funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT);
 	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
@@ -60,20 +56,3 @@ static void pin_mux_mmc(void)
 	/* For CD GPIO PP1 */
 	pinmux_tristate_disable(PINGRP_DAP3);
 }
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-	debug("board_mmc_init called\n");
-
-	/* Enable muxes, etc. for SDMMC controllers */
-	pin_mux_mmc();
-
-	/* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */
-	tegra_mmc_init(0, 4, -1, GPIO_PP1);
-
-	/* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */
-	tegra_mmc_init(3, 4, -1, -1);
-
-	return 0;
-}
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index d1d8a29..474a4a2 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -48,6 +48,9 @@
 #ifdef CONFIG_USB_EHCI_TEGRA
 #include <asm/arch/usb.h>
 #endif
+#ifdef CONFIG_TEGRA_MMC
+#include <asm/arch-tegra/mmc.h>
+#endif
 #include <i2c.h>
 #include <spi.h>
 #include "emc.h"
@@ -221,3 +224,25 @@ int board_late_init(void)
 #endif
 	return 0;
 }
+
+#if defined(CONFIG_TEGRA_MMC)
+void __pin_mux_mmc(void)
+{
+}
+
+void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc")));
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+	debug("%s called\n", __func__);
+
+	/* Enable muxes, etc. for SDMMC controllers */
+	pin_mux_mmc();
+
+	debug("%s: init MMC\n", __func__);
+	tegra_mmc_init();
+
+	return 0;
+}
+#endif
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index 93430ed..3122441 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -27,19 +27,14 @@
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/gpio.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
-
 
 #ifdef CONFIG_TEGRA_MMC
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
+void pin_mux_mmc(void)
 {
 	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
 	funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
@@ -54,25 +49,6 @@ static void pin_mux_mmc(void)
 	/* For CD GPIO PI5 */
 	pinmux_tristate_disable(PINGRP_ATC);
 }
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-	debug("board_mmc_init called\n");
-
-	/* Enable muxes, etc. for SDMMC controllers */
-	pin_mux_mmc();
-
-	debug("board_mmc_init: init SD slot J26\n");
-	/* init dev 0, SD slot J26, with 8-bit bus */
-	tegra_mmc_init(0, 8, GPIO_PI6, GPIO_PH2);
-
-	debug("board_mmc_init: init SD slot J5\n");
-	/* init dev 2, SD slot J5, with 4-bit bus */
-	tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
-
-	return 0;
-}
 #endif
 
 void pin_mux_usb(void)
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 3e33da0..e581fdd 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -28,11 +28,7 @@
 #include <asm/arch/funcmux.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/gpio.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
 
 /* TODO: Remove this code when the SPI switch is working */
 #if !defined(CONFIG_SPI_UART_SWITCH) && (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
@@ -51,7 +47,7 @@ void gpio_early_init_uart(void)
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
+void pin_mux_mmc(void)
 {
 	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
 	funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
@@ -61,25 +57,6 @@ static void pin_mux_mmc(void)
 	/* For CD GPIO PI5 */
 	pinmux_tristate_disable(PINGRP_ATC);
 }
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-	debug("board_mmc_init called\n");
-
-	/* Enable muxes, etc. for SDMMC controllers */
-	pin_mux_mmc();
-
-	debug("board_mmc_init: init eMMC\n");
-	/* init dev 0, eMMC chip, with 8-bit bus */
-	tegra_mmc_init(0, 8, -1, -1);
-
-	debug("board_mmc_init: init SD slot\n");
-	/* init dev 1, SD slot, with 4-bit bus */
-	tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
-
-	return 0;
-}
 #endif
 
 void pin_mux_usb(void)
diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c
index 592cd6b..f18aa27 100644
--- a/board/nvidia/whistler/whistler.c
+++ b/board/nvidia/whistler/whistler.c
@@ -27,32 +27,19 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/gpio.h>
 #include <i2c.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
-
 
+#ifdef CONFIG_TEGRA_MMC
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
-{
-	funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT);
-	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT);
-}
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
+void pin_mux_mmc(void)
 {
 	uchar val;
 	int ret;
 
-	debug("board_mmc_init called\n");
-
 	/* Turn on MAX8907B LDO12 to 2.8V for J40 power */
 	ret = i2c_set_bus_num(0);
 	if (ret)
@@ -70,17 +57,10 @@ int board_mmc_init(bd_t *bd)
 	if (ret)
 		printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret);
 
-	/* Enable muxes, etc. for SDMMC controllers */
-	pin_mux_mmc();
-
-	/* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */
-	tegra_mmc_init(0, 8, -1, -1);
-
-	/* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */
-	tegra_mmc_init(1, 8, -1, -1);
-
-	return 0;
+	funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT);
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT);
 }
+#endif
 
 /* this is a weak define that we are overriding */
 void pin_mux_usb(void)
diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c
index e40a986..aa76f65 100644
--- a/board/toradex/colibri_t20_iris/colibri_t20_iris.c
+++ b/board/toradex/colibri_t20_iris/colibri_t20_iris.c
@@ -19,7 +19,6 @@
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/board.h>
-#include <asm/arch-tegra/mmc.h>
 
 #include "../colibri_t20-common/colibri_t20-common.h"
 
@@ -34,13 +33,13 @@ void pin_mux_usb(void)
 #endif
 
 #ifdef CONFIG_TEGRA_MMC
-int board_mmc_init(bd_t *bd)
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
 {
 	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
 	pinmux_tristate_disable(PINGRP_GMB);
-
-	tegra_mmc_init(0, 4, -1, GPIO_PC7);
-
-	return 0;
 }
 #endif
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index d749ab0..7e8f0b8 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2009 SAMSUNG Electronics
  * Minkyu Kang <mk7.kang@samsung.com>
  * Jaehoon Chung <jh80.chung@samsung.com>
- * Portions Copyright 2011-2012 NVIDIA Corporation
+ * Portions Copyright 2011-2013 NVIDIA Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,6 +21,7 @@
 
 #include <bouncebuf.h>
 #include <common.h>
+#include <fdtdec.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -28,44 +29,14 @@
 #include <asm/arch-tegra/tegra_mmc.h>
 #include <mmc.h>
 
-/* support 4 mmc hosts */
-struct mmc mmc_dev[4];
-struct mmc_host mmc_host[4];
+DECLARE_GLOBAL_DATA_PTR;
 
+struct mmc mmc_dev[MAX_HOSTS];
+struct mmc_host mmc_host[MAX_HOSTS];
 
-/**
- * Get the host address and peripheral ID for a device. Devices are numbered
- * from 0 to 3.
- *
- * @param host		Structure to fill in (base, reg, mmc_id)
- * @param dev_index	Device index (0-3)
- */
-static void tegra_get_setup(struct mmc_host *host, int dev_index)
-{
-	debug("tegra_get_setup: dev_index = %d\n", dev_index);
-
-	switch (dev_index) {
-	case 1:
-		host->base = TEGRA_SDMMC3_BASE;
-		host->mmc_id = PERIPH_ID_SDMMC3;
-		break;
-	case 2:
-		host->base = TEGRA_SDMMC2_BASE;
-		host->mmc_id = PERIPH_ID_SDMMC2;
-		break;
-	case 3:
-		host->base = TEGRA_SDMMC1_BASE;
-		host->mmc_id = PERIPH_ID_SDMMC1;
-		break;
-	case 0:
-	default:
-		host->base = TEGRA_SDMMC4_BASE;
-		host->mmc_id = PERIPH_ID_SDMMC4;
-		break;
-	}
-
-	host->reg = (struct tegra_mmc *)host->base;
-}
+#ifndef CONFIG_OF_CONTROL
+#error "Please enable device tree support to use this driver"
+#endif
 
 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
 				struct bounce_buffer *bbstate)
@@ -518,41 +489,43 @@ int tegra_mmc_getcd(struct mmc *mmc)
 
 	debug("tegra_mmc_getcd called\n");
 
-	if (host->cd_gpio >= 0)
-		return !gpio_get_value(host->cd_gpio);
+	if (fdt_gpio_isvalid(&host->cd_gpio))
+		return !fdtdec_get_gpio(&host->cd_gpio);
 
 	return 1;
 }
 
-int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
+static int do_mmc_init(int dev_index)
 {
 	struct mmc_host *host;
 	char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
 	struct mmc *mmc;
 
-	debug(" tegra_mmc_init: index %d, bus width %d "
-		"pwr_gpio %d cd_gpio %d\n",
-		dev_index, bus_width, pwr_gpio, cd_gpio);
-
+	/* DT should have been read & host config filled in */
 	host = &mmc_host[dev_index];
+	if (!host->enabled)
+		return -1;
 
-	host->clock = 0;
-	host->pwr_gpio = pwr_gpio;
-	host->cd_gpio = cd_gpio;
-	tegra_get_setup(host, dev_index);
+	debug(" do_mmc_init: index %d, bus width %d "
+		"pwr_gpio %d cd_gpio %d\n",
+		dev_index, host->width,
+		host->pwr_gpio.gpio, host->cd_gpio.gpio);
 
+	host->clock = 0;
 	clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
 
-	if (host->pwr_gpio >= 0) {
+	if (fdt_gpio_isvalid(&host->pwr_gpio)) {
 		sprintf(gpusage, "SD/MMC%d PWR", dev_index);
-		gpio_request(host->pwr_gpio, gpusage);
-		gpio_direction_output(host->pwr_gpio, 1);
+		gpio_request(host->pwr_gpio.gpio, gpusage);
+		gpio_direction_output(host->pwr_gpio.gpio, 1);
+		debug(" Power GPIO name = %s\n", host->pwr_gpio.name);
 	}
 
-	if (host->cd_gpio >= 0) {
+	if (fdt_gpio_isvalid(&host->cd_gpio)) {
 		sprintf(gpusage, "SD/MMC%d CD", dev_index);
-		gpio_request(host->cd_gpio, gpusage);
-		gpio_direction_input(host->cd_gpio);
+		gpio_request(host->cd_gpio.gpio, gpusage);
+		gpio_direction_input(host->cd_gpio.gpio);
+		debug(" CD GPIO name = %s\n", host->cd_gpio.name);
 	}
 
 	mmc = &mmc_dev[dev_index];
@@ -566,9 +539,9 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 
 	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 	mmc->host_caps = 0;
-	if (bus_width == 8)
+	if (host->width == 8)
 		mmc->host_caps |= MMC_MODE_8BIT;
-	if (bus_width >= 4)
+	if (host->width >= 4)
 		mmc->host_caps |= MMC_MODE_4BIT;
 	mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
 
@@ -577,8 +550,6 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 	 *  low-speed SDIO card frequency (actually 400KHz)
 	 * max freq is highest HS eMMC clock as per the SD/MMC spec
 	 *  (actually 52MHz)
-	 * Both of these are the closest equivalents w/216MHz source
-	 *  clock and Tegra SDMMC divisors.
 	 */
 	mmc->f_min = 375000;
 	mmc->f_max = 48000000;
@@ -587,3 +558,95 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 
 	return 0;
 }
+
+/**
+ * Get the host address and peripheral ID for a node.
+ *
+ * @param blob		fdt blob
+ * @param node		Device index (0-3)
+ * @param host		Structure to fill in (reg, width, mmc_id)
+ */
+static int mmc_get_config(const void *blob, int node, struct mmc_host *host)
+{
+	debug("%s: node = %d\n", __func__, node);
+
+	host->enabled = fdtdec_get_is_enabled(blob, node);
+
+	host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg");
+	if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) {
+		debug("%s: no sdmmc base reg info found\n", __func__);
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	host->mmc_id = clock_decode_periph_id(blob, node);
+	if (host->mmc_id == PERIPH_ID_NONE) {
+		debug("%s: could not decode periph id\n", __func__);
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	/*
+	 * NOTE: mmc->bus_width is determined by mmc.c dynamically.
+	 * TBD: Override it with this value?
+	 */
+	host->width = fdtdec_get_int(blob, node, "bus-width", 0);
+	if (!host->width)
+		debug("%s: no sdmmc width found\n", __func__);
+
+	/* These GPIOs are optional */
+	fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
+	fdtdec_decode_gpio(blob, node, "wp-gpios", &host->wp_gpio);
+	fdtdec_decode_gpio(blob, node, "power-gpios", &host->pwr_gpio);
+
+	debug("%s: found controller at %p, width = %d, periph_id = %d\n",
+		__func__, host->reg, host->width, host->mmc_id);
+	return 0;
+}
+
+/*
+ * Process a list of nodes, adding them to our list of SDMMC ports.
+ *
+ * @param blob          fdt blob
+ * @param node_list     list of nodes to process (any <=0 are ignored)
+ * @param count         number of nodes to process
+ * @return 0 if ok, -1 on error
+ */
+static int process_nodes(const void *blob, int node_list[], int count)
+{
+	struct mmc_host *host;
+	int i, node;
+
+	debug("%s: count = %d\n", __func__, count);
+
+	/* build mmc_host[] for each controller */
+	for (i = 0; i < count; i++) {
+		node = node_list[i];
+		if (node <= 0)
+			continue;
+
+		host = &mmc_host[i];
+		host->id = i;
+
+		if (mmc_get_config(blob, node, host)) {
+			printf("%s: failed to decode dev %d\n",	__func__, i);
+			return -1;
+		}
+		do_mmc_init(i);
+	}
+	return 0;
+}
+
+void tegra_mmc_init(void)
+{
+	int node_list[MAX_HOSTS], count;
+	const void *blob = gd->fdt_blob;
+	debug("%s entry\n", __func__);
+
+	count = fdtdec_find_aliases_for_id(blob, "sdhci",
+		COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS);
+	debug("%s: count of sdhci nodes is %d\n", __func__, count);
+
+	if (process_nodes(blob, node_list, count)) {
+		printf("%s: Error processing mmc node(s)!\n", __func__);
+		return;
+	}
+}
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 77f244f..4f9dbcf 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -70,6 +70,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
 	COMPAT_NVIDIA_TEGRA20_PWM,	/* Tegra 2 PWM controller */
 	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
+	COMPAT_NVIDIA_TEGRA20_SDMMC,	/* Tegra SDMMC controller */
 	COMPAT_NVIDIA_TEGRA20_SFLASH,	/* Tegra 2 SPI flash controller */
 	COMPAT_NVIDIA_TEGRA20_SLINK,	/* Tegra 2 SPI SLINK controller */
 	COMPAT_SMSC_LAN9215,		/* SMSC 10/100 Ethernet LAN9215 */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 3ae348d..57e552c 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -45,6 +45,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
 	COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
 	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+	COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
 	COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
 	COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"),
 	COMPAT(SMSC_LAN9215, "smsc,lan9215"),
-- 
1.7.0.4

[U-Boot] [PATCH v5 3/4] Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files

[Stephen Warren]

On 02/20/2013 02:05 PM, Tom Warren wrote:
> Linux dts files were used for those boards that didn't already
> have sdhci info populated. Tamonten has their own dtsi file with
> common sdhci nodes (sourced from Linux).

So this patch now does a two unrelated things:

a) Switches from /include/ to #include.
b) A bunch of changes for the SDHCI properties.

Those should really be separate patches.

> diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts

> -/include/ ARCH_CPU_DTS
> +#include ARCH_CPU_DTS

I think we should get rid of ARCH_CPU_DTS too. The only reason it ever
existed was because we were using dtc's include processing and had to
work around some issue with that (I can't remember exactly what, but
Simon will). Now that we're using cpp's include processing, we can
simply write:

#include "tegra20.dtsi".

> diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts

>  /memreserve/ 0x1c000000 0x04000000;

Unrelated to this series, but we should remove that line. It's unlikely
to be remotely correct.

>  	sdhci at c8000400 {
> +		status = "okay";
>  		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
>  		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
>  		power-gpios = <&gpio 70 0>; /* gpio PI6 */
> +		bus-width = <4>;
>  	};

In an earlier version of these patches, I think you'd made the cd-gpios
flags be "3" not "0", and I'd pointed out that doesn't match the
kernel's. It turns out that on most (if not all) boards, cd-gpios should
actually be marked active-low, so the flags should likely be "1" (not 3;
bit 1 isn't defined to mean anything). This is true for all the NVIDIA
boards, and Paz00 and TrimSlice. Joseph Lo is waiting for confirmation
from Thierry and Lucas on their boards before re-spinning the patch to
update them too.

See:
http://www.spinics.net/lists/linux-mmc/msg19134.html
http://www.spinics.net/lists/linux-mmc/msg19139.html

> diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts

>  /memreserve/ 0x1c000000 0x04000000;

Same here, except that value is definitely always incorrect; memory
starts at 0x80000000 on Tegra30, so that range never matches memory.

[U-Boot] [PATCH v5 0/4] Tegra: MMC: Add DT support for MMC to T20 boards

[Stephen Warren]

On 02/20/2013 02:05 PM, Tom Warren wrote:
> This patchset adds device-tree support to the Tegra MMC driver.
> All device config is done via properties in the DT files instead
> of hard-coded config options/function arguments.
> 
> I've tested this on my Seaboard and everything works fine,
> including card detect. For the other T20 boards, I've used
> the Linux kernel DTS files for the sdhci nodes where there
> wasn't one already, or expanded the info that was already
> there. Everything builds fine, but I haven't tested anything
> but Seaboard.

The series,

Tested-by: Stephen Warren <swarren@nvidia.com>

(On Harmony only, which was one of the 2 problematic boards for v4)

[U-Boot] [PATCH v5 3/4] Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files

[Tom Warren]

Stephen,

On Wed, Feb 20, 2013 at 3:35 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 02/20/2013 02:05 PM, Tom Warren wrote:
>> Linux dts files were used for those boards that didn't already
>> have sdhci info populated. Tamonten has their own dtsi file with
>> common sdhci nodes (sourced from Linux).
>
> So this patch now does a two unrelated things:
>
> a) Switches from /include/ to #include.
> b) A bunch of changes for the SDHCI properties.
>
> Those should really be separate patches.
I'll split 'em.

>
>> diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts
>
>> -/include/ ARCH_CPU_DTS
>> +#include ARCH_CPU_DTS
>
> I think we should get rid of ARCH_CPU_DTS too. The only reason it ever
> existed was because we were using dtc's include processing and had to
> work around some issue with that (I can't remember exactly what, but
> Simon will). Now that we're using cpp's include processing, we can
> simply write:
>
> #include "tegra20.dtsi".
That can be done later in a dts include file cleanup patch for all the
DT builds/files. What is there now works fine.

>
>> diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
>
>>  /memreserve/ 0x1c000000 0x04000000;
>
> Unrelated to this series, but we should remove that line. It's unlikely
> to be remotely correct.
Yep, saw those (tegra30, too), but didn't want to fix 'em here. I'll
do it in a separate patch later.

>
>>       sdhci at c8000400 {
>> +             status = "okay";
>>               cd-gpios = <&gpio 69 0>; /* gpio PI5 */
>>               wp-gpios = <&gpio 57 0>; /* gpio PH1 */
>>               power-gpios = <&gpio 70 0>; /* gpio PI6 */
>> +             bus-width = <4>;
>>       };
>
> In an earlier version of these patches, I think you'd made the cd-gpios
> flags be "3" not "0", and I'd pointed out that doesn't match the
> kernel's. It turns out that on most (if not all) boards, cd-gpios should
> actually be marked active-low, so the flags should likely be "1" (not 3;
> bit 1 isn't defined to mean anything). This is true for all the NVIDIA
> boards, and Paz00 and TrimSlice. Joseph Lo is waiting for confirmation
> from Thierry and Lucas on their boards before re-spinning the patch to
> update them too.

Card-detect works fine (at least, on Seaboard). There never was an
earlier version with cd-gpios flags with anything other than 0. It was
power-gpios for Seaboard that had its flags set to 3 in a ChromeOS
version of U-Boot that I originally copied the DT sdhci info from, and
I've fixed that.

>
> See:
> http://www.spinics.net/lists/linux-mmc/msg19134.html
> http://www.spinics.net/lists/linux-mmc/msg19139.html
>
>> diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
>
>>  /memreserve/ 0x1c000000 0x04000000;
>
> Same here, except that value is definitely always incorrect; memory
> starts at 0x80000000 on Tegra30, so that range never matches memory.

[U-Boot] [PATCH v5 3/4] Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files

[Stephen Warren]

On 02/20/2013 04:01 PM, Tom Warren wrote:
> Stephen,
> 
> On Wed, Feb 20, 2013 at 3:35 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 02/20/2013 02:05 PM, Tom Warren wrote:
>>> Linux dts files were used for those boards that didn't already
>>> have sdhci info populated. Tamonten has their own dtsi file with
>>> common sdhci nodes (sourced from Linux).
>>
>> So this patch now does a two unrelated things:
>>
>> a) Switches from /include/ to #include.
>> b) A bunch of changes for the SDHCI properties.
>>
>> Those should really be separate patches.
> I'll split 'em.
> 
>>
>>> diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts
>>
>>> -/include/ ARCH_CPU_DTS
>>> +#include ARCH_CPU_DTS
>>
>> I think we should get rid of ARCH_CPU_DTS too. The only reason it ever
>> existed was because we were using dtc's include processing and had to
>> work around some issue with that (I can't remember exactly what, but
>> Simon will). Now that we're using cpp's include processing, we can
>> simply write:
>>
>> #include "tegra20.dtsi".
> That can be done later in a dts include file cleanup patch for all the
> DT builds/files. What is there now works fine.

Sigh. But if you're using cpp now, then removing the use of ARCH_CPU_DTS
is logically part of that.

I agree it works now, but it's far more important to get it right than
just make it work.

>>> diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
>>
>>>  /memreserve/ 0x1c000000 0x04000000;
>>
>> Unrelated to this series, but we should remove that line. It's unlikely
>> to be remotely correct.
> Yep, saw those (tegra30, too), but didn't want to fix 'em here. I'll
> do it in a separate patch later.
> 
>>
>>>       sdhci at c8000400 {
>>> +             status = "okay";
>>>               cd-gpios = <&gpio 69 0>; /* gpio PI5 */
>>>               wp-gpios = <&gpio 57 0>; /* gpio PH1 */
>>>               power-gpios = <&gpio 70 0>; /* gpio PI6 */
>>> +             bus-width = <4>;
>>>       };
>>
>> In an earlier version of these patches, I think you'd made the cd-gpios
>> flags be "3" not "0", and I'd pointed out that doesn't match the
>> kernel's. It turns out that on most (if not all) boards, cd-gpios should
>> actually be marked active-low, so the flags should likely be "1" (not 3;
>> bit 1 isn't defined to mean anything). This is true for all the NVIDIA
>> boards, and Paz00 and TrimSlice. Joseph Lo is waiting for confirmation
>> from Thierry and Lucas on their boards before re-spinning the patch to
>> update them too.
> 
> Card-detect works fine (at least, on Seaboard).

That's likely because nothing in the code actually uses the GPIO flags
field, but rather assumes that the GPIO is active low.

We should still correct this error in the DT so that what the DT asserts
is true actually is true.

> There never was an
> earlier version with cd-gpios flags with anything other than 0. It was
> power-gpios for Seaboard that had its flags set to 3 in a ChromeOS
> version of U-Boot that I originally copied the DT sdhci info from, and
> I've fixed that.

Ah, OK.

[U-Boot] [PATCH v5 0/4] Tegra: MMC: Add DT support for MMC to T20 boards

[Thierry Reding]

On Wed, Feb 20, 2013 at 02:05:46PM -0700, Tom Warren wrote:
> This patchset adds device-tree support to the Tegra MMC driver.
> All device config is done via properties in the DT files instead
> of hard-coded config options/function arguments.
> 
> I've tested this on my Seaboard and everything works fine,
> including card detect. For the other T20 boards, I've used
> the Linux kernel DTS files for the sdhci nodes where there
> wasn't one already, or expanded the info that was already
> there. Everything builds fine, but I haven't tested anything
> but Seaboard.
> 
> v2: Changes as per Stephen's & Simon's review
> v3: Changes as per Stephen/Lucas/Thierry/Simon's feedback
> v4: Additional changes as per Stephen/Lucas/Thierry/Simon
> v5: Additional changes as per Stephen/Lucas/Andy

Hi Tom,

Joseph Lo posted some patches recently which make changes to the Linux
driver to use common MMC code. This results in the third cell of the
GPIO specifier to actually become meaningful. That is, boards now need
to define the CD GPIO as low-active in order for card-detection to work
properly.

I wonder if we should be integrating similar changes into this patch
series. fdtdec_get_gpio() seems to already support that functionality,
so I think the only changes necessary would be to change the third cell
in the specifier and make tegra_mmc_getcd() return fdtdec_get_gpio()
instead of !fdtdec_get_gpio().

Does that sound like something you'd be willing to integrate with this
series?

Thierry
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[U-Boot] [PATCH v5 0/4] Tegra: MMC: Add DT support for MMC to T20 boards

[Thierry Reding]

On Thu, Feb 21, 2013 at 10:00:20AM +0100, Thierry Reding wrote:
> On Wed, Feb 20, 2013 at 02:05:46PM -0700, Tom Warren wrote:
> > This patchset adds device-tree support to the Tegra MMC driver.
> > All device config is done via properties in the DT files instead
> > of hard-coded config options/function arguments.
> > 
> > I've tested this on my Seaboard and everything works fine,
> > including card detect. For the other T20 boards, I've used
> > the Linux kernel DTS files for the sdhci nodes where there
> > wasn't one already, or expanded the info that was already
> > there. Everything builds fine, but I haven't tested anything
> > but Seaboard.
> > 
> > v2: Changes as per Stephen's & Simon's review
> > v3: Changes as per Stephen/Lucas/Thierry/Simon's feedback
> > v4: Additional changes as per Stephen/Lucas/Thierry/Simon
> > v5: Additional changes as per Stephen/Lucas/Andy
> 
> Hi Tom,
> 
> Joseph Lo posted some patches recently which make changes to the Linux
> driver to use common MMC code. This results in the third cell of the
> GPIO specifier to actually become meaningful. That is, boards now need
> to define the CD GPIO as low-active in order for card-detection to work
> properly.
> 
> I wonder if we should be integrating similar changes into this patch
> series. fdtdec_get_gpio() seems to already support that functionality,
> so I think the only changes necessary would be to change the third cell
> in the specifier and make tegra_mmc_getcd() return fdtdec_get_gpio()
> instead of !fdtdec_get_gpio().

The below patch is what I used on top of your v5 series and verified
that card-detection continues to work as expected.

Thierry

diff --git a/board/avionic-design/dts/tegra20-tamonten.dtsi b/board/avionic-design/dts/tegra20-tamonten.dtsi
index 6296f77..d4c3293 100644
--- a/board/avionic-design/dts/tegra20-tamonten.dtsi
+++ b/board/avionic-design/dts/tegra20-tamonten.dtsi
@@ -476,7 +476,7 @@
 	};
 
 	sdhci at c8000600 {
-		cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+		cd-gpios = <&gpio 58 1>; /* gpio PH2 */
 		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
 		bus-width = <4>;
 		status = "okay";
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 7e8f0b8..6063d08 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -490,7 +490,7 @@ int tegra_mmc_getcd(struct mmc *mmc)
 	debug("tegra_mmc_getcd called\n");
 
 	if (fdt_gpio_isvalid(&host->cd_gpio))
-		return !fdtdec_get_gpio(&host->cd_gpio);
+		return fdtdec_get_gpio(&host->cd_gpio);
 
 	return 1;
 }
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[U-Boot] [PATCH v5 0/4] Tegra: MMC: Add DT support for MMC to T20 boards

[Tom Warren]

Thierry,

On Thu, Feb 21, 2013 at 2:00 AM, Thierry Reding
<thierry.reding@avionic-design.de> wrote:
> On Wed, Feb 20, 2013 at 02:05:46PM -0700, Tom Warren wrote:
>> This patchset adds device-tree support to the Tegra MMC driver.
>> All device config is done via properties in the DT files instead
>> of hard-coded config options/function arguments.
>>
>> I've tested this on my Seaboard and everything works fine,
>> including card detect. For the other T20 boards, I've used
>> the Linux kernel DTS files for the sdhci nodes where there
>> wasn't one already, or expanded the info that was already
>> there. Everything builds fine, but I haven't tested anything
>> but Seaboard.
>>
>> v2: Changes as per Stephen's & Simon's review
>> v3: Changes as per Stephen/Lucas/Thierry/Simon's feedback
>> v4: Additional changes as per Stephen/Lucas/Thierry/Simon
>> v5: Additional changes as per Stephen/Lucas/Andy
>
> Hi Tom,
>
> Joseph Lo posted some patches recently which make changes to the Linux
> driver to use common MMC code. This results in the third cell of the
> GPIO specifier to actually become meaningful. That is, boards now need
> to define the CD GPIO as low-active in order for card-detection to work
> properly.
>
> I wonder if we should be integrating similar changes into this patch
> series. fdtdec_get_gpio() seems to already support that functionality,
> so I think the only changes necessary would be to change the third cell
> in the specifier and make tegra_mmc_getcd() return fdtdec_get_gpio()
> instead of !fdtdec_get_gpio().
>
> Does that sound like something you'd be willing to integrate with this
> series?
Sure, what's another spin? ;)  I'll add it in v6. Thanks

Tom
>
> Thierry

[U-Boot] [PATCH v5 3/4] Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files

[Tom Warren]

Stephen,

On Wed, Feb 20, 2013 at 5:15 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 02/20/2013 04:01 PM, Tom Warren wrote:
>> Stephen,
>>
>> On Wed, Feb 20, 2013 at 3:35 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> On 02/20/2013 02:05 PM, Tom Warren wrote:
>>>> Linux dts files were used for those boards that didn't already
>>>> have sdhci info populated. Tamonten has their own dtsi file with
>>>> common sdhci nodes (sourced from Linux).
>>>
>>> So this patch now does a two unrelated things:
>>>
>>> a) Switches from /include/ to #include.
>>> b) A bunch of changes for the SDHCI properties.
>>>
>>> Those should really be separate patches.
>> I'll split 'em.
>>
>>>
>>>> diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts
>>>
>>>> -/include/ ARCH_CPU_DTS
>>>> +#include ARCH_CPU_DTS
>>>
>>> I think we should get rid of ARCH_CPU_DTS too. The only reason it ever
>>> existed was because we were using dtc's include processing and had to
>>> work around some issue with that (I can't remember exactly what, but
>>> Simon will). Now that we're using cpp's include processing, we can
>>> simply write:
>>>
>>> #include "tegra20.dtsi".
>> That can be done later in a dts include file cleanup patch for all the
>> DT builds/files. What is there now works fine.
>
> Sigh. But if you're using cpp now, then removing the use of ARCH_CPU_DTS
> is logically part of that.
>
> I agree it works now, but it's far more important to get it right than
> just make it work.
Since I have to touch the dts files yet again to put the cd-gpios flag
change in, I'll change all the ARCH_CPU_DTS occurrences to
"tegra20.dtsi". Sigh. ;)

>
>>>> diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
>>>
>>>>  /memreserve/ 0x1c000000 0x04000000;
>>>
>>> Unrelated to this series, but we should remove that line. It's unlikely
>>> to be remotely correct.
>> Yep, saw those (tegra30, too), but didn't want to fix 'em here. I'll
>> do it in a separate patch later.
>>
>>>
>>>>       sdhci at c8000400 {
>>>> +             status = "okay";
>>>>               cd-gpios = <&gpio 69 0>; /* gpio PI5 */
>>>>               wp-gpios = <&gpio 57 0>; /* gpio PH1 */
>>>>               power-gpios = <&gpio 70 0>; /* gpio PI6 */
>>>> +             bus-width = <4>;
>>>>       };
>>>
>>> In an earlier version of these patches, I think you'd made the cd-gpios
>>> flags be "3" not "0", and I'd pointed out that doesn't match the
>>> kernel's. It turns out that on most (if not all) boards, cd-gpios should
>>> actually be marked active-low, so the flags should likely be "1" (not 3;
>>> bit 1 isn't defined to mean anything). This is true for all the NVIDIA
>>> boards, and Paz00 and TrimSlice. Joseph Lo is waiting for confirmation
>>> from Thierry and Lucas on their boards before re-spinning the patch to
>>> update them too.
>>
>> Card-detect works fine (at least, on Seaboard).
>
> That's likely because nothing in the code actually uses the GPIO flags
> field, but rather assumes that the GPIO is active low.
>
> We should still correct this error in the DT so that what the DT asserts
> is true actually is true.
>
>> There never was an
>> earlier version with cd-gpios flags with anything other than 0. It was
>> power-gpios for Seaboard that had its flags set to 3 in a ChromeOS
>> version of U-Boot that I originally copied the DT sdhci info from, and
>> I've fixed that.
>
> Ah, OK.