[U-Boot] [PATCH 4/5] mmc: Tegra: Add SD bus power/voltage function and MMC pad init call.

Tom Warren
2013-02-26T20:46:35Z

Tegra30 requires the SD Bus Voltage & Power bits be set in the SD
Power Control register. Tegra20 works w/o them set, but do it anyway
for those SoCs as it's part of the SD spec. Also call a common
board pad init routine (pad_init_mmc) in mmc_reset(), used by
Tegra30 only for now.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
drivers/mmc/tegra_mmc.c | 48 ++++++++++++++++++++++++++++++++++++++++++----
1 files changed, 43 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 6063d08..9e44771 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -21,7 +21,6 @@

#include <bouncebuf.h>
#include <common.h>
-#include <fdtdec.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
@@ -38,6 +37,38 @@ struct mmc_host mmc_host[MAX_HOSTS];
#error "Please enable device tree support to use this driver"
#endif

+static void mmc_set_power(struct mmc_host *host, unsigned short power)
+{
+ u8 pwr = 0;
+ debug("%s: power = %x\n", __func__, power);
+
+ if (power != (unsigned short)-1) {
+ switch (1 << power) {
+ case MMC_VDD_165_195:
+ pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
+ break;
+ case MMC_VDD_29_30:
+ case MMC_VDD_30_31:
+ pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
+ break;
+ case MMC_VDD_32_33:
+ case MMC_VDD_33_34:
+ pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
+ break;
+ }
+ }
+ debug("%s: pwr = %X\n", __func__, pwr);
+
+ /* Set the bus voltage first (if any) */
+ writeb(pwr, &host->reg->pwrcon);
+ if (pwr == 0)
+ return;
+
+ /* Now enable bus power */
+ pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
+ writeb(pwr, &host->reg->pwrcon);
+}
+
static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
struct bounce_buffer *bbstate)
{
@@ -334,8 +365,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
debug(" mmc_change_clock called\n");

/*
- * Change Tegra SDMMCx clock divisor here. Source is 216MHz,
- * PLLP_OUT0
+ * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
*/
if (clock == 0)
goto out;
@@ -410,7 +440,7 @@ static void mmc_set_ios(struct mmc *mmc)
debug("mmc_set_ios: hostctl = %08X\n", ctrl);
}

-static void mmc_reset(struct mmc_host *host)
+static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
{
unsigned int timeout;
debug(" mmc_reset called\n");
@@ -436,6 +466,14 @@ static void mmc_reset(struct mmc_host *host)
timeout--;
udelay(1000);
}
+
+ /* Set SD bus voltage & enable bus power */
+ mmc_set_power(host, fls(mmc->voltages) - 1);
+ debug("%s: power control = %02X, host control = %02X\n", __func__,
+ readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
+
+ /* Make sure SDIO pads are set up */
+ pad_init_mmc(host->reg);
}

static int mmc_core_init(struct mmc *mmc)
@@ -444,7 +482,7 @@ static int mmc_core_init(struct mmc *mmc)
unsigned int mask;
debug(" mmc_core_init called\n");

- mmc_reset(host);
+ mmc_reset(host, mmc);

host->version = readw(&host->reg->hcver);
debug("host version = %x\n", host->version);
--
1.7.0.4