From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Date: Fri, 01 Mar 2013 14:53:33 -0700 Subject: [U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds In-Reply-To: <512F8F11.3080204@wwwdotorg.org> References: <1361917709-11536-1-git-send-email-swarren@wwwdotorg.org> <512F8F11.3080204@wwwdotorg.org> Message-ID: <5131235D.4030507@wwwdotorg.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 02/28/2013 10:08 AM, Stephen Warren wrote: > On 02/26/2013 03:28 PM, Stephen Warren wrote: >> From: Stephen Warren >> >> Various errata exist in the Cortex-A9 CPU, and may be worked around by >> setting some bits in a CP15 diagnostic register. Add code to implement >> the workarounds, enabled by new CONFIG_ options. >> >> This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S, >> and modified to remove the logic to conditionally apply the WAR (since we >> know exactly which CPU we're running on given the U-Boot configuration), >> and use r0 instead of r10 for consistency with the rest of U-Boot's >> cpu_init_cp15(). > > Hmmm. Lets hold off on this series; there are some conditions under > which the kernel has to be able to apply these WARs anyway (e.g. SMP CPU > power saving), which may impact which of the WARs the bootloader should > apply even when booting the initial CPU 0. I'll repost once that's been > resolved. Tom, It looks like the bootloader should always apply these WARs for CPU 0. We just have to make sure that the kernel applies them for CPUs 1..n if/when running in secure mode. In other words, I think these patches are good to go in as-is. Since there are no changes to the patches, I won't repost them, unless you need me to.