From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Tue, 05 Mar 2013 10:55:34 -0700
Subject: [U-Boot] [PATCH v2 3/6] Tegra30: MMC: Add SD bus power-rail and
 SDMMC pad init routines
In-Reply-To: <1362500985-13196-4-git-send-email-twarren@nvidia.com>
References: <1362500985-13196-1-git-send-email-twarren@nvidia.com>
	<1362500985-13196-4-git-send-email-twarren@nvidia.com>
Message-ID: <51363196.6020902@wwwdotorg.org>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On 03/05/2013 09:29 AM, Tom Warren wrote:
> T30 requires specific SDMMC pad programming, and bus power-rail bringup.

> diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c

> +void pad_init_mmc(struct mmc_host *host)

> +	if (id == PERIPH_ID_SDMMC1) {
> +		val = readl(&gpc->sdio1cfg);
> +		val &= padmask;
> +		val |= padcfg;
> +		writel(val, &gpc->sdio1cfg);
> +		debug(" wrote 0x%08X to %p\n", val, &gpc->sdio1cfg);
> +	} else {
> +		val = readl(&gpc->sdio3cfg);
> +		val &= padmask;
> +		val |= padcfg;
> +		writel(val, &gpc->sdio3cfg);
> +		debug(" wrote 0x%08X to %p\n", val, &gpc->sdio3cfg);
> +	}

This isn't generic enough, although the problems may not show up for the
SDMMC1/3 controllers since it looks like those controllers always use a
specific set of pins; the pinmux HW doesn't allow those controllers to
be routed to different places.

However, SDMMC1 and SDMMC4 would also need entries in the above if
statement for it to be complete. Those controllers can definitely be
switched between different sets of pins. This function would then
somehow have to know which set of pins to apply the pinmux configuration
to, which would imply searching through the pinmux registers to find the
pins which have their mux function set to point at the controller in
question.

This implies that configuring the pinmux here isn't the right way to do
this. As I wrote in my immediately previous email, I think the pingroup
drive registers (named "*cfg") should be initialized based on a table
provided by the board file (and later by DT; the values are already part
of the DT pinctrl bindings). The table or DT content will be
board-specific, and hence able to describe which pingroup should be
configured based on the board design.