[U-Boot] [PATCH 3/7] arm: dra7xx: clock: Add the dplls data

Tom Rini
2013-02-15T16:34:32Z

On Wed, Feb 13, 2013 at 12:59:05PM +0530, Lokesh Vutla wrote:
> A new DPLL DDR is added in DRA7XX socs. Now clocks to
> EMIF CD is from DPLL DDR. So DPLL DDR should be locked
> before initializing RAM.
> Also adding other dpll data which are different from OMAP5 ES2.0.
> SYS_CLK running at 20MHz is introduced in DRA7xx socs.
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>

Reviewed-by: Tom Rini <trini@ti.com>

--
Tom
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