From: Lauri Hintsala <lauri.hintsala@bluegiga.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2] mxs: spl_mem_init: Align DDR2 init with FSL bootlets source
Date: Tue, 19 Mar 2013 08:52:59 +0200 [thread overview]
Message-ID: <51480B4B.7060104@bluegiga.com> (raw)
In-Reply-To: <1362092359-16113-1-git-send-email-festevam@gmail.com>
Hi,
On 03/01/2013 12:59 AM, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> Currently the following kernel hang happens when loading a 2.6.35 kernel from
> Freeescale on a mx28evk board:
>
> RPC: Registered tcp transport module.
> RPC: Registered tcp NFSv4.1 backchannel transport module.
> Bus freq driver module loaded
> IMX usb wakeup probe
> usb h1 wakeup device is registered
> mxs_cpu_init: cpufreq init finished
> ...
I tried to boot Freescale's 2.6.35.3 kernel on apx4devkit. The device is
still freezing after mxs_cpu_init print.
Full logs:
U-Boot 2013.04-rc1-00002-g9659479 (Mar 19 2013 - 08:30:05)
CPU: Freescale i.MX28 rev1.2 at 454 MHz
BOOT: SSP SD/MMC #0, 3V3
I2C: ready
DRAM: 64 MiB
NAND: 128 MiB
MMC: MXS MMC: 0
In: serial
Out: serial
Err: serial
Net: FEC
Hit any key to stop autoboot: 0
1944456 bytes read in 754 ms (2.5 MiB/s)
## Booting kernel from Legacy Image at 41000000 ...
Image Name: Linux-2.6.35.3-01010-ge53a812
Created: 2013-03-19 6:31:40 UTC
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 1944392 Bytes = 1.9 MiB
Load Address: 40008000
Entry Point: 40008000
Loading Kernel Image ... OK
OK
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
Linux version 2.6.35.3-01010-ge53a812 (hintsla at bgtlh) (gcc version 4.3.4
(crosstool-NG-1.7.0) ) #32 Tue Mar 19 08:31:39 EET 2013
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Freescale MX28EVK board
Memory policy: ECC disabled, Data cache writeback
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256
Kernel command line: console=tty0 console=ttyAMA0,115200 consoleblank=0
ethaddr=00:07:80:01:66:db btaddr=00:07:80:01:67:0d
wlanaddr=00:07:80:59:ef:64 root=/dev/mmcblk0p2 rootwait
mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root) rw
PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 64MB = 64MB total
Memory: 60880k/60880k available, 4656k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
DMA : 0xfde00000 - 0xffe00000 ( 32 MB)
vmalloc : 0xc4800000 - 0xf0000000 ( 696 MB)
lowmem : 0xc0000000 - 0xc4000000 ( 64 MB)
modules : 0xbf000000 - 0xc0000000 ( 16 MB)
.init : 0xc0008000 - 0xc002d000 ( 148 kB)
.text : 0xc002d000 - 0xc03b8000 (3628 kB)
.data : 0xc03b8000 - 0xc03e4ba0 ( 179 kB)
SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Hierarchical RCU implementation.
RCU-based detection of stalled CPUs is disabled.
Verbose stalled-CPUs detection is disabled.
NR_IRQS:288
Console: colour dummy device 80x30
console [tty0] enabled
console [ttyAMA0] enabled
Calibrating delay loop... 226.09 BogoMIPS (lpj=1130496)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
regulator: core version 0.5
NET: Registered protocol family 16
regulator: vddd: 800 <--> 1575 mV at 1500 mV fast normal
regulator: vdddbo: 800 <--> 1575 mV fast normal
regulator: vdda: 1500 <--> 2275 mV at 1800 mV fast normal
vddio = 3380000, val=10
regulator: vddio: 2880 <--> 3680 mV at 3380 mV fast normal
regulator: overall_current: fast normal
regulator: vbus5v:
regulator: mxs-duart-1: fast normal
regulator: mxs-bl-1: fast normal
regulator: mxs-i2c-1: fast normal
regulator: mmc_ssp-1: fast normal
regulator: mmc_ssp-2: fast normal
regulator: charger-1: fast normal
regulator: power-test-1: fast normal
regulator: cpufreq-1: fast normal
i.MX IRAM pool: 124 KB at 0xc4820000
Initializing GPMI pins
Initializing SSP2 pins
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Advanced Linux Sound Architecture Driver Version 1.0.23.
IMX usb wakeup probe
usb DR wakeup device is registered
Switching to clocksource mxs clock source
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
Switched to NOHz mode on CPU #0
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Bus freq driver module loaded
IMX usb wakeup probe
usb h1 wakeup device is registered
WARNING : No battery connected !
Aborting power driver initialization
mxs-battery: probe of mxs-battery.0 failed with error 1
mxs_cpu_init: cpufreq init finished
And after that line the device is completely dead.
Lauri
>
> Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01
> package, the hang does not occur.
>
> Comparing the DDR2 initialization from the bootlets code against the U-boot
> one, we can notice some mismatches, and after applying the same initialization
> into U-boot the 2.6.35 kernel can boot normally.
>
> Also tested with 'mtest' command, which runs succesfully.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v1:
> - Fix tabs/space confusion and only show the real context changes
> arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> index f8392f6..2195dce 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> @@ -45,17 +45,17 @@ static uint32_t dram_vals[] = {
> 0x00000000, 0x00000000, 0x00010101, 0x01010101,
> 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
> 0x00000100, 0x00000100, 0x00000000, 0x00000002,
> - 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
> - 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,
> + 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
> + 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
> 0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
> 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
> 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
> 0x00000003, 0x00000000, 0x00000000, 0x00000000,
> 0x00000000, 0x00000000, 0x00000000, 0x00000000,
> 0x00000000, 0x00000000, 0x00000612, 0x01000F02,
> - 0x06120612, 0x00000200, 0x00020007, 0xf5014b27,
> - 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300,
> - 0x07000300, 0x07000300, 0x07000300, 0x00000006,
> + 0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
> + 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300,
> + 0x07000300, 0x07400300, 0x07400300, 0x00000005,
> 0x00000000, 0x00000000, 0x01000000, 0x01020408,
> 0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
> 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
> @@ -76,14 +76,14 @@ static uint32_t dram_vals[] = {
> 0x00000000, 0x00000000, 0x00000000, 0x00000000,
> 0x00000000, 0x00000000, 0x00000000, 0x00000000,
> 0x00000000, 0x00000000, 0x00000000, 0x00000000,
> - 0x00000000, 0x00000000, 0x00010000, 0x00020304,
> - 0x00000004, 0x00000000, 0x00000000, 0x00000000,
> + 0x00000000, 0x00000000, 0x00010000, 0x00030404,
> + 0x00000003, 0x00000000, 0x00000000, 0x00000000,
> 0x00000000, 0x00000000, 0x00000000, 0x01010000,
> 0x01000000, 0x03030000, 0x00010303, 0x01020202,
> 0x00000000, 0x02040303, 0x21002103, 0x00061200,
> - 0x06120612, 0x04320432, 0x04320432, 0x00040004,
> + 0x06120612, 0x04420442, 0x04420442, 0x00040004,
> 0x00040004, 0x00000000, 0x00000000, 0x00000000,
> - 0x00000000, 0x00010001
> + 0x00000000, 0xffffffff
>
> /*
> * i.MX23 DDR at 133MHz
>
next prev parent reply other threads:[~2013-03-19 6:52 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-28 22:59 [U-Boot] [PATCH v2] mxs: spl_mem_init: Align DDR2 init with FSL bootlets source Fabio Estevam
2013-03-06 13:44 ` Otavio Salvador
2013-03-06 14:31 ` Marek Vasut
2013-03-06 15:33 ` Otavio Salvador
2013-03-06 15:41 ` Marek Vasut
2013-03-06 15:44 ` Otavio Salvador
2013-03-06 15:46 ` Marek Vasut
2013-03-13 8:16 ` Stefano Babic
2013-03-13 14:18 ` Fabio Estevam
2013-03-13 14:22 ` Fabio Estevam
2013-03-14 5:09 ` Lauri Hintsala
2013-03-18 13:15 ` Otavio Salvador
2013-03-13 16:01 ` Marek Vasut
2013-03-13 16:07 ` Stefano Babic
2013-03-13 15:15 ` Marek Vasut
2013-03-19 6:52 ` Lauri Hintsala [this message]
2013-03-19 11:35 ` Otavio Salvador
2013-03-19 11:43 ` Lauri Hintsala
2013-03-23 16:56 ` Fabio Estevam
2013-03-19 12:36 ` Fabio Estevam
2013-03-20 5:17 ` Lauri Hintsala
2013-03-20 5:33 ` Fabio Estevam
2013-03-20 8:26 ` Stefano Babic
2013-03-20 10:07 ` Stefano Babic
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