From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Wed, 20 Mar 2013 11:07:29 +0100 Subject: [U-Boot] [PATCH v2] mxs: spl_mem_init: Align DDR2 init with FSL bootlets source In-Reply-To: <1362092359-16113-1-git-send-email-festevam@gmail.com> References: <1362092359-16113-1-git-send-email-festevam@gmail.com> Message-ID: <51498A61.1040502@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 28/02/2013 23:59, Fabio Estevam wrote: > From: Fabio Estevam > > Currently the following kernel hang happens when loading a 2.6.35 kernel from > Freeescale on a mx28evk board: > > RPC: Registered tcp transport module. > RPC: Registered tcp NFSv4.1 backchannel transport module. > Bus freq driver module loaded > IMX usb wakeup probe > usb h1 wakeup device is registered > mxs_cpu_init: cpufreq init finished > ... > Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================