* [U-Boot] [PATCH] arm: omap: emif: Support for ddr3 after warm reset
@ 2013-03-27 4:25 Lokesh Vutla
2013-03-27 5:11 ` Sricharan R
0 siblings, 1 reply; 3+ messages in thread
From: Lokesh Vutla @ 2013-03-27 4:25 UTC (permalink / raw)
To: u-boot
EMIF supports a global warm reset mode, during which the
EMIF keeps the SDRAM content. But if leveling is enabled
at the time of warm reset for DDR3, the following steps
needs to be done after warm reset:
1) Keep EMIF in self refresh mode.
2) Reset PHY to bring back the PHY to a known state.
3) Start Levelling procedure.
Doing the same.
And also enabling DLL lock and code output after warm reset.
Tested on OMAP5432 ES2.0
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 9eb1279..8811958 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1072,6 +1072,12 @@ static void do_sdram_init(u32 base)
else
ddr3_init(base, regs);
}
+ if (!in_sdram && warm_reset() &&
+ (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
+ set_lpmode_selfrefresh(base);
+ emif_reset_phy(base);
+ ddr3_leveling(base, regs);
+ }
/* Write to the shadow registers */
emif_update_timings(base, regs);
@@ -1259,10 +1265,10 @@ void sdram_init(void)
in_sdram = running_from_sdram();
debug("in_sdram = %d\n", in_sdram);
- if (!(in_sdram || warm_reset())) {
- if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+ if (!in_sdram) {
+ if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
bypass_dpll((*prcm)->cm_clkmode_dpll_core);
- else
+ else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 3+ messages in thread* [U-Boot] [PATCH] arm: omap: emif: Support for ddr3 after warm reset
2013-03-27 4:25 [U-Boot] [PATCH] arm: omap: emif: Support for ddr3 after warm reset Lokesh Vutla
@ 2013-03-27 5:11 ` Sricharan R
2013-03-27 5:43 ` Lokesh Vutla
0 siblings, 1 reply; 3+ messages in thread
From: Sricharan R @ 2013-03-27 5:11 UTC (permalink / raw)
To: u-boot
On Wednesday 27 March 2013 09:55 AM, Lokesh Vutla wrote:
> EMIF supports a global warm reset mode, during which the
> EMIF keeps the SDRAM content. But if leveling is enabled
> at the time of warm reset for DDR3, the following steps
> needs to be done after warm reset:
> 1) Keep EMIF in self refresh mode.
> 2) Reset PHY to bring back the PHY to a known state.
> 3) Start Levelling procedure.
> Doing the same.
> And also enabling DLL lock and code output after warm reset.
>
Should the $subject be something like
Fix DDR3 initialisation after warm reset ?
> Tested on OMAP5432 ES2.0
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
> arch/arm/cpu/armv7/omap-common/emif-common.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
> index 9eb1279..8811958 100644
> --- a/arch/arm/cpu/armv7/omap-common/emif-common.c
> +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
> @@ -1072,6 +1072,12 @@ static void do_sdram_init(u32 base)
> else
> ddr3_init(base, regs);
> }
> + if (!in_sdram && warm_reset() &&
> + (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
> + set_lpmode_selfrefresh(base);
> + emif_reset_phy(base);
> + ddr3_leveling(base, regs);
> + }
>
Why do we need !in_sdram check here ?. Otherwise, good..
Reviewed-by: R Sricharan <r.sricharan@ti.com>
Regards,
Sricharan
^ permalink raw reply [flat|nested] 3+ messages in thread* [U-Boot] [PATCH] arm: omap: emif: Support for ddr3 after warm reset
2013-03-27 5:11 ` Sricharan R
@ 2013-03-27 5:43 ` Lokesh Vutla
0 siblings, 0 replies; 3+ messages in thread
From: Lokesh Vutla @ 2013-03-27 5:43 UTC (permalink / raw)
To: u-boot
On Wednesday 27 March 2013 10:41 AM, Sricharan R wrote:
> On Wednesday 27 March 2013 09:55 AM, Lokesh Vutla wrote:
>> EMIF supports a global warm reset mode, during which the
>> EMIF keeps the SDRAM content. But if leveling is enabled
>> at the time of warm reset for DDR3, the following steps
>> needs to be done after warm reset:
>> 1) Keep EMIF in self refresh mode.
>> 2) Reset PHY to bring back the PHY to a known state.
>> 3) Start Levelling procedure.
>> Doing the same.
>> And also enabling DLL lock and code output after warm reset.
>>
>
> Should the $subject be something like
> Fix DDR3 initialisation after warm reset ?
Ok I ll change it.
>
>> Tested on OMAP5432 ES2.0
>>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> ---
>> arch/arm/cpu/armv7/omap-common/emif-common.c | 12 +++++++++---
>> 1 file changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
>> index 9eb1279..8811958 100644
>> --- a/arch/arm/cpu/armv7/omap-common/emif-common.c
>> +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
>> @@ -1072,6 +1072,12 @@ static void do_sdram_init(u32 base)
>> else
>> ddr3_init(base, regs);
>> }
>> + if (!in_sdram && warm_reset() &&
>> + (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
>> + set_lpmode_selfrefresh(base);
>> + emif_reset_phy(base);
>> + ddr3_leveling(base, regs);
>> + }
>>
>
> Why do we need !in_sdram check here ?. Otherwise, good..
DDR3 leveling cannot happen from SDRAM. So I kept a check here.
Thanks and Regards,
Lokesh
>
> Reviewed-by: R Sricharan <r.sricharan@ti.com>
>
>
> Regards,
> Sricharan
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2013-03-27 5:43 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-03-27 4:25 [U-Boot] [PATCH] arm: omap: emif: Support for ddr3 after warm reset Lokesh Vutla
2013-03-27 5:11 ` Sricharan R
2013-03-27 5:43 ` Lokesh Vutla
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox