* [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
@ 2012-11-30 6:29 Rajeshwari Shinde
2012-12-08 19:38 ` Simon Glass
2013-03-27 8:00 ` Minkyu Kang
0 siblings, 2 replies; 7+ messages in thread
From: Rajeshwari Shinde @ 2012-11-30 6:29 UTC (permalink / raw)
To: u-boot
This patch set adds L2 Cache Support to EXYNOS.
Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
arch/arm/cpu/armv7/exynos/soc.c | 37 +++++++++++++++++++++++++++++++++++++
1 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
index ab65b8d..676a388 100644
--- a/arch/arm/cpu/armv7/exynos/soc.c
+++ b/arch/arm/cpu/armv7/exynos/soc.c
@@ -23,6 +23,14 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/system.h>
+
+enum l2_cache_params {
+ CACHE_TAG_RAM_SETUP = (1<<9),
+ CACHE_DATA_RAM_SETUP = (1<<5),
+ CACHE_TAG_RAM_LATENCY = (2<<6),
+ CACHE_DATA_RAM_LATENCY = (2<<0)
+};
void reset_cpu(ulong addr)
{
@@ -36,3 +44,32 @@ void enable_caches(void)
dcache_enable();
}
#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Set L2 cache parameters
+ */
+static void exynos5_set_l2cache_params(void)
+{
+ unsigned int val = 0;
+
+ asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
+
+ val |= CACHE_TAG_RAM_SETUP |
+ CACHE_DATA_RAM_SETUP |
+ CACHE_TAG_RAM_LATENCY |
+ CACHE_DATA_RAM_LATENCY;
+
+ asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
+}
+
+/*
+ * Sets L2 cache related parameters before enabling data cache
+ */
+void v7_outer_cache_enable(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_l2cache_params();
+}
+#endif
+
--
1.7.4.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
2012-11-30 6:29 [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support Rajeshwari Shinde
@ 2012-12-08 19:38 ` Simon Glass
2012-12-08 19:38 ` Simon Glass
2012-12-27 5:59 ` Rajeshwari Birje
2013-03-27 8:00 ` Minkyu Kang
1 sibling, 2 replies; 7+ messages in thread
From: Simon Glass @ 2012-12-08 19:38 UTC (permalink / raw)
To: u-boot
On Thu, Nov 29, 2012 at 10:29 PM, Rajeshwari Shinde
<rajeshwari.s@samsung.com> wrote:
> This patch set adds L2 Cache Support to EXYNOS.
>
> Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
> ---
> arch/arm/cpu/armv7/exynos/soc.c | 37 +++++++++++++++++++++++++++++++++++++
> 1 files changed, 37 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
> index ab65b8d..676a388 100644
> --- a/arch/arm/cpu/armv7/exynos/soc.c
> +++ b/arch/arm/cpu/armv7/exynos/soc.c
> @@ -23,6 +23,14 @@
>
> #include <common.h>
> #include <asm/io.h>
> +#include <asm/system.h>
> +
> +enum l2_cache_params {
> + CACHE_TAG_RAM_SETUP = (1<<9),
> + CACHE_DATA_RAM_SETUP = (1<<5),
> + CACHE_TAG_RAM_LATENCY = (2<<6),
> + CACHE_DATA_RAM_LATENCY = (2<<0)
> +};
>
> void reset_cpu(ulong addr)
> {
> @@ -36,3 +44,32 @@ void enable_caches(void)
> dcache_enable();
> }
> #endif
> +
> +#ifndef CONFIG_SYS_L2CACHE_OFF
> +/*
> + * Set L2 cache parameters
> + */
> +static void exynos5_set_l2cache_params(void)
> +{
> + unsigned int val = 0;
> +
> + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
> +
> + val |= CACHE_TAG_RAM_SETUP |
> + CACHE_DATA_RAM_SETUP |
> + CACHE_TAG_RAM_LATENCY |
> + CACHE_DATA_RAM_LATENCY;
> +
> + asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
> +}
> +
> +/*
> + * Sets L2 cache related parameters before enabling data cache
> + */
> +void v7_outer_cache_enable(void)
> +{
> + if (cpu_is_exynos5())
> + exynos5_set_l2cache_params();
> +}
> +#endif
> +
> --
> 1.7.4.4
>
^ permalink raw reply [flat|nested] 7+ messages in thread* [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
2012-12-08 19:38 ` Simon Glass
@ 2012-12-08 19:38 ` Simon Glass
2012-12-10 9:00 ` Rajeshwari Birje
2012-12-27 5:59 ` Rajeshwari Birje
1 sibling, 1 reply; 7+ messages in thread
From: Simon Glass @ 2012-12-08 19:38 UTC (permalink / raw)
To: u-boot
On Sat, Dec 8, 2012 at 11:38 AM, Simon Glass <sjg@chromium.org> wrote:
> On Thu, Nov 29, 2012 at 10:29 PM, Rajeshwari Shinde
> <rajeshwari.s@samsung.com> wrote:
>> This patch set adds L2 Cache Support to EXYNOS.
>>
>> Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> Acked-by: Simon Glass <sjg@chromium.org>
>
BTW I am assuming this is v2? It looks like it.
Regards,
Simon
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
2012-12-08 19:38 ` Simon Glass
@ 2012-12-10 9:00 ` Rajeshwari Birje
0 siblings, 0 replies; 7+ messages in thread
From: Rajeshwari Birje @ 2012-12-10 9:00 UTC (permalink / raw)
To: u-boot
Hi Simon,
Yes it is a V2 patch.
Sorry I missed the add the same will submitting the patch.
Regards,
Rajeshwari Shinde.
On Sun, Dec 9, 2012 at 1:08 AM, Simon Glass <sjg@chromium.org> wrote:
> On Sat, Dec 8, 2012 at 11:38 AM, Simon Glass <sjg@chromium.org> wrote:
>> On Thu, Nov 29, 2012 at 10:29 PM, Rajeshwari Shinde
>> <rajeshwari.s@samsung.com> wrote:
>>> This patch set adds L2 Cache Support to EXYNOS.
>>>
>>> Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
>>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>>
>> Acked-by: Simon Glass <sjg@chromium.org>
>>
>
> BTW I am assuming this is v2? It looks like it.
>
> Regards,
> Simon
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
2012-12-08 19:38 ` Simon Glass
2012-12-08 19:38 ` Simon Glass
@ 2012-12-27 5:59 ` Rajeshwari Birje
2013-01-11 10:39 ` Rajeshwari Birje
1 sibling, 1 reply; 7+ messages in thread
From: Rajeshwari Birje @ 2012-12-27 5:59 UTC (permalink / raw)
To: u-boot
Hi Minkyu Kang,
Please do let me know if any comments regarding this patch.
Regards,
Rajeshwari Shinde.
On Sun, Dec 9, 2012 at 1:08 AM, Simon Glass <sjg@chromium.org> wrote:
> On Thu, Nov 29, 2012 at 10:29 PM, Rajeshwari Shinde
> <rajeshwari.s@samsung.com> wrote:
> > This patch set adds L2 Cache Support to EXYNOS.
> >
> > Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
> > Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> > ---
> > arch/arm/cpu/armv7/exynos/soc.c | 37
> +++++++++++++++++++++++++++++++++++++
> > 1 files changed, 37 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv7/exynos/soc.c
> b/arch/arm/cpu/armv7/exynos/soc.c
> > index ab65b8d..676a388 100644
> > --- a/arch/arm/cpu/armv7/exynos/soc.c
> > +++ b/arch/arm/cpu/armv7/exynos/soc.c
> > @@ -23,6 +23,14 @@
> >
> > #include <common.h>
> > #include <asm/io.h>
> > +#include <asm/system.h>
> > +
> > +enum l2_cache_params {
> > + CACHE_TAG_RAM_SETUP = (1<<9),
> > + CACHE_DATA_RAM_SETUP = (1<<5),
> > + CACHE_TAG_RAM_LATENCY = (2<<6),
> > + CACHE_DATA_RAM_LATENCY = (2<<0)
> > +};
> >
> > void reset_cpu(ulong addr)
> > {
> > @@ -36,3 +44,32 @@ void enable_caches(void)
> > dcache_enable();
> > }
> > #endif
> > +
> > +#ifndef CONFIG_SYS_L2CACHE_OFF
> > +/*
> > + * Set L2 cache parameters
> > + */
> > +static void exynos5_set_l2cache_params(void)
> > +{
> > + unsigned int val = 0;
> > +
> > + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
> > +
> > + val |= CACHE_TAG_RAM_SETUP |
> > + CACHE_DATA_RAM_SETUP |
> > + CACHE_TAG_RAM_LATENCY |
> > + CACHE_DATA_RAM_LATENCY;
> > +
> > + asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
> > +}
> > +
> > +/*
> > + * Sets L2 cache related parameters before enabling data cache
> > + */
> > +void v7_outer_cache_enable(void)
> > +{
> > + if (cpu_is_exynos5())
> > + exynos5_set_l2cache_params();
> > +}
> > +#endif
> > +
> > --
> > 1.7.4.4
> >
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 7+ messages in thread* [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
2012-12-27 5:59 ` Rajeshwari Birje
@ 2013-01-11 10:39 ` Rajeshwari Birje
0 siblings, 0 replies; 7+ messages in thread
From: Rajeshwari Birje @ 2013-01-11 10:39 UTC (permalink / raw)
To: u-boot
Hi Minkyu,
Please do let me know if any comments for same.
Regards,
Rajeshwari Shinde.
On Thu, Dec 27, 2012 at 11:29 AM, Rajeshwari Birje
<rajeshwari.birje@gmail.com> wrote:
> Minkyu Kang,
>
> Please do let me know if any comments regarding this patch.
>
> Regards,
> Rajeshwari Shinde.
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
2012-11-30 6:29 [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support Rajeshwari Shinde
2012-12-08 19:38 ` Simon Glass
@ 2013-03-27 8:00 ` Minkyu Kang
1 sibling, 0 replies; 7+ messages in thread
From: Minkyu Kang @ 2013-03-27 8:00 UTC (permalink / raw)
To: u-boot
On 30/11/12 15:29, Rajeshwari Shinde wrote:
> This patch set adds L2 Cache Support to EXYNOS.
>
> Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
> arch/arm/cpu/armv7/exynos/soc.c | 37 +++++++++++++++++++++++++++++++++++++
> 1 files changed, 37 insertions(+), 0 deletions(-)
>
Sorry! too late.
appiled to u-boot-samsung.
Thanks,
Minkyu Kang.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2013-03-27 8:00 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-11-30 6:29 [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support Rajeshwari Shinde
2012-12-08 19:38 ` Simon Glass
2012-12-08 19:38 ` Simon Glass
2012-12-10 9:00 ` Rajeshwari Birje
2012-12-27 5:59 ` Rajeshwari Birje
2013-01-11 10:39 ` Rajeshwari Birje
2013-03-27 8:00 ` Minkyu Kang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox