From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Nelson Date: Wed, 03 Apr 2013 06:38:12 -0700 Subject: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix waiting for DMA operation completion In-Reply-To: <6C5EA58090A5ED459815C4D04C2B466FD931DFA2@EU-MBX-03.mgc.mentorg.com> References: <1364897095-28227-1-git-send-email-andrew_gabbasov@mentor.com>, <515AFE1E.801@boundarydevices.com> <6C5EA58090A5ED459815C4D04C2B466FD931DF69@EU-MBX-03.mgc.mentorg.com>, <515B4FDB.9020902@boundarydevices.com> <6C5EA58090A5ED459815C4D04C2B466FD931DFA2@EU-MBX-03.mgc.mentorg.com> Message-ID: <515C30C4.1030802@boundarydevices.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Andrew, On 04/02/2013 11:48 PM, Gabbasov, Andrew wrote: >>>> On 04/02/2013 03:04 AM, Andrew Gabbasov wrote: >>>>> On iMX6 sometimes the Transfer Complete interrupt occurs earlier >>>>> than the DMA part completes its operation. If immediately after that >>>>> the read data is used for some data verification, those obtained data >>>>> may be incomplete, which causes intermittent verification failures. >>>>> >>>> >>>> Can you describe how to repeat this? >>>> >>>>> For example, when the default environment command tries to load and run >>>>> boot script from FAT partition on SD/MMC card, it sometimes fails, >>>>> reporting invalid partition table, or unknown partition type, or >>>>> something else of that kind. Such errors disappear if the build >>>>> configuration has CONFIG_SYS_FSL_ESDHC_USE_PIO, or if some delay >>>>> is added after transfer completion. >>>>> >>> >> >> >> >> Looking at the code with fresh eyes, it appears that >> the cache invalidate is in the wrong place (after >> "command complete" but before "transfer complete" >> is checked). >> >> >> >> Andrew, can you test with this patch to see if >> it also addresses the issue? >> > Hi Eric, > > Yes, this patch seems to fix the issue too. > Thanks for testing. > I think, it would be useful to have both patches. Although invalidating cache > (by adding some delay) indirectly helps with waiting for DMA End event, > it is probably worth having explicit DMA completion waiting patch too. > I agree wholeheartedly. I do wonder if the previous loop should be re-worked though. It seems that we should be waiting for TC & (DINT|DMAE) on all processor variants and the previous loop has tests for timeout and data errors. Regards, Eric