From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Nelson Date: Wed, 17 Apr 2013 11:57:45 -0700 Subject: [U-Boot] [PATCH] imx: mx6q_4x_mt41j128.cfg: Setup CCM_CCOSR register In-Reply-To: <1366223610-29127-1-git-send-email-festevam@gmail.com> References: <1366223610-29127-1-git-send-email-festevam@gmail.com> Message-ID: <516EF0A9.8060507@boundarydevices.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Thanks Fabio, On 04/17/2013 11:33 AM, Fabio Estevam wrote: > From: Fabio Estevam > > Setup CCM_CCOSR register to provide a CKO1 clock frequency of 16.5 MHz. > > CKO1 drives sgtl5000 codec clock on mx6qsabrelite and doing this setup in the > bootloader will allow us to remove a lot of code in arch/arm/mach-imx/mach-imx6q.c > from the mainline kernel. > More importantly than eliminating code in the mainline kernel, enabling the clock will remove squeal after an ungraceful reboot (watchdog) if hooked up to speakers. I believe you can see this under Android by issuing a 'reboot' command. We've been meaning to push a patch for this for a while. We did it in two parts. 1.) Add routine to enable the clock: https://github.com/boundarydevices/u-boot-imx6/commit/7087d645ea1ad476825ea96a1b6f3747f5980028 2.) Enable it on each of SABRE Lite, Nitrogen6X and one of our custom boards. https://github.com/boundarydevices/u-boot-imx6/commit/44b1015f69b52c0a7d7b930b0607af7a724e29bb > mx6q_4x_mt41j128.cfg is also used by mx6qsabresd, and it is safe to use it for > this board as well. > Does wandboard also use SGTL5000 connected up to CKO1? > Signed-off-by: Fabio Estevam > --- > board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg > index f4cae5e..4661775 100644 > --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg > +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg > @@ -172,3 +172,14 @@ DATA 4 0x020e0010 0xF00000CF > /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ > DATA 4 0x020e0018 0x007F007F > DATA 4 0x020e001c 0x007F007F > + > +/* > + * Setup CCM_CCOSR register as follows: > + * > + * cko1_en = 1 --> CKO1 enabled > + * cko1_div = 111 --> divide by 8 > + * cko1_sel = 1011 --> ahb_clk_root > + * > + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz > + */ > +DATA 4 0x020c4060 0x000000fb >