From mboxrd@z Thu Jan  1 00:00:00 1970
From: Bo Shen <voice.shen@atmel.com>
Date: Thu, 18 Apr 2013 09:23:48 +0800
Subject: [U-Boot] phy ic isn't reset
In-Reply-To: <1cdeaab7.eb01.13e178acf19.Coremail.laub923@163.com>
References: <1cdeaab7.eb01.13e178acf19.Coremail.laub923@163.com>
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To: u-boot@lists.denx.de

Hi Alex,

On 4/17/2013 18:29, alex wrote:
> Hi:
>    I work on one board based on at9g25evk board now. I find one issue
> that phy IC isn't reset, so network can't work. Only the different
> crystal with evk board is connected to PHY IC. I copy the phy-reset part
> of at9260 to at9g25. It can work now. Please the maintainer of at9gx5
> check this. The modification I do is as below:

As you mentioned, you use different crystal, please specify this in detail.

> +
> +#ifdef CONFIG_MACB
> +int at91sam9x5ek_macb_hw_init(void)
> +{
> +        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> +        struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
> +       struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
> +       unsigned long erstl;
> +
> +        /* Enable EMAC clock */
> +        writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
> +
> +       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
> +
> +       /* Need to reset PHY -> 500ms reset */
> +       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
> +                       AT91_RSTC_MR_URSTEN, &rstc->mr);
> +
> +       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
> +
> +       /* Wait for end hardware reset */
> +       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
> +               ;
> +
> +       /* Restore NRST value */
> +       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
> +                       &rstc->mr);
> +
> +       at91_macb_hw_init();
> +}
> +#endif

On at91sam9g25ek, it don't need this patch. The network work properly.

Btw, please help provide the log information for why not ethernet 
doesn't work.

Best Regards,
Bo Shen

>
> Best Regards,
> Alex
>
>