[U-Boot] [Patch v2, batch 2 03/23] powerpc/pcie: add PCIe version 3.x support

[York Sun <yorksun@freescale.com>]

Andy,

I think I caught this issue and asked Roy to submit another patch to fix
it http://patchwork.ozlabs.org/patch/230825/

York

On 05/13/2013 11:50 AM, Andy Fleming wrote:
> This patch causes all sorts of problems. I'm NACKing it for now. Please
> make sure none of these changes break 83xx before re-submitting.
> 
> 
> On Mon, Mar 25, 2013 at 12:33 PM, York Sun <yorksun@freescale.com
> <mailto:yorksun@freescale.com>> wrote:
> 
>     From: Roy ZANG <tie-fei.zang@freescale.com
>     <mailto:tie-fei.zang@freescale.com>>
> 
>     T4240 PCIe IP is version 3.0 and has some update comparing previous
>     QorIQ products.
> 
>     1.  Move Freescale specific register define
>     to
>     arch/powerpc/include/asm/fsl_pci.h
>     and update the register offset define for T4240.
> 
>     2. add the status/control register define
>     use status/control register to judge the link status
> 
>     3. The original code uses 'Programming Interface' field to judge if
>     PCIE is
>     EP or RC mode, however, T4240 does not support this functionality.
>     According to PCIE specification, 'Header Type' offset 0x0e is used to
>     indicate header type, so for PCIE controller, the patch changes code to
>     use 'Header Type' field to identify if the PCIE is RC or EP mode.
> 
>     Signed-off-by: Roy Zang <tie-fei.zang@freescale.com
>     <mailto:tie-fei.zang@freescale.com>>
>     Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com
>     <mailto:Minghuan.Lian@freescale.com>>
>     ---
>      arch/powerpc/include/asm/config_mpc85xx.h |    1 +
>      arch/powerpc/include/asm/fsl_pci.h        |   35
>     +++++++++++++++++++++++++++--
>      drivers/pci/fsl_pci_init.c                |   20 ++++++++++++-----
>      include/pci.h                             |    7 ------
>      4 files changed, 48 insertions(+), 15 deletions(-)
> 
> 
> [...] 
>  
> 
>     index 15f583f..c0ed553 100644
>     --- a/include/pci.h
>     +++ b/include/pci.h
>     @@ -426,13 +426,6 @@
>      #define PCI_MAX_PCI_DEVICES    32
>      #define PCI_MAX_PCI_FUNCTIONS  8
> 
>     -#define PCI_DCR                0x54    /* PCIe Device Control
>     Register */
>     -#define PCI_DSR                0x56    /* PCIe Device Status
>     Register */
>     -#define PCI_LSR                0x5e    /* PCIe Link Status Register */
>     -#define PCI_LCR                0x5c    /* PCIe Link Control Register */
>     -#define PCI_LTSSM      0x404   /* PCIe Link Training, Status State
>     Machine */
>     -#define  PCI_LTSSM_L0  0x16    /* L0 state */
> 
> 
> 
> These were being used by 83xx as well, and are now unavailable. Please
> devise a solution that works for all of our platforms.
> 
> Andy