* [U-Boot] [PATCH v2 0/6] arm: mvf600: Add Freescale Vybrid MVF600 CPU and MVF600TWR board support
@ 2013-05-14 9:51 Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support Alison Wang
` (5 more replies)
0 siblings, 6 replies; 25+ messages in thread
From: Alison Wang @ 2013-05-14 9:51 UTC (permalink / raw)
To: u-boot
This series contain the support for Freescale Vybrid MVF600 CPU and MVF600TWR board.
Vybird devices are built on an asymmetrical-multiprocessing architecture
using ARM cores. The families in the Vybrid portfolio span entry-level,
single core Cortex-A class SoCs all the way to dual heterogeneous core SoCs
with multiple communication and connectivity options.
Part of the Vybrid platform, MVF600 is a dual-core eMPU combining the ARM
Cortex A5 and Cortex M4 cores.
The u-boot runs on Cortex A5 core.
MVF600 shares some IPs with i.MX family, such as FEC,ESDHC,WATCHDOG,I2C,ASRC and ESAI.
MVF600 also shares some IPs with ColdFire family, such as eDMA and DSPI.
MVF600 still has its own IPs, such as PIT,SAI,UART,QSPI and DCU.
More documents for this soc can be found at:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=VF6xx&fsrch=1&sr=5
http://www.freescale.com/webapp/sps/site/homepage.jsp?code=VYBRID
Changes in v2:
- Remove vybrid-common directory
- Rename directory name 'vybrid' to 'mvf600'
- Add generic.c file
- Rewrite get_reset_cause() to make it readable
- Remove reset_cpu(), and use the function in imx_watchdog.c
- Rewrite timer.c file
- Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk()
- Remove lowlevel_init.S, and add clock_init() in board_early_init_f()
- Remove useless CONFIG_SYS_ defines
- Move CONFIG_MACH_TYPE to board configuration file
- Define C structures and access C structures to set/read registers
- Remove useless errata
- Remove useless macros
- Rename directory name 'arch-vybrid' to 'arch-mvf600'
- Use common iomux-v3 code
- Use common FEC driver fec_mxc.c
- Add watchdog support
- Add an entry to MAINTAINERS file
- Rename directory name 'vybird' to 'mvf600twr'
- Use standard method to set gd->ram_size
- Rewrite board_mmc_getcd() function
- Remove useless undef
- Remove hardcoded IP addresses and MAC addresses
- Move CONFIG_MACH_TYPE to board configuration file
----------------------------------------------------------------
Alison Wang (6):
arm: mvf600: Add Vybrid MVF600 CPU support
arm: mvf600: Add IOMUX support for Vybrid MVF600
arm: mvf600: Add FEC support for Vybrid MVF600
arm: mvf600: Add watchdog support for Vybrid MVF600
arm: mvf600: Add uart support for Vybrid MVF600
arm: mvf600: Add basic support for Vybrid MVF600TWR board
MAINTAINERS | 4 ++
Makefile | 2 +-
arch/arm/cpu/armv7/mvf600/Makefile | 42 +++++++++++
arch/arm/cpu/armv7/mvf600/generic.c | 309 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/cpu/armv7/mvf600/timer.c | 144 ++++++++++++++++++++++++++++++++++++++
arch/arm/imx-common/Makefile | 2 +-
arch/arm/imx-common/iomux-v3.c | 6 ++
arch/arm/include/asm/arch-mvf600/clock.h | 38 ++++++++++
arch/arm/include/asm/arch-mvf600/crm_regs.h | 170 ++++++++++++++++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-mvf600/imx-regs.h | 201 ++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-mvf600/mvf_pins.h | 92 ++++++++++++++++++++++++
arch/arm/include/asm/imx-common/iomux-v3.h | 18 +++++
board/freescale/mvf600twr/Makefile | 39 +++++++++++
board/freescale/mvf600twr/imximage.cfg | 35 ++++++++++
board/freescale/mvf600twr/mvf600twr.c | 403 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
boards.cfg | 1 +
drivers/net/fec_mxc.c | 6 +-
drivers/serial/Makefile | 1 +
drivers/serial/serial_lpuart.c | 161 ++++++++++++++++++++++++++++++++++++++++++
drivers/watchdog/Makefile | 2 +-
include/configs/mvf600twr.h | 147 ++++++++++++++++++++++++++++++++++++++
21 files changed, 1819 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv7/mvf600/Makefile
create mode 100644 arch/arm/cpu/armv7/mvf600/generic.c
create mode 100644 arch/arm/cpu/armv7/mvf600/timer.c
create mode 100644 arch/arm/include/asm/arch-mvf600/clock.h
create mode 100644 arch/arm/include/asm/arch-mvf600/crm_regs.h
create mode 100644 arch/arm/include/asm/arch-mvf600/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-mvf600/mvf_pins.h
create mode 100644 board/freescale/mvf600twr/Makefile
create mode 100644 board/freescale/mvf600twr/imximage.cfg
create mode 100644 board/freescale/mvf600twr/mvf600twr.c
create mode 100644 drivers/serial/serial_lpuart.c
create mode 100644 include/configs/mvf600twr.h
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support
2013-05-14 9:51 [U-Boot] [PATCH v2 0/6] arm: mvf600: Add Freescale Vybrid MVF600 CPU and MVF600TWR board support Alison Wang
@ 2013-05-14 9:51 ` Alison Wang
2013-05-15 8:13 ` Stefano Babic
2013-05-14 9:51 ` [U-Boot] [PATCH v2 2/6] arm: mvf600: Add IOMUX support for Vybrid MVF600 Alison Wang
` (4 subsequent siblings)
5 siblings, 1 reply; 25+ messages in thread
From: Alison Wang @ 2013-05-14 9:51 UTC (permalink / raw)
To: u-boot
This patch adds generic codes to support Freescale's Vybrid MVF600 CPU.
It aligns Vybrid MVF600 platform with i.MX platform. As there are
some differences between MVF600 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/mvf600 directory.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
Changes in v2:
- Remove vybrid-common directory
- Rename directory name 'vybrid' to 'mvf600'
- Add generic.c file
- Rewrite get_reset_cause() to make it readable
- Remove reset_cpu(), and use the function in imx_watchdog.c
- Rewrite timer.c file
- Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk()
- Remove lowlevel_init.S, and add clock_init() in board_early_init_f()
- Remove useless CONFIG_SYS_ defines
- Move CONFIG_MACH_TYPE to board configuration file
- Define C structures and access C structures to set/read registers
- Remove useless errata
- Remove useless macros
- Rename directory 'arch-vybrid' to 'arch-mvf600'
Makefile | 2 +-
arch/arm/cpu/armv7/mvf600/Makefile | 42 ++++
arch/arm/cpu/armv7/mvf600/generic.c | 309 ++++++++++++++++++++++++++++
arch/arm/cpu/armv7/mvf600/timer.c | 144 +++++++++++++
arch/arm/include/asm/arch-mvf600/clock.h | 38 ++++
arch/arm/include/asm/arch-mvf600/crm_regs.h | 170 +++++++++++++++
arch/arm/include/asm/arch-mvf600/imx-regs.h | 201 ++++++++++++++++++
arch/arm/include/asm/arch-mvf600/mvf_pins.h | 92 +++++++++
8 files changed, 997 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/mvf600/Makefile
create mode 100644 arch/arm/cpu/armv7/mvf600/generic.c
create mode 100644 arch/arm/cpu/armv7/mvf600/timer.c
create mode 100644 arch/arm/include/asm/arch-mvf600/clock.h
create mode 100644 arch/arm/include/asm/arch-mvf600/crm_regs.h
create mode 100644 arch/arm/include/asm/arch-mvf600/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-mvf600/mvf_pins.h
diff --git a/Makefile b/Makefile
index c52f0f1..9df2138 100644
--- a/Makefile
+++ b/Makefile
@@ -341,7 +341,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs mvf600))
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
endif
diff --git a/arch/arm/cpu/armv7/mvf600/Makefile b/arch/arm/cpu/armv7/mvf600/Makefile
new file mode 100644
index 0000000..9232cd4
--- /dev/null
+++ b/arch/arm/cpu/armv7/mvf600/Makefile
@@ -0,0 +1,42 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS += generic.o
+COBJS += timer.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/mvf600/generic.c b/arch/arm/cpu/armv7/mvf600/generic.c
new file mode 100644
index 0000000..f21ce73
--- /dev/null
+++ b/arch/arm/cpu/armv7/mvf600/generic.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <netdev.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+static u32 get_mcu_main_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_ccsr, ccm_cacrr, armclk_div;
+ u32 sysclk_sel, pll_pfd_sel = 0;
+ u32 freq = 0;
+
+ ccm_ccsr = readl(&ccm->ccsr);
+ sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
+ sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+ armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
+ armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
+ armclk_div += 1;
+
+ switch (sysclk_sel) {
+ case 0:
+ freq = FASE_CLK_FREQ;
+ break;
+ case 1:
+ freq = SLOW_CLK_FREQ;
+ break;
+ case 2:
+ pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
+ pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
+ if (pll_pfd_sel == 0)
+ freq = PLL2_MAIN_FREQ;
+ else if (pll_pfd_sel == 1)
+ freq = PLL2_PFD1_FREQ;
+ else if (pll_pfd_sel == 2)
+ freq = PLL2_PFD2_FREQ;
+ else if (pll_pfd_sel == 3)
+ freq = PLL2_PFD3_FREQ;
+ else if (pll_pfd_sel == 4)
+ freq = PLL2_PFD4_FREQ;
+ break;
+ case 3:
+ freq = PLL2_MAIN_FREQ;
+ break;
+ case 4:
+ pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
+ pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
+ if (pll_pfd_sel == 0)
+ freq = PLL1_MAIN_FREQ;
+ else if (pll_pfd_sel == 1)
+ freq = PLL1_PFD1_FREQ;
+ else if (pll_pfd_sel == 2)
+ freq = PLL1_PFD2_FREQ;
+ else if (pll_pfd_sel == 3)
+ freq = PLL1_PFD3_FREQ;
+ else if (pll_pfd_sel == 4)
+ freq = PLL1_PFD4_FREQ;
+ break;
+ case 5:
+ freq = PLL3_MAIN_FREQ;
+ break;
+ default:
+ printf("unsupported system clock select\n");
+ }
+
+ return freq / armclk_div;
+}
+
+static u32 get_bus_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cacrr, busclk_div;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+
+ busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
+ busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
+ busclk_div += 1;
+
+ return get_mcu_main_clk() / busclk_div;
+}
+
+static u32 get_ipg_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cacrr, ipgclk_div;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+
+ ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
+ ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
+ ipgclk_div += 1;
+
+ return get_bus_clk() / ipgclk_div;
+}
+
+static u32 get_uart_clk(void)
+{
+ return get_ipg_clk();
+}
+
+static u32 get_sdhc_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
+ u32 freq = 0;
+
+ ccm_cscmr1 = readl(&ccm->cscmr1);
+ sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
+ sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
+
+ ccm_cscdr2 = readl(&ccm->cscdr2);
+ sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
+ sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
+ sdhc_clk_div += 1;
+
+ switch (sdhc_clk_sel) {
+ case 0:
+ freq = PLL3_MAIN_FREQ;
+ break;
+ case 1:
+ freq = PLL3_PFD3_FREQ;
+ break;
+ case 2:
+ freq = PLL1_PFD3_FREQ;
+ break;
+ case 3:
+ freq = get_bus_clk();
+ break;
+ }
+
+ return freq / sdhc_clk_div;
+}
+
+u32 get_fec_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cscmr2, rmii_clk_sel;
+ u32 freq = 0;
+
+ ccm_cscmr2 = readl(&ccm->cscmr2);
+ rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
+ rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
+
+ switch (rmii_clk_sel) {
+ case 0:
+ freq = ENET_EXTERNAL_CLK;
+ break;
+ case 1:
+ freq = AUDIO_EXTERNAL_CLK;
+ break;
+ case 2:
+ freq = PLL5_MAIN_FREQ;
+ break;
+ case 3:
+ freq = PLL5_MAIN_FREQ / 2;
+ break;
+ }
+
+ return freq;
+}
+
+unsigned int mvf_get_clock(enum mvf_clock clk)
+{
+ switch (clk) {
+ case MVF_ARM_CLK:
+ return get_mcu_main_clk();
+ case MVF_BUS_CLK:
+ return get_bus_clk();
+ case MVF_IPG_CLK:
+ return get_ipg_clk();
+ case MVF_UART_CLK:
+ return get_uart_clk();
+ case MVF_ESDHC_CLK:
+ return get_sdhc_clk();
+ case MVF_FEC_CLK:
+ return get_fec_clk();
+ default:
+ break;
+ }
+ return -1;
+}
+
+/* Dump some core clocks */
+int do_mvf600_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ printf("\n");
+ printf("cpu clock : %8d MHz\n", mvf_get_clock(MVF_ARM_CLK) / 1000000);
+ printf("bus clock : %8d MHz\n", mvf_get_clock(MVF_BUS_CLK) / 1000000);
+ printf("ipg clock : %8d MHz\n", mvf_get_clock(MVF_IPG_CLK) / 1000000);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_mvf600_showclocks,
+ "display clocks",
+ ""
+);
+
+#ifdef CONFIG_FEC_MXC
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
+ struct fuse_bank4_regs *fuse =
+ (struct fuse_bank4_regs *)bank->fuse_regs;
+
+ u32 value = readl(&fuse->mac_addr0);
+ mac[0] = (value >> 8);
+ mac[1] = value;
+
+ value = readl(&fuse->mac_addr1);
+ mac[2] = value >> 24;
+ mac[3] = value >> 16;
+ mac[4] = value >> 8;
+ mac[5] = value;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+ u32 cause;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ cause = readl(&src_regs->srsr);
+ writel(cause, &src_regs->srsr);
+ cause &= 0xff;
+
+ switch (cause) {
+ case 0x08:
+ return "WDOG";
+ case 0x20:
+ return "JTAG HIGH-Z";
+ case 0x80:
+ return "EXTERNAL RESET";
+ case 0xfd:
+ return "POR";
+ default:
+ return "unknown reset";
+ }
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: Freescale Vybrid MVF600 at %d MHz\n",
+ mvf_get_clock(MVF_ARM_CLK) / 1000000);
+ printf("Reset cause: %s\n", get_reset_cause());
+
+ return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+ rc = fecmxc_initialize(bis);
+#endif
+
+ return rc;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+ return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+ gd->arch.sdhc_clk = mvf_get_clock(MVF_ESDHC_CLK);
+#endif
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/mvf600/timer.c b/arch/arm/cpu/armv7/mvf600/timer.c
new file mode 100644
index 0000000..99ca57d
--- /dev/null
+++ b/arch/arm/cpu/armv7/mvf600/timer.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+/* Periodic interrupt timer registers */
+struct pit_reg {
+ u32 mcr;
+ u32 recv0[55];
+ u32 ltmr64h;
+ u32 ltmr64l;
+ u32 recv1[6];
+ u32 ldval0;
+ u32 cval0;
+ u32 tctrl0;
+ u32 tflg0;
+ u32 ldval1;
+ u32 cval1;
+ u32 tctrl1;
+ u32 tflg1;
+ u32 ldval2;
+ u32 cval2;
+ u32 tctrl2;
+ u32 tflg2;
+ u32 ldval3;
+ u32 cval3;
+ u32 tctrl3;
+ u32 tflg3;
+ u32 ldval4;
+ u32 cval4;
+ u32 tctrl4;
+ u32 tflg4;
+ u32 ldval5;
+ u32 cval5;
+ u32 tctrl5;
+ u32 tflg5;
+ u32 ldval6;
+ u32 cval6;
+ u32 tctrl6;
+ u32 tflg6;
+ u32 ldval7;
+ u32 cval7;
+ u32 tctrl7;
+ u32 tflg7;
+};
+
+static struct pit_reg *cur_pit = (struct pit_reg *)PIT_BASE_ADDR;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, mvf_get_clock(MVF_IPG_CLK));
+
+ return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+ usec = usec * mvf_get_clock(MVF_IPG_CLK) + 999999;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+int timer_init(void)
+{
+ __raw_writel(0, &cur_pit->mcr);
+
+ __raw_writel(TIMER_LOAD_VAL, &cur_pit->ldval1);
+ __raw_writel(0, &cur_pit->tctrl1);
+ __raw_writel(1, &cur_pit->tctrl1);
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+ ulong now = TIMER_LOAD_VAL - __raw_readl(&cur_pit->cval1);
+
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
+
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+ulong get_timer_masked(void)
+{
+ return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+ unsigned long long start;
+ ulong tmo;
+
+ start = get_ticks(); /* get current timestamp */
+ tmo = us_to_tick(usec); /* convert usecs to ticks */
+ while ((get_ticks() - start) < tmo)
+ ; /* loop till time has passed */
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return mvf_get_clock(MVF_IPG_CLK);
+}
diff --git a/arch/arm/include/asm/arch-mvf600/clock.h b/arch/arm/include/asm/arch-mvf600/clock.h
new file mode 100644
index 0000000..889d4d9
--- /dev/null
+++ b/arch/arm/include/asm/arch-mvf600/clock.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+enum mvf_clock {
+ MVF_ARM_CLK = 0,
+ MVF_BUS_CLK,
+ MVF_IPG_CLK,
+ MVF_UART_CLK,
+ MVF_ESDHC_CLK,
+ MVF_FEC_CLK,
+};
+
+unsigned int mvf_get_clock(enum mvf_clock clk);
+
+#define imx_get_fecclk() mvf_get_clock(MVF_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mvf600/crm_regs.h b/arch/arm/include/asm/arch-mvf600/crm_regs.h
new file mode 100644
index 0000000..4e51a67
--- /dev/null
+++ b/arch/arm/include/asm/arch-mvf600/crm_regs.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_ARM_MACH_MVF_CCM_REGS_H__
+#define __ARCH_ARM_MACH_MVF_CCM_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+/* Clock Controller Module (CCM) */
+struct ccm_reg {
+ u32 ccr;
+ u32 csr;
+ u32 ccsr;
+ u32 cacrr;
+ u32 cscmr1;
+ u32 cscdr1;
+ u32 cscdr2;
+ u32 cscdr3;
+ u32 cscmr2;
+ u32 cscdr4;
+ u32 ctor;
+ u32 clpcr;
+ u32 cisr;
+ u32 cimr;
+ u32 ccosr;
+ u32 cgpr;
+ u32 ccgr0;
+ u32 ccgr1;
+ u32 ccgr2;
+ u32 ccgr3;
+ u32 ccgr4;
+ u32 ccgr5;
+ u32 ccgr6;
+ u32 ccgr7;
+ u32 ccgr8;
+ u32 ccgr9;
+ u32 ccgr10;
+ u32 ccgr11;
+ u32 cmeor0;
+ u32 cmeor1;
+ u32 cmeor2;
+ u32 cmeor3;
+ u32 cmeor4;
+ u32 cmeor5;
+ u32 cppdsr;
+ u32 ccowr;
+ u32 ccpgr0;
+ u32 ccpgr1;
+ u32 ccpgr2;
+ u32 ccpgr3;
+};
+
+/* Analog components control digital interface (ANADIG) */
+struct anadig_reg {
+ u32 pll3_ctrl;
+ u32 resv0[3];
+ u32 pll7_ctrl;
+ u32 resv1[3];
+ u32 pll2_ctrl;
+ u32 resv2[3];
+ u32 pll2_ss;
+ u32 resv3[3];
+ u32 pll2_num;
+ u32 resv4[3];
+ u32 pll2_denom;
+ u32 resv5[3];
+ u32 pll4_ctrl;
+ u32 resv6[3];
+ u32 pll4_num;
+ u32 resv7[3];
+ u32 pll4_denom;
+ u32 pll6_ctrl;
+ u32 resv8[3];
+ u32 pll6_num;
+ u32 resv9[3];
+ u32 pll6_denom;
+ u32 resv10[3];
+ u32 pll5_ctrl;
+ u32 resv11[3];
+ u32 pll3_pfd;
+ u32 resv12[3];
+ u32 pll2_pfd;
+ u32 resv13[3];
+ u32 reg_1p1;
+ u32 resv14[3];
+ u32 reg_3p0;
+ u32 resv15[3];
+ u32 reg_2p5;
+ u32 resv16[7];
+ u32 ana_misc0;
+ u32 resv17[3];
+ u32 ana_misc1;
+ u32 resv18[63];
+ u32 anadig_digprog;
+ u32 resv19[3];
+ u32 pll1_ctrl;
+ u32 resv20[3];
+ u32 pll1_ss;
+ u32 resv21[3];
+ u32 pll1_num;
+ u32 resv22[3];
+ u32 pll1_denom;
+ u32 resv23[3];
+ u32 pll1_pdf;
+ u32 resv24[3];
+ u32 pll_lock;
+};
+#endif
+
+#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
+#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
+
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
+
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
+
+#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
+#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
+#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
+#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
+#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
+#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
+
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
+
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
+
+#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
+#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
+
+#define FASE_CLK_FREQ 24000000
+#define SLOW_CLK_FREQ 32000
+#define PLL1_PFD1_FREQ 500000000
+#define PLL1_PFD2_FREQ 452000000
+#define PLL1_PFD3_FREQ 396000000
+#define PLL1_PFD4_FREQ 528000000
+#define PLL1_MAIN_FREQ 528000000
+#define PLL2_PFD1_FREQ 500000000
+#define PLL2_PFD2_FREQ 396000000
+#define PLL2_PFD3_FREQ 339000000
+#define PLL2_PFD4_FREQ 413000000
+#define PLL2_MAIN_FREQ 528000000
+#define PLL3_MAIN_FREQ 480000000
+#define PLL3_PFD3_FREQ 298000000
+#define PLL5_MAIN_FREQ 500000000
+
+#define ENET_EXTERNAL_CLK 50000000
+#define AUDIO_EXTERNAL_CLK 24576000
+
+#endif /*__ARCH_ARM_MACH_MVF_CCM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mvf600/imx-regs.h b/arch/arm/include/asm/arch-mvf600/imx-regs.h
new file mode 100644
index 0000000..8e247c9
--- /dev/null
+++ b/arch/arm/include/asm/arch-mvf600/imx-regs.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
+#define IRAM_SIZE 0x00080000 /* 512 KB */
+
+#define AIPS0_BASE_ADDR 0x40000000
+#define AIPS1_BASE_ADDR 0x40080000
+
+/* AIPS 0 */
+#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
+#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
+#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
+#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
+#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000)
+#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000)
+#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
+#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
+#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000)
+#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
+#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000)
+#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000)
+#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
+#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000)
+#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000)
+#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000)
+#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000)
+#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000)
+#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000)
+#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000)
+#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000)
+#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000)
+#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000)
+#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000)
+#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000)
+#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000)
+#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000)
+#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000)
+#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000)
+#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000)
+#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000)
+#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
+#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
+#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
+#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
+#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
+#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
+#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
+#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000)
+#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000)
+#define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
+#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000)
+#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
+#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000)
+#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
+#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
+#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
+#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
+#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
+#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
+#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
+#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
+#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
+#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
+#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
+#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
+#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
+#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
+#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
+#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
+
+/* AIPS 1 */
+#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)
+#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
+#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
+#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
+
+#define FEC_QUIRK_ENET_MAC
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* System Reset Controller (SRC) */
+struct src {
+ u32 scr;
+ u32 sbmr1;
+ u32 srsr;
+ u32 secr;
+ u32 gpsr;
+ u32 sicr;
+ u32 simr;
+ u32 sbmr2;
+ u32 gpr0;
+ u32 gpr1;
+ u32 gpr2;
+ u32 gpr3;
+ u32 gpr4;
+ u32 hab0;
+ u32 hab1;
+ u32 hab2;
+ u32 hab3;
+ u32 hab4;
+ u32 hab5;
+ u32 misc0;
+ u32 misc1;
+ u32 misc2;
+ u32 misc3;
+};
+
+/* Watchdog Timer (WDOG) */
+struct wdog_regs {
+ u16 wcr;
+ u16 wsr;
+ u16 wrsr;
+ u16 wicr;
+ u16 wmcr;
+};
+
+/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */
+struct ddrmr_regs {
+ u32 cr[162];
+ u32 rsvd[94];
+ u32 phy[53];
+};
+
+/* On-Chip One Time Programmable Controller (OCOTP) */
+struct ocotp_regs {
+ u32 ctrl;
+ u32 ctrl_set;
+ u32 ctrl_clr;
+ u32 ctrl_tog;
+ u32 timing;
+ u32 rsvd0[3];
+ u32 data;
+ u32 rsvd1[3];
+ u32 read_ctr;
+ u32 rsvd2[3];
+ u32 read_fuse_data;
+ u32 rsvd3[7];
+ u32 scs;
+ u32 scs_set;
+ u32 scs_clr;
+ u32 scs_tog;
+ u32 crc_addr;
+ u32 rsvd4[3];
+ u32 crc_value;
+ u32 rsvd5[3];
+ u32 version;
+ u32 rsvd6[0xdb];
+
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ } bank[16];
+};
+
+/* OTP Bank 4 */
+struct fuse_bank4_regs {
+ u32 sjc_resp0;
+ u32 rsvd0[3];
+ u32 sjc_resp1;
+ u32 rsvd1[3];
+ u32 mac_addr0;
+ u32 rsvd2[3];
+ u32 mac_addr1;
+ u32 rsvd3[3];
+ u32 mac_addr2;
+ u32 rsvd4[3];
+ u32 mac_addr3;
+ u32 rsvd5[3];
+ u32 gp1;
+ u32 rsvd6[3];
+ u32 gp2;
+ u32 rsvd7[3];
+};
+
+#endif /* __ASSEMBLER__*/
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mvf600/mvf_pins.h b/arch/arm/include/asm/arch-mvf600/mvf_pins.h
new file mode 100644
index 0000000..0fd89af
--- /dev/null
+++ b/arch/arm/include/asm/arch-mvf600/mvf_pins.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MVF_PINS_H__
+#define __ASM_ARCH_MVF_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+enum {
+ MVF600_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, 0x0000, 0, 0),
+ MVF600_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, 0),
+ MVF600_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006C, 0x006C, 2, 0x037C, 0, 0),
+ MVF600_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00B8, 0x00B8, 1, 0x0000, 0, 0),
+ MVF600_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00B4, 0x00B4, 1, 0x0000, 0, 0),
+ MVF600_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00BC, 0x00BC, 1, 0x0000, 0, 0),
+ MVF600_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00C0, 0x00C0, 1, 0x0000, 0, 0),
+ MVF600_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00C4, 0x00C4, 1, 0x0000, 0, 0),
+ MVF600_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00C8, 0x00C8, 1, 0x0000, 0, 0),
+ MVF600_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00CC, 0x00CC, 1, 0x0000, 0, 0),
+ MVF600_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, 0x0000, 0, 0),
+ MVF600_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, 0x0000, 0, 0),
+ MVF600_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, 0x0000, 0, 0),
+ MVF600_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003C, 0x003C, 5, 0x0000, 0, 0),
+ MVF600_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, 0x0000, 0, 0),
+ MVF600_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, 0x0000, 0, 0),
+ MVF600_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, 0x0000, 0, 0),
+ MVF600_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004C, 0x004C, 5, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, 0x0000, 0, 0),
+ MVF600_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, 0x0000, 0, 0),
+};
+
+#endif /* __ASM_ARCH_MVF_PINS_H__ */
--
1.8.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 2/6] arm: mvf600: Add IOMUX support for Vybrid MVF600
2013-05-14 9:51 [U-Boot] [PATCH v2 0/6] arm: mvf600: Add Freescale Vybrid MVF600 CPU and MVF600TWR board support Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support Alison Wang
@ 2013-05-14 9:51 ` Alison Wang
2013-05-15 8:16 ` Stefano Babic
2013-05-14 9:51 ` [U-Boot] [PATCH v2 3/6] arm: mvf600: Add FEC " Alison Wang
` (3 subsequent siblings)
5 siblings, 1 reply; 25+ messages in thread
From: Alison Wang @ 2013-05-14 9:51 UTC (permalink / raw)
To: u-boot
This patch adds the IOMUX support for Vybrid MVF600 platform.
There is a little difference for IOMUXC module between MVF600 and i.MX
platform, the muxmode and pad configuration share one 32bit register on
MVF600, but they are two independent registers on I.MX platform. A
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
Changes in v2:
- Use common iomux-v3 code
arch/arm/imx-common/Makefile | 2 +-
arch/arm/imx-common/iomux-v3.c | 6 ++++++
arch/arm/include/asm/imx-common/iomux-v3.h | 18 ++++++++++++++++++
3 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 8bba8a5..3378931 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libimx-common.o
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mvf600))
COBJS-y = iomux-v3.o
endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 7fe5ce7..35880c7 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
if (sel_input_ofs)
__raw_writel(sel_input, base + sel_input_ofs);
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+ if (!(pad_ctrl & NO_PAD_CTRL))
+ __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
+ base + pad_ctrl_ofs);
+#else
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+#endif
}
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index 0b4e763..7005fde 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -121,6 +121,24 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
+#elif defined(CONFIG_MVF600)
+
+#define PAD_MUX_MODE_SHIFT 20
+
+#define PAD_CTL_PUS_47K_UP (1 << 4)
+#define PAD_CTL_PUS_100K_UP (2 << 4)
+#define PAD_CTL_PUE (1 << 2)
+#define PAD_CTL_PKE (1 << 3)
+
+#define PAD_CTL_SPEED_HIGH (3 << 12)
+#define PAD_CTL_SPEED_MED (1 << 12)
+
+#define PAD_CTL_DSE_20ohm (7 << 6)
+#define PAD_CTL_DSE_25ohm (6 << 6)
+#define PAD_CTL_DSE_50ohm (3 << 6)
+
+#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
+
#else
#define PAD_CTL_DVS (1 << 13)
--
1.8.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 3/6] arm: mvf600: Add FEC support for Vybrid MVF600
2013-05-14 9:51 [U-Boot] [PATCH v2 0/6] arm: mvf600: Add Freescale Vybrid MVF600 CPU and MVF600TWR board support Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 2/6] arm: mvf600: Add IOMUX support for Vybrid MVF600 Alison Wang
@ 2013-05-14 9:51 ` Alison Wang
2013-05-15 8:15 ` Stefano Babic
2013-05-14 9:51 ` [U-Boot] [PATCH v2 4/6] arm: mvf600: Add watchdog " Alison Wang
` (2 subsequent siblings)
5 siblings, 1 reply; 25+ messages in thread
From: Alison Wang @ 2013-05-14 9:51 UTC (permalink / raw)
To: u-boot
This patch adds FEC support for Vybrid MVF600 platform.
Add code to use RMII for MVF600.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
Changes in v2:
- Use common FEC driver fec_mxc.c
drivers/net/fec_mxc.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4dbcdca..21e58f4 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -518,7 +518,11 @@ static int fec_open(struct eth_device *edev)
u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
u32 rcr = (readl(&fec->eth->r_cntrl) &
~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
- FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
+ FEC_RCNTRL_MII_MODE;
+ if (fec->xcv_type == RGMII)
+ rcr |= FEC_RCNTRL_RGMII;
+ else if (fec->xcv_type == RMII)
+ rcr |= FEC_RCNTRL_RMII;
if (speed == _1000BASET)
ecr |= FEC_ECNTRL_SPEED;
else if (speed != _100BASET)
--
1.8.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 4/6] arm: mvf600: Add watchdog support for Vybrid MVF600
2013-05-14 9:51 [U-Boot] [PATCH v2 0/6] arm: mvf600: Add Freescale Vybrid MVF600 CPU and MVF600TWR board support Alison Wang
` (2 preceding siblings ...)
2013-05-14 9:51 ` [U-Boot] [PATCH v2 3/6] arm: mvf600: Add FEC " Alison Wang
@ 2013-05-14 9:51 ` Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 5/6] arm: mvf600: Add uart " Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board Alison Wang
5 siblings, 0 replies; 25+ messages in thread
From: Alison Wang @ 2013-05-14 9:51 UTC (permalink / raw)
To: u-boot
This patch adds watchdog support for Vybrid MVF600 platform.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
Changes in v2:
- Add watchdog support
- Use reset_cpu() in imx_watchdog.c
drivers/watchdog/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 13e7c37..40946df 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -27,7 +27,7 @@ LIB := $(obj)libwatchdog.o
COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
-ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6))
+ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mvf600))
COBJS-y += imx_watchdog.o
endif
COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
--
1.8.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 5/6] arm: mvf600: Add uart support for Vybrid MVF600
2013-05-14 9:51 [U-Boot] [PATCH v2 0/6] arm: mvf600: Add Freescale Vybrid MVF600 CPU and MVF600TWR board support Alison Wang
` (3 preceding siblings ...)
2013-05-14 9:51 ` [U-Boot] [PATCH v2 4/6] arm: mvf600: Add watchdog " Alison Wang
@ 2013-05-14 9:51 ` Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board Alison Wang
5 siblings, 0 replies; 25+ messages in thread
From: Alison Wang @ 2013-05-14 9:51 UTC (permalink / raw)
To: u-boot
This patch adds lpuart support for Vybrid MVF600 platform.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
---
Changes in v2:
- Define C structures and access C structures to set/read registers
- Change the names to reuse this driver on other platforms
drivers/serial/Makefile | 1 +
drivers/serial/serial_lpuart.c | 161 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 162 insertions(+)
create mode 100644 drivers/serial/serial_lpuart.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index fbc4e97..bb6559b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -52,6 +52,7 @@ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
new file mode 100644
index 0000000..6ae7f77
--- /dev/null
+++ b/drivers/serial/serial_lpuart.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#define UART_BASE UART1_BASE
+
+struct lpuart_fsl {
+ u8 ubdh;
+ u8 ubdl;
+ u8 uc1;
+ u8 uc2;
+ u8 us1;
+ u8 us2;
+ u8 uc3;
+ u8 ud;
+ u8 uma1;
+ u8 uma2;
+ u8 uc4;
+ u8 uc5;
+ u8 ued;
+ u8 umodem;
+ u8 uir;
+ u8 reserved;
+ u8 upfifo;
+ u8 ucfifo;
+ u8 usfifo;
+ u8 utwfifo;
+ u8 utcfifo;
+ u8 urwfifo;
+ u8 urcfifo;
+ u8 rsvd[28];
+};
+
+#define US1_TDRE (1 << 7)
+#define US1_RDRF (1 << 5)
+#define UC2_TE (1 << 3)
+#define UC2_RE (1 << 2)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct lpuart_fsl *base = (struct lpuart_fsl *)UART_BASE;
+
+static void lpuart_serial_setbrg(void)
+{
+ u32 clk = mvf_get_clock(MVF_UART_CLK);
+ u16 sbr;
+
+ if (!gd->baudrate)
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ sbr = (u16)(clk / (16 * gd->baudrate));
+ /* place adjustment later - n/32 BRFA */
+
+ __raw_writeb(sbr >> 8, &base->ubdh);
+ __raw_writeb(sbr & 0xff, &base->ubdl);
+}
+
+static int lpuart_serial_getc(void)
+{
+ u8 status;
+
+ while (!(__raw_readb(&base->us1) & US1_RDRF))
+ WATCHDOG_RESET();
+
+ status = __raw_readb(&base->us1);
+ status |= US1_RDRF;
+ __raw_writeb(status, &base->us1);
+
+ return __raw_readb(&base->ud);
+}
+
+static void lpuart_serial_putc(const char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(__raw_readb(&base->us1) & US1_TDRE))
+ WATCHDOG_RESET();
+
+ __raw_writeb(c, &base->ud);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart_serial_tstc(void)
+{
+ if (__raw_readb(&base->urcfifo) == 0)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart_serial_init(void)
+{
+ u8 ctrl;
+
+ ctrl = __raw_readb(&base->uc2);
+ ctrl &= ~UC2_RE;
+ ctrl &= ~UC2_TE;
+ __raw_writeb(ctrl, &base->uc2);
+
+ __raw_writeb(0, &base->umodem);
+ __raw_writeb(0, &base->uc1);
+
+ /* provide data bits, parity, stop bit, etc */
+
+ serial_setbrg();
+
+ __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
+
+ return 0;
+}
+
+static struct serial_device lpuart_serial_drv = {
+ .name = "lpuart_serial",
+ .start = lpuart_serial_init,
+ .stop = NULL,
+ .setbrg = lpuart_serial_setbrg,
+ .putc = lpuart_serial_putc,
+ .puts = default_serial_puts,
+ .getc = lpuart_serial_getc,
+ .tstc = lpuart_serial_tstc,
+};
+
+void lpuart_serial_initialize(void)
+{
+ serial_register(&lpuart_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &lpuart_serial_drv;
+}
--
1.8.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board
2013-05-14 9:51 [U-Boot] [PATCH v2 0/6] arm: mvf600: Add Freescale Vybrid MVF600 CPU and MVF600TWR board support Alison Wang
` (4 preceding siblings ...)
2013-05-14 9:51 ` [U-Boot] [PATCH v2 5/6] arm: mvf600: Add uart " Alison Wang
@ 2013-05-14 9:51 ` Alison Wang
2013-05-15 4:14 ` Shawn Guo
2013-05-15 9:01 ` Stefano Babic
5 siblings, 2 replies; 25+ messages in thread
From: Alison Wang @ 2013-05-14 9:51 UTC (permalink / raw)
To: u-boot
MVF600TWR is a board based on Vybrid MVF600 SoC.
This patch adds basic support for Vybrid MVF600TWR board.
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
---
Changes in v2:
- Add an entry to MAINTAINERS file
- Rename directory name 'vybird' to 'mvf600twr'
- Use standard method to set gd->ram_size
- Rewrite board_mmc_getcd() function
- Remove useless undef
- Remove hardcoded IP addresses and MAC addresses
- Remove useless CONFIG_SYS_ defines
- Define C structures and access C structures to set/read registers
- Move CONFIG_MACH_TYPE to board configuration file
- Use common iomux-v3 code
MAINTAINERS | 4 +
board/freescale/mvf600twr/Makefile | 39 ++++
board/freescale/mvf600twr/imximage.cfg | 35 +++
board/freescale/mvf600twr/mvf600twr.c | 403 +++++++++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/mvf600twr.h | 147 ++++++++++++
6 files changed, 629 insertions(+)
create mode 100644 board/freescale/mvf600twr/Makefile
create mode 100644 board/freescale/mvf600twr/imximage.cfg
create mode 100644 board/freescale/mvf600twr/mvf600twr.c
create mode 100644 include/configs/mvf600twr.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c05433a..d32ac66 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1057,6 +1057,10 @@ Eric Nelson <eric.nelson@boundarydevices.com>
nitrogen6s i.MX6S 512MB
nitrogen6s1g i.MX6S 1GB
+Alison Wang <b18965@freescale.com>
+
+ mvf600twr MVF600
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
diff --git a/board/freescale/mvf600twr/Makefile b/board/freescale/mvf600twr/Makefile
new file mode 100644
index 0000000..7416228
--- /dev/null
+++ b/board/freescale/mvf600twr/Makefile
@@ -0,0 +1,39 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mvf600twr/imximage.cfg b/board/freescale/mvf600twr/imximage.cfg
new file mode 100644
index 0000000..33ead0f
--- /dev/null
+++ b/board/freescale/mvf600twr/imximage.cfg
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
diff --git a/board/freescale/mvf600twr/mvf600twr.c b/board/freescale/mvf600twr/mvf600twr.c
new file mode 100644
index 0000000..500ceb8
--- /dev/null
+++ b/board/freescale/mvf600twr/mvf600twr.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mvf_pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ESDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | \
+ PAD_CTL_OBE_IBE_ENABLE)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define DDR_PAD_CTRL PAD_CTL_DSE_25ohm
+
+#define PHY_DQ_TIMING 0x00002613
+#define PHY_DQS_TIMING 0x00002615
+#define PHY_CTRL 0x01210080
+#define PHY_MASTER_CTRL 0x0001012a
+#define PHY_SLAVE_CTRL 0x00012020
+
+iomux_v3_cfg_t const ddr_pads[] = {
+ MVF600_PAD_DDR_A15__DDR_A_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A14__DDR_A_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A13__DDR_A_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A12__DDR_A_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A11__DDR_A_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A10__DDR_A_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A9__DDR_A_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A8__DDR_A_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A7__DDR_A_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A6__DDR_A_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A5__DDR_A_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A4__DDR_A_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A3__DDR_A_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A2__DDR_A_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_A1__DDR_A_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_BA2__DDR_BA_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_BA1__DDR_BA_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_BA0__DDR_BA_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_CAS__DDR_CAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_CKE__DDR_CKE_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_CLK__DDR_CLK_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_CS__DDR_CS_B_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D15__DDR_D_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D14__DDR_D_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D13__DDR_D_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D12__DDR_D_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D11__DDR_D_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D10__DDR_D_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D9__DDR_D_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D8__DDR_D_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D7__DDR_D_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D6__DDR_D_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D5__DDR_D_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D4__DDR_D_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D3__DDR_D_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D2__DDR_D_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D1__DDR_D_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_D0__DDR_D_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_DQM1__DDR_DQM_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_DQM0__DDR_DQM_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_DQS1__DDR_DQS_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_DQS0__DDR_DQS_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_RAS__DDR_RAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_WE__DDR_WE_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_ODT1__DDR_ODT_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+ MVF600_PAD_DDR_ODT0__DDR_ODT_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart1_pads[] = {
+ MVF600_PAD_PTB4__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MVF600_PAD_PTB5__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet0_pads[] = {
+ MVF600_PAD_PTA6__RMII0_CLKIN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MVF600_PAD_PTC1__RMII0_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MVF600_PAD_PTC0__RMII0_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MVF600_PAD_PTC2__RMII0_CRS_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MVF600_PAD_PTC3__RMII0_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MVF600_PAD_PTC4__RMII0_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MVF600_PAD_PTC5__RMII0_RXER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MVF600_PAD_PTC6__RMII0_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MVF600_PAD_PTC7__RMII0_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MVF600_PAD_PTC8__RMII0_TXEN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const esdhc1_pads[] = {
+ MVF600_PAD_PTA24__ESDHC1_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+ MVF600_PAD_PTA25__ESDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+ MVF600_PAD_PTA26__ESDHC1_DAT0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+ MVF600_PAD_PTA27__ESDHC1_DAT1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+ MVF600_PAD_PTA28__ESDHC1_DAT2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+ MVF600_PAD_PTA29__ESDHC1_DAT3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+void setup_iomux_ddr(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddr_phy_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[0]);
+ __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[16]);
+ __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[32]);
+ __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[48]);
+
+ __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[1]);
+ __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[17]);
+ __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[33]);
+ __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[49]);
+
+ __raw_writel(PHY_CTRL, &ddrmr->phy[2]);
+ __raw_writel(PHY_CTRL, &ddrmr->phy[18]);
+ __raw_writel(PHY_CTRL, &ddrmr->phy[34]);
+ __raw_writel(PHY_CTRL, &ddrmr->phy[50]);
+
+ __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[3]);
+ __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[19]);
+ __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[35]);
+ __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[51]);
+
+ __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[4]);
+ __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[20]);
+ __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+ __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[52]);
+
+ __raw_writel(0x00001105, &ddrmr->phy[50]);
+}
+
+void ddr_ctrl_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ __raw_writel(0x00000600, &ddrmr->cr[0]); /* LPDDR2 or DDR3 */
+ __raw_writel(0x00000020, &ddrmr->cr[2]); /* TINIT */
+ __raw_writel(0x0000007c, &ddrmr->cr[10]);
+
+ __raw_writel(0x00013880, &ddrmr->cr[11]);
+ __raw_writel(0x0000050c, &ddrmr->cr[12]);
+ __raw_writel(0x15040404, &ddrmr->cr[13]);
+ __raw_writel(0x1406040F, &ddrmr->cr[14]);
+ __raw_writel(0x04040000, &ddrmr->cr[16]);
+ __raw_writel(0x006DB00C, &ddrmr->cr[17]);
+ __raw_writel(0x00000403, &ddrmr->cr[18]);
+
+ __raw_writel(0x01000000, &ddrmr->cr[20]);
+ __raw_writel(0x06060101, &ddrmr->cr[21]);
+
+ __raw_writel(0x000B0000, &ddrmr->cr[22]);
+ __raw_writel(0x03000200, &ddrmr->cr[23]);
+ __raw_writel(0x00000006, &ddrmr->cr[24]);
+
+ __raw_writel(0x00010000, &ddrmr->cr[25]);
+ __raw_writel(0x0C28002C, &ddrmr->cr[26]);
+ __raw_writel(0x00000005, &ddrmr->cr[28]);
+ __raw_writel(0x00000003, &ddrmr->cr[29]);
+
+ __raw_writel(0x0000000A, &ddrmr->cr[30]);
+ __raw_writel(0x00440200, &ddrmr->cr[31]);
+ __raw_writel(0x00010000, &ddrmr->cr[33]);
+ __raw_writel(0x00050500, &ddrmr->cr[34]);
+
+ /* Frequency change */
+ __raw_writel(0x00000100, &ddrmr->cr[38]);
+ __raw_writel(0x04001002, &ddrmr->cr[39]);
+
+ __raw_writel(0x00000001, &ddrmr->cr[41]);
+ __raw_writel(0x00000000, &ddrmr->cr[45]);
+ __raw_writel(0x00000000, &ddrmr->cr[46]);
+ __raw_writel(0x00000000, &ddrmr->cr[47]);
+
+ /* DRAM device Mode registers */
+ __raw_writel(0x00460420, &ddrmr->cr[48]);
+ __raw_writel(0x00000000, &ddrmr->cr[49]);
+ __raw_writel(0x00000000, &ddrmr->cr[51]);
+ __raw_writel(0x00000000, &ddrmr->cr[57]);
+
+ /* ZQ stuff */
+ __raw_writel(0x01000200, &ddrmr->cr[66]);
+ __raw_writel(0x02000040, &ddrmr->cr[67]);
+ __raw_writel(0x00000200, &ddrmr->cr[69]);
+
+ __raw_writel(0x00000040, &ddrmr->cr[70]);
+ __raw_writel(0x00000000, &ddrmr->cr[71]);
+ __raw_writel(0x01000000, &ddrmr->cr[72]);
+
+ /* DRAM controller misc */
+ __raw_writel(0x0a010300, &ddrmr->cr[73]);
+ __raw_writel(0x0101ffff, &ddrmr->cr[74]);
+ __raw_writel(0x01010101, &ddrmr->cr[75]);
+ __raw_writel(0x03030101, &ddrmr->cr[76]);
+ __raw_writel(0x01000101, &ddrmr->cr[77]);
+ __raw_writel(0x0000000C, &ddrmr->cr[78]);
+ __raw_writel(0x01000000, &ddrmr->cr[79]);
+
+ /* Disable interrupts */
+ __raw_writel(0x1FFFFFFF, &ddrmr->cr[82]);
+
+ /* ODT */
+ __raw_writel(0x01010000, &ddrmr->cr[87]);
+ __raw_writel(0x00040000, &ddrmr->cr[88]);
+ __raw_writel(0x00000002, &ddrmr->cr[89]);
+
+ __raw_writel(0x00020000, &ddrmr->cr[91]);
+ __raw_writel(0x00000000, &ddrmr->cr[92]);
+
+ __raw_writel(0x00002819, &ddrmr->cr[96]);
+
+ /* AXI ports */
+ __raw_writel(0x00202000, &ddrmr->cr[105]);
+ __raw_writel(0x20200000, &ddrmr->cr[106]);
+ __raw_writel(0x00002020, &ddrmr->cr[110]);
+ __raw_writel(0x00202000, &ddrmr->cr[114]);
+ __raw_writel(0x20200000, &ddrmr->cr[115]);
+
+ __raw_writel(0x00000101, &ddrmr->cr[117]);
+ __raw_writel(0x01010000, &ddrmr->cr[118]);
+ __raw_writel(0x00000000, &ddrmr->cr[119]);
+
+ __raw_writel(0x02020000, &ddrmr->cr[120]);
+ __raw_writel(0x00000202, &ddrmr->cr[121]);
+ __raw_writel(0x01010064, &ddrmr->cr[122]);
+ __raw_writel(0x00000101, &ddrmr->cr[123]);
+ __raw_writel(0x00000064, &ddrmr->cr[124]);
+
+ /* TDFI */
+ __raw_writel(0x00000000, &ddrmr->cr[125]);
+ __raw_writel(0x00000B00, &ddrmr->cr[126]);
+ __raw_writel(0x00000000, &ddrmr->cr[127]);
+
+ __raw_writel(0x00000000, &ddrmr->cr[131]);
+ __raw_writel(0x00000506, &ddrmr->cr[132]);
+ __raw_writel(0x02000000, &ddrmr->cr[137]);
+ __raw_writel(0x04070303, &ddrmr->cr[139]);
+
+ __raw_writel(0x00000000, &ddrmr->cr[136]);
+
+ __raw_writel(0x68200000, &ddrmr->cr[154]);
+ __raw_writel(0x00000202, &ddrmr->cr[155]);
+ __raw_writel(0x00000006, &ddrmr->cr[158]);
+ __raw_writel(0x00000006, &ddrmr->cr[159]);
+
+ ddr_phy_init();
+
+ __raw_writel(0x00000601, &ddrmr->cr[0]);
+
+ udelay(200);
+}
+
+int dram_init(void)
+{
+ setup_iomux_ddr();
+
+ ddr_ctrl_init();
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* eSDHC1 is always present */
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ s32 status = 0;
+
+ esdhc_cfg[0].sdhc_clk = mvf_get_clock(MVF_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(
+ esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+ status |= fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+
+ return status;
+}
+#endif
+
+static void clock_init(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+
+ __raw_writel(0x00000078, &ccm->clpcr);
+ __raw_writel(0x000fc000, &ccm->ccgr0);
+ __raw_writel(0xf00fc0c0, &ccm->ccgr1);
+ __raw_writel(0x0fff0303, &ccm->ccgr2);
+ __raw_writel(0x00000033, &ccm->ccgr3);
+ __raw_writel(0x33f0f003, &ccm->ccgr4);
+ __raw_writel(0x3003cc00, &ccm->ccgr6);
+ __raw_writel(0x0000033c, &ccm->ccgr7);
+ __raw_writel(0x0000000f, &ccm->ccgr9);
+
+ __raw_writel(0x00002001, &anadig->pll2_ctrl);
+ __raw_writel(0x00011001, &anadig->pll5_ctrl);
+ __raw_writel(0x00002001, &anadig->pll1_ctrl);
+
+ __raw_writel(0x00010005, &ccm->ccr);
+ __raw_writel(0x0003ff64, &ccm->ccsr);
+ __raw_writel(0x00000810, &ccm->cacrr);
+ __raw_writel(0x03cf0000, &ccm->cscmr1);
+ __raw_writel(0x01000000, &ccm->cscdr1);
+ __raw_writel(0x30004240, &ccm->cscdr2);
+ __raw_writel(0x00003f1f, &ccm->cscdr3);
+ __raw_writel(0, &ccm->cscmr2);
+ __raw_writel(0, &ccm->cscdr4);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ setup_iomux_enet();
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("FEC MXC: %s:failed\n", __func__);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ clock_init();
+
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: mvf600twr\n");
+
+ return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 2f39f26..60c1920 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -262,6 +262,7 @@ mx6qsabrelite arm armv7 mx6qsabrelite freesca
mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
titanium arm armv7 titanium freescale mx6 titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg
+mvf600twr arm armv7 mvf600twr freescale mvf600 mvf600twr:IMX_CONFIG=board/freescale/mvf600twr/imximage.cfg
eco5pk arm armv7 eco5pk 8dtech omap3
nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048
diff --git a/include/configs/mvf600twr.h b/include/configs/mvf600twr.h
new file mode 100644
index 0000000..bb1f3ef
--- /dev/null
+++ b/include/configs/mvf600twr.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale Vybrid mvf600twr board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_MVF600
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_VYBRID_VF6XX 4146
+#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_FSL_LPUART
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_UART_PORT (1)
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC
+#undef CONFIG_CMD_IMLS
+
+/* MUX mode and PAD ctrl are in one register */
+#define CONFIG_IOMUX_SHARE_CONF_REG
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_SYS_TEXT_BASE 0x3f010000
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "Vybrid U-Boot > "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x80010000
+#define CONFIG_SYS_MEMTEST_END 0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR 0x80010000
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_PRAM 2048
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/* Physical memory map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM (0x80000000)
+#define PHYS_SDRAM_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
--
1.8.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board
2013-05-14 9:51 ` [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board Alison Wang
@ 2013-05-15 4:14 ` Shawn Guo
2013-05-15 8:11 ` Wang Huan-B18965
2013-05-15 9:01 ` Stefano Babic
1 sibling, 1 reply; 25+ messages in thread
From: Shawn Guo @ 2013-05-15 4:14 UTC (permalink / raw)
To: u-boot
On Tue, May 14, 2013 at 05:51:48PM +0800, Alison Wang wrote:
> diff --git a/include/configs/mvf600twr.h b/include/configs/mvf600twr.h
> new file mode 100644
> index 0000000..bb1f3ef
> --- /dev/null
> +++ b/include/configs/mvf600twr.h
To make it friendly to the mainline kernel, I would suggest we enable
the following two options.
CONFIG_OF_LIBFDT
CONFIG_CMD_BOOTZ
Shawn
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board
2013-05-15 4:14 ` Shawn Guo
@ 2013-05-15 8:11 ` Wang Huan-B18965
0 siblings, 0 replies; 25+ messages in thread
From: Wang Huan-B18965 @ 2013-05-15 8:11 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Shawn Guo [mailto:shawn.guo at linaro.org]
> Sent: Wednesday, May 15, 2013 12:15 PM
> To: Wang Huan-B18965
> Cc: sbabic at denx.de; u-boot at lists.denx.de; TsiChung Liew; Jin Zhengxiong-
> R64188; Estevam Fabio-R49496
> Subject: Re: [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for
> Vybrid MVF600TWR board
>
> On Tue, May 14, 2013 at 05:51:48PM +0800, Alison Wang wrote:
> > diff --git a/include/configs/mvf600twr.h b/include/configs/mvf600twr.h
> > new file mode 100644 index 0000000..bb1f3ef
> > --- /dev/null
> > +++ b/include/configs/mvf600twr.h
>
> To make it friendly to the mainline kernel, I would suggest we enable
> the following two options.
>
> CONFIG_OF_LIBFDT
> CONFIG_CMD_BOOTZ
>
[Alison Wang] Yes, I will enable them. Thanks.
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support
2013-05-14 9:51 ` [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support Alison Wang
@ 2013-05-15 8:13 ` Stefano Babic
2013-05-15 12:09 ` Albert ARIBAUD
2013-05-16 4:00 ` [U-Boot] " Wang Huan-B18965
0 siblings, 2 replies; 25+ messages in thread
From: Stefano Babic @ 2013-05-15 8:13 UTC (permalink / raw)
To: u-boot
On 14/05/2013 11:51, Alison Wang wrote:
> This patch adds generic codes to support Freescale's Vybrid MVF600 CPU.
>
> It aligns Vybrid MVF600 platform with i.MX platform. As there are
> some differences between MVF600 and i.MX platforms, the specific
> codes are in the arch/arm/cpu/armv7/mvf600 directory.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
Hi Alison,
> Changes in v2:
> - Remove vybrid-common directory
> - Rename directory name 'vybrid' to 'mvf600'
> - Add generic.c file
> - Rewrite get_reset_cause() to make it readable
> - Remove reset_cpu(), and use the function in imx_watchdog.c
> - Rewrite timer.c file
> - Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk()
> - Remove lowlevel_init.S, and add clock_init() in board_early_init_f()
> - Remove useless CONFIG_SYS_ defines
> - Move CONFIG_MACH_TYPE to board configuration file
> - Define C structures and access C structures to set/read registers
> - Remove useless errata
> - Remove useless macros
> - Rename directory 'arch-vybrid' to 'arch-mvf600'
>
> Makefile | 2 +-
> arch/arm/cpu/armv7/mvf600/Makefile | 42 ++++
> arch/arm/cpu/armv7/mvf600/generic.c | 309 ++++++++++++++++++++++++++++
Just a minor concern here. The SOC is a ARMv5, but files go into the
armv7 directory. Maybe the bigger issue can be with the increasing
number of work-around (CONFIG_ERRATA) that flow into start.S for armv7,
that are specific only for armv7. I know that for ARMv5 we split
differently instead of ARM architecture (ARM926,...).
Albert, what do you think about ? Should these files be moved away from
armv7 ?
> +unsigned int mvf_get_clock(enum mvf_clock clk)
> +{
> + switch (clk) {
> + case MVF_ARM_CLK:
> + return get_mcu_main_clk();
> + case MVF_BUS_CLK:
> + return get_bus_clk();
> + case MVF_IPG_CLK:
> + return get_ipg_clk();
> + case MVF_UART_CLK:
> + return get_uart_clk();
> + case MVF_ESDHC_CLK:
> + return get_sdhc_clk();
> + case MVF_FEC_CLK:
> + return get_fec_clk();
> + default:
> + break;
> + }
> + return -1;
> +}
Ok - we have the same structure as for i.MX. I agree with you that the
name of the function mxc_get_clock() is not anymore correct, after some
other Freescale's SOC families were introduced. However, it is still
important to have a common API to expone a SOC to a board maintainer.
If you see, the mxs family (MX23 / MX28) has a mxc_get_clock(), even if
most internal functions are marked as mxs_. I think we can later change
the name for this function (maybe this is not the only one) to make the
name clearer and not specific to i.MX, but then it is will be easier if
all SOCs use the same names. For this reason, it is better to rename
this function to mxc_get_clock() and please take the same enums that are
already set for the other Freescale's SOCs.
> +
> +#ifdef CONFIG_FEC_MXC
> +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
> +{
> + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
> + struct fuse_bank *bank = &ocotp->bank[4];
> + struct fuse_bank4_regs *fuse =
> + (struct fuse_bank4_regs *)bank->fuse_regs;
> +
> + u32 value = readl(&fuse->mac_addr0);
> + mac[0] = (value >> 8);
> + mac[1] = value;
To my knowledge : is the whole MAC stored in the ocotp ? No need to add
the first bytes (vendor-id) as we had for MX28 ?
> diff --git a/arch/arm/cpu/armv7/mvf600/timer.c b/arch/arm/cpu/armv7/mvf600/timer.c
> new file mode 100644
> index 0000000..99ca57d
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/mvf600/timer.c
> @@ -0,0 +1,144 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <div64.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/clock.h>
> +
> +/* Periodic interrupt timer registers */
> +struct pit_reg {
> + u32 mcr;
> + u32 recv0[55];
> + u32 ltmr64h;
> + u32 ltmr64l;
> + u32 recv1[6];
> + u32 ldval0;
> + u32 cval0;
> + u32 tctrl0;
> + u32 tflg0;
> + u32 ldval1;
> + u32 cval1;
> + u32 tctrl1;
> + u32 tflg1;
> + u32 ldval2;
> + u32 cval2;
> + u32 tctrl2;
> + u32 tflg2;
> + u32 ldval3;
> + u32 cval3;
> + u32 tctrl3;
> + u32 tflg3;
> + u32 ldval4;
> + u32 cval4;
> + u32 tctrl4;
> + u32 tflg4;
> + u32 ldval5;
> + u32 cval5;
> + u32 tctrl5;
> + u32 tflg5;
> + u32 ldval6;
> + u32 cval6;
> + u32 tctrl6;
> + u32 tflg6;
> + u32 ldval7;
> + u32 cval7;
> + u32 tctrl7;
> + u32 tflg7;
> +};
> +
I had put these structure in imx-regs.h - no block from my side, but
there is also no big reason to let it here.
> diff --git a/arch/arm/include/asm/arch-mvf600/clock.h b/arch/arm/include/asm/arch-mvf600/clock.h
> new file mode 100644
> index 0000000..889d4d9
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mvf600/clock.h
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __ASM_ARCH_CLOCK_H
> +#define __ASM_ARCH_CLOCK_H
> +
> +#include <common.h>
> +
> +enum mvf_clock {
> + MVF_ARM_CLK = 0,
> + MVF_BUS_CLK,
> + MVF_IPG_CLK,
> + MVF_UART_CLK,
> + MVF_ESDHC_CLK,
> + MVF_FEC_CLK,
> +};
> +
> +unsigned int mvf_get_clock(enum mvf_clock clk);
> +
> +#define imx_get_fecclk() mvf_get_clock(MVF_FEC_CLK)
See my previous comment. Agree the names are not anymore correct, but we
can fix them later with a separate patch for all Freescale's SOCs.
> +/* On-Chip One Time Programmable Controller (OCOTP) */
> +struct ocotp_regs {
> + u32 ctrl;
> + u32 ctrl_set;
> + u32 ctrl_clr;
> + u32 ctrl_tog;
> + u32 timing;
> + u32 rsvd0[3];
> + u32 data;
> + u32 rsvd1[3];
> + u32 read_ctr;
> + u32 rsvd2[3];
> + u32 read_fuse_data;
> + u32 rsvd3[7];
> + u32 scs;
> + u32 scs_set;
> + u32 scs_clr;
> + u32 scs_tog;
> + u32 crc_addr;
> + u32 rsvd4[3];
> + u32 crc_value;
> + u32 rsvd5[3];
> + u32 version;
> + u32 rsvd6[0xdb];
> +
> + struct fuse_bank {
> + u32 fuse_regs[0x20];
> + } bank[16];
> +};
> +
> +/* OTP Bank 4 */
> +struct fuse_bank4_regs {
> + u32 sjc_resp0;
> + u32 rsvd0[3];
> + u32 sjc_resp1;
> + u32 rsvd1[3];
> + u32 mac_addr0;
> + u32 rsvd2[3];
> + u32 mac_addr1;
> + u32 rsvd3[3];
> + u32 mac_addr2;
> + u32 rsvd4[3];
> + u32 mac_addr3;
> + u32 rsvd5[3];
> + u32 gp1;
> + u32 rsvd6[3];
> + u32 gp2;
> + u32 rsvd7[3];
> +};
> +
Have you seen that a driver for fuse / ocotp was recently added to
mainline ? Have you tested on your platform ?
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 3/6] arm: mvf600: Add FEC support for Vybrid MVF600
2013-05-14 9:51 ` [U-Boot] [PATCH v2 3/6] arm: mvf600: Add FEC " Alison Wang
@ 2013-05-15 8:15 ` Stefano Babic
2013-05-15 14:19 ` Benoît Thébaudeau
0 siblings, 1 reply; 25+ messages in thread
From: Stefano Babic @ 2013-05-15 8:15 UTC (permalink / raw)
To: u-boot
On 14/05/2013 11:51, Alison Wang wrote:
> This patch adds FEC support for Vybrid MVF600 platform.
> Add code to use RMII for MVF600.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
> Changes in v2:
> - Use common FEC driver fec_mxc.c
>
> drivers/net/fec_mxc.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 4dbcdca..21e58f4 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -518,7 +518,11 @@ static int fec_open(struct eth_device *edev)
> u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
> u32 rcr = (readl(&fec->eth->r_cntrl) &
> ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
> - FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
> + FEC_RCNTRL_MII_MODE;
> + if (fec->xcv_type == RGMII)
> + rcr |= FEC_RCNTRL_RGMII;
> + else if (fec->xcv_type == RMII)
> + rcr |= FEC_RCNTRL_RMII;
> if (speed == _1000BASET)
> ecr |= FEC_ECNTRL_SPEED;
> else if (speed != _100BASET)
>
This can generally be applied, it is not only related to the new SOC.
Acked-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 2/6] arm: mvf600: Add IOMUX support for Vybrid MVF600
2013-05-14 9:51 ` [U-Boot] [PATCH v2 2/6] arm: mvf600: Add IOMUX support for Vybrid MVF600 Alison Wang
@ 2013-05-15 8:16 ` Stefano Babic
2013-05-15 13:53 ` Benoît Thébaudeau
0 siblings, 1 reply; 25+ messages in thread
From: Stefano Babic @ 2013-05-15 8:16 UTC (permalink / raw)
To: u-boot
On 14/05/2013 11:51, Alison Wang wrote:
> This patch adds the IOMUX support for Vybrid MVF600 platform.
>
> There is a little difference for IOMUXC module between MVF600 and i.MX
> platform, the muxmode and pad configuration share one 32bit register on
> MVF600, but they are two independent registers on I.MX platform. A
> CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
> Changes in v2:
> - Use common iomux-v3 code
>
> arch/arm/imx-common/Makefile | 2 +-
> arch/arm/imx-common/iomux-v3.c | 6 ++++++
> arch/arm/include/asm/imx-common/iomux-v3.h | 18 ++++++++++++++++++
> 3 files changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
> index 8bba8a5..3378931 100644
> --- a/arch/arm/imx-common/Makefile
> +++ b/arch/arm/imx-common/Makefile
> @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
>
> LIB = $(obj)libimx-common.o
>
> -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6))
> +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mvf600))
> COBJS-y = iomux-v3.o
> endif
> ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
> diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
> index 7fe5ce7..35880c7 100644
> --- a/arch/arm/imx-common/iomux-v3.c
> +++ b/arch/arm/imx-common/iomux-v3.c
> @@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
> if (sel_input_ofs)
> __raw_writel(sel_input, base + sel_input_ofs);
>
> +#ifdef CONFIG_IOMUX_SHARE_CONF_REG
> + if (!(pad_ctrl & NO_PAD_CTRL))
> + __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
> + base + pad_ctrl_ofs);
> +#else
> if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
> __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
> +#endif
> }
>
> void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
> diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
> index 0b4e763..7005fde 100644
> --- a/arch/arm/include/asm/imx-common/iomux-v3.h
> +++ b/arch/arm/include/asm/imx-common/iomux-v3.h
> @@ -121,6 +121,24 @@ typedef u64 iomux_v3_cfg_t;
> #define PAD_CTL_DSE_40ohm (6 << 3)
> #define PAD_CTL_DSE_34ohm (7 << 3)
>
> +#elif defined(CONFIG_MVF600)
> +
> +#define PAD_MUX_MODE_SHIFT 20
> +
> +#define PAD_CTL_PUS_47K_UP (1 << 4)
> +#define PAD_CTL_PUS_100K_UP (2 << 4)
> +#define PAD_CTL_PUE (1 << 2)
> +#define PAD_CTL_PKE (1 << 3)
> +
> +#define PAD_CTL_SPEED_HIGH (3 << 12)
> +#define PAD_CTL_SPEED_MED (1 << 12)
> +
> +#define PAD_CTL_DSE_20ohm (7 << 6)
> +#define PAD_CTL_DSE_25ohm (6 << 6)
> +#define PAD_CTL_DSE_50ohm (3 << 6)
> +
> +#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
> +
> #else
>
> #define PAD_CTL_DVS (1 << 13)
>
Acked-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board
2013-05-14 9:51 ` [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board Alison Wang
2013-05-15 4:14 ` Shawn Guo
@ 2013-05-15 9:01 ` Stefano Babic
2013-05-17 15:20 ` Wang Huan-B18965
1 sibling, 1 reply; 25+ messages in thread
From: Stefano Babic @ 2013-05-15 9:01 UTC (permalink / raw)
To: u-boot
On 14/05/2013 11:51, Alison Wang wrote:
> MVF600TWR is a board based on Vybrid MVF600 SoC.
>
> This patch adds basic support for Vybrid MVF600TWR board.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> ---
Hi Alison,
> diff --git a/board/freescale/mvf600twr/imximage.cfg b/board/freescale/mvf600twr/imximage.cfg
> new file mode 100644
> index 0000000..33ead0f
> --- /dev/null
> +++ b/board/freescale/mvf600twr/imximage.cfg
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not write to the Free Software
> + * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> + * MA 02110-1301 USA
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +/* image version */
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi, sd (the board has no nand neither onenand)
> + */
> +BOOT_FROM sd
Ok, verstanden (I hope). This SOC has plenty of internal IRAM. It still
uses the imximage mechanism, but you decided to start from internal RAM
instead of DDR and to set up the RAM controller in the board
initialization function.
We recently discussed about the wrongness of BOOT_FROM command. It makes
no sense, and it was replaced by BOOT_OFFSET. If the SOC uses the main
common offset (0x400), you can put
BOOT_OFFSET FLASH_OFFSET_STANDARD
> +#include <netdev.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
> +
> +#define ESDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | \
> + PAD_CTL_OBE_IBE_ENABLE)
Please see commit 7e2173cf82d0bc235b695460c56d46927febdf36 and adjust
this SOC consequently. PUE requires that PKE is enabled, that means that
setting PKE alone does nothing. Then it is better to define PAD_CTL_PUE
so that PKE is enabled, so in your 2/6 (that I have too fast acked):
PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
and drop PAD_CTL_PKE here. This must fixed globally.
> +#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
> + PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
> +
> +#define DDR_PAD_CTRL PAD_CTL_DSE_25ohm
> +
> +#define PHY_DQ_TIMING 0x00002613
> +#define PHY_DQS_TIMING 0x00002615
> +#define PHY_CTRL 0x01210080
> +#define PHY_MASTER_CTRL 0x0001012a
> +#define PHY_SLAVE_CTRL 0x00012020
> +
> +iomux_v3_cfg_t const ddr_pads[] = {
> + MVF600_PAD_DDR_A15__DDR_A_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A14__DDR_A_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A13__DDR_A_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A12__DDR_A_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A11__DDR_A_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A10__DDR_A_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A9__DDR_A_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A8__DDR_A_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A7__DDR_A_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A6__DDR_A_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A5__DDR_A_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A4__DDR_A_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A3__DDR_A_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A2__DDR_A_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_A1__DDR_A_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_BA2__DDR_BA_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_BA1__DDR_BA_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_BA0__DDR_BA_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_CAS__DDR_CAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_CKE__DDR_CKE_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_CLK__DDR_CLK_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_CS__DDR_CS_B_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D15__DDR_D_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D14__DDR_D_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D13__DDR_D_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D12__DDR_D_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D11__DDR_D_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D10__DDR_D_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D9__DDR_D_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D8__DDR_D_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D7__DDR_D_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D6__DDR_D_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D5__DDR_D_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D4__DDR_D_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D3__DDR_D_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D2__DDR_D_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D1__DDR_D_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_D0__DDR_D_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_DQM1__DDR_DQM_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_DQM0__DDR_DQM_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_DQS1__DDR_DQS_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_DQS0__DDR_DQS_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_RAS__DDR_RAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_WE__DDR_WE_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_ODT1__DDR_ODT_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> + MVF600_PAD_DDR_ODT0__DDR_ODT_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +};
> +
As this is the first board with this SOC, it can be ok. But is this
setup valid only for this board ? Maybe the pads for RAM should be the
same. Then this part should be factorize elsewhere.
> +void setup_iomux_ddr(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
> +}
> +
> +void ddr_phy_init(void)
> +{
> + struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
> +
> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[0]);
> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[16]);
> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[32]);
> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[48]);
> +
> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[1]);
> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[17]);
> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[33]);
> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[49]);
> +
> + __raw_writel(PHY_CTRL, &ddrmr->phy[2]);
> + __raw_writel(PHY_CTRL, &ddrmr->phy[18]);
> + __raw_writel(PHY_CTRL, &ddrmr->phy[34]);
> + __raw_writel(PHY_CTRL, &ddrmr->phy[50]);
> +
> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[3]);
> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[19]);
> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[35]);
> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[51]);
> +
> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[4]);
> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[20]);
> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[36]);
> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[52]);
> +
Without reference manual, it is difficult to judge. But it is surely
difficult to read. What does hide under the magic index of the ddrmr
stucture ?
> + __raw_writel(0x00001105, &ddrmr->phy[50]);
> +}
And can you add useful define instead of raw number ?
> +
> +void ddr_ctrl_init(void)
> +{
> + struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
> +
> + __raw_writel(0x00000600, &ddrmr->cr[0]); /* LPDDR2 or DDR3 */
> + __raw_writel(0x00000020, &ddrmr->cr[2]); /* TINIT */
> + __raw_writel(0x0000007c, &ddrmr->cr[10]);
> +
> + __raw_writel(0x00013880, &ddrmr->cr[11]);
> + __raw_writel(0x0000050c, &ddrmr->cr[12]);
> + __raw_writel(0x15040404, &ddrmr->cr[13]);
> + __raw_writel(0x1406040F, &ddrmr->cr[14]);
> + __raw_writel(0x04040000, &ddrmr->cr[16]);
> + __raw_writel(0x006DB00C, &ddrmr->cr[17]);
> + __raw_writel(0x00000403, &ddrmr->cr[18]);
> +
> + __raw_writel(0x01000000, &ddrmr->cr[20]);
> + __raw_writel(0x06060101, &ddrmr->cr[21]);
> +
> + __raw_writel(0x000B0000, &ddrmr->cr[22]);
> + __raw_writel(0x03000200, &ddrmr->cr[23]);
> + __raw_writel(0x00000006, &ddrmr->cr[24]);
> +
> + __raw_writel(0x00010000, &ddrmr->cr[25]);
> + __raw_writel(0x0C28002C, &ddrmr->cr[26]);
> + __raw_writel(0x00000005, &ddrmr->cr[28]);
> + __raw_writel(0x00000003, &ddrmr->cr[29]);
> +
> + __raw_writel(0x0000000A, &ddrmr->cr[30]);
> + __raw_writel(0x00440200, &ddrmr->cr[31]);
> + __raw_writel(0x00010000, &ddrmr->cr[33]);
> + __raw_writel(0x00050500, &ddrmr->cr[34]);
> +
> + /* Frequency change */
> + __raw_writel(0x00000100, &ddrmr->cr[38]);
> + __raw_writel(0x04001002, &ddrmr->cr[39]);
> +
> + __raw_writel(0x00000001, &ddrmr->cr[41]);
> + __raw_writel(0x00000000, &ddrmr->cr[45]);
> + __raw_writel(0x00000000, &ddrmr->cr[46]);
> + __raw_writel(0x00000000, &ddrmr->cr[47]);
> +
> + /* DRAM device Mode registers */
> + __raw_writel(0x00460420, &ddrmr->cr[48]);
> + __raw_writel(0x00000000, &ddrmr->cr[49]);
> + __raw_writel(0x00000000, &ddrmr->cr[51]);
> + __raw_writel(0x00000000, &ddrmr->cr[57]);
> +
> + /* ZQ stuff */
> + __raw_writel(0x01000200, &ddrmr->cr[66]);
> + __raw_writel(0x02000040, &ddrmr->cr[67]);
> + __raw_writel(0x00000200, &ddrmr->cr[69]);
> +
> + __raw_writel(0x00000040, &ddrmr->cr[70]);
> + __raw_writel(0x00000000, &ddrmr->cr[71]);
> + __raw_writel(0x01000000, &ddrmr->cr[72]);
> +
> + /* DRAM controller misc */
> + __raw_writel(0x0a010300, &ddrmr->cr[73]);
> + __raw_writel(0x0101ffff, &ddrmr->cr[74]);
> + __raw_writel(0x01010101, &ddrmr->cr[75]);
> + __raw_writel(0x03030101, &ddrmr->cr[76]);
> + __raw_writel(0x01000101, &ddrmr->cr[77]);
> + __raw_writel(0x0000000C, &ddrmr->cr[78]);
> + __raw_writel(0x01000000, &ddrmr->cr[79]);
> +
> + /* Disable interrupts */
> + __raw_writel(0x1FFFFFFF, &ddrmr->cr[82]);
> +
> + /* ODT */
> + __raw_writel(0x01010000, &ddrmr->cr[87]);
> + __raw_writel(0x00040000, &ddrmr->cr[88]);
> + __raw_writel(0x00000002, &ddrmr->cr[89]);
> +
> + __raw_writel(0x00020000, &ddrmr->cr[91]);
> + __raw_writel(0x00000000, &ddrmr->cr[92]);
> +
> + __raw_writel(0x00002819, &ddrmr->cr[96]);
> +
> + /* AXI ports */
> + __raw_writel(0x00202000, &ddrmr->cr[105]);
> + __raw_writel(0x20200000, &ddrmr->cr[106]);
> + __raw_writel(0x00002020, &ddrmr->cr[110]);
> + __raw_writel(0x00202000, &ddrmr->cr[114]);
> + __raw_writel(0x20200000, &ddrmr->cr[115]);
> +
> + __raw_writel(0x00000101, &ddrmr->cr[117]);
> + __raw_writel(0x01010000, &ddrmr->cr[118]);
> + __raw_writel(0x00000000, &ddrmr->cr[119]);
> +
> + __raw_writel(0x02020000, &ddrmr->cr[120]);
> + __raw_writel(0x00000202, &ddrmr->cr[121]);
> + __raw_writel(0x01010064, &ddrmr->cr[122]);
> + __raw_writel(0x00000101, &ddrmr->cr[123]);
> + __raw_writel(0x00000064, &ddrmr->cr[124]);
> +
> + /* TDFI */
> + __raw_writel(0x00000000, &ddrmr->cr[125]);
> + __raw_writel(0x00000B00, &ddrmr->cr[126]);
> + __raw_writel(0x00000000, &ddrmr->cr[127]);
> +
> + __raw_writel(0x00000000, &ddrmr->cr[131]);
> + __raw_writel(0x00000506, &ddrmr->cr[132]);
> + __raw_writel(0x02000000, &ddrmr->cr[137]);
> + __raw_writel(0x04070303, &ddrmr->cr[139]);
> +
> + __raw_writel(0x00000000, &ddrmr->cr[136]);
> +
> + __raw_writel(0x68200000, &ddrmr->cr[154]);
> + __raw_writel(0x00000202, &ddrmr->cr[155]);
> + __raw_writel(0x00000006, &ddrmr->cr[158]);
> + __raw_writel(0x00000006, &ddrmr->cr[159]);
> +
> + ddr_phy_init();
> +
> + __raw_writel(0x00000601, &ddrmr->cr[0]);
> +
> + udelay(200);
> +}
Ditto. There are a lot of magical numbers here associated to magic indexes.
> +
> +static void clock_init(void)
> +{
> + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
> + struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
> +
> + __raw_writel(0x00000078, &ccm->clpcr);
> + __raw_writel(0x000fc000, &ccm->ccgr0);
> + __raw_writel(0xf00fc0c0, &ccm->ccgr1);
> + __raw_writel(0x0fff0303, &ccm->ccgr2);
> + __raw_writel(0x00000033, &ccm->ccgr3);
> + __raw_writel(0x33f0f003, &ccm->ccgr4);
> + __raw_writel(0x3003cc00, &ccm->ccgr6);
> + __raw_writel(0x0000033c, &ccm->ccgr7);
> + __raw_writel(0x0000000f, &ccm->ccgr9);
> +
> + __raw_writel(0x00002001, &anadig->pll2_ctrl);
> + __raw_writel(0x00011001, &anadig->pll5_ctrl);
> + __raw_writel(0x00002001, &anadig->pll1_ctrl);
> +
> + __raw_writel(0x00010005, &ccm->ccr);
> + __raw_writel(0x0003ff64, &ccm->ccsr);
> + __raw_writel(0x00000810, &ccm->cacrr);
> + __raw_writel(0x03cf0000, &ccm->cscmr1);
> + __raw_writel(0x01000000, &ccm->cscdr1);
> + __raw_writel(0x30004240, &ccm->cscdr2);
> + __raw_writel(0x00003f1f, &ccm->cscdr3);
> + __raw_writel(0, &ccm->cscmr2);
> + __raw_writel(0, &ccm->cscdr4);
> +}
The same here. Note that in most boards we use clrsetbits_le32() to set
the single bits and all bits are defined in the crm_regs.h.
> +int board_eth_init(bd_t *bis)
> +{
> + int ret;
> +
> + setup_iomux_enet();
> +
> + ret = cpu_eth_init(bis);
> + if (ret)
> + printf("FEC MXC: %s:failed\n", __func__);
> +
> + return 0;
> +}
Maybe not useful ? I mean, if you move setup_iomux_enet() into
board_early_init_f(), you can drop this function, because it simply
calls cpu_eth_init()
> diff --git a/include/configs/mvf600twr.h b/include/configs/mvf600twr.h
> new file mode 100644
> index 0000000..bb1f3ef
> --- /dev/null
> +++ b/include/configs/mvf600twr.h
> @@ -0,0 +1,147 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Freescale Vybrid mvf600twr board.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <asm/arch/imx-regs.h>
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_MVF600
> +
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define MACH_TYPE_VYBRID_VF6XX 4146
> +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX
Your choice, but maybe you could drop MACH_TYPE_VYBRID_VF6XX, because it
is not used in any file.
> +
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +
> +#define CONFIG_SYS_ICACHE_OFF
> +#define CONFIG_SYS_CACHELINE_SIZE 64
On the website, cache is marked "optional" in the figure. Does it mean
that some SOC have instruction cache and other ones not ?
Is this setup related to the fact that you use start.S inside armv7 and
something is not compatible ?
> +
> +/* Enable passing of ATAGs */
> +#define CONFIG_CMDLINE_TAG
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +#define CONFIG_FSL_LPUART
> +
> +/* Allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_SYS_UART_PORT (1)
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
> +
> +#define CONFIG_CMD_BDI /* bdinfo */
> +#define CONFIG_CMD_BOOTD
> +#define CONFIG_CMD_CONSOLE /* coninfo */
> +#define CONFIG_CMD_ELF
> +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
> +#define CONFIG_CMD_MISC
> +#undef CONFIG_CMD_IMLS
You do not include cmd_default.h. Is it wanted ?
> +
> +/* MUX mode and PAD ctrl are in one register */
> +#define CONFIG_IOMUX_SHARE_CONF_REG
NAK. This is not a board configuration, it is related to the SOC. This
setup should flow into the related imx-regs.h for this SOC. When you set
CONFIG_MVF600, this value should be set automatically.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support
2013-05-15 8:13 ` Stefano Babic
@ 2013-05-15 12:09 ` Albert ARIBAUD
2013-05-15 12:24 ` Stefano Babic
2013-05-16 4:00 ` [U-Boot] " Wang Huan-B18965
1 sibling, 1 reply; 25+ messages in thread
From: Albert ARIBAUD @ 2013-05-15 12:09 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Wed, 15 May 2013 10:13:36 +0200, Stefano Babic <sbabic@denx.de>
wrote:
> On 14/05/2013 11:51, Alison Wang wrote:
> > This patch adds generic codes to support Freescale's Vybrid MVF600 CPU.
> >
> > It aligns Vybrid MVF600 platform with i.MX platform. As there are
> > some differences between MVF600 and i.MX platforms, the specific
> > codes are in the arch/arm/cpu/armv7/mvf600 directory.
> >
> > Signed-off-by: Alison Wang <b18965@freescale.com>
> > ---
>
> Hi Alison,
>
> > Changes in v2:
> > - Remove vybrid-common directory
> > - Rename directory name 'vybrid' to 'mvf600'
> > - Add generic.c file
> > - Rewrite get_reset_cause() to make it readable
> > - Remove reset_cpu(), and use the function in imx_watchdog.c
> > - Rewrite timer.c file
> > - Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk()
> > - Remove lowlevel_init.S, and add clock_init() in board_early_init_f()
> > - Remove useless CONFIG_SYS_ defines
> > - Move CONFIG_MACH_TYPE to board configuration file
> > - Define C structures and access C structures to set/read registers
> > - Remove useless errata
> > - Remove useless macros
> > - Rename directory 'arch-vybrid' to 'arch-mvf600'
> >
> > Makefile | 2 +-
> > arch/arm/cpu/armv7/mvf600/Makefile | 42 ++++
> > arch/arm/cpu/armv7/mvf600/generic.c | 309 ++++++++++++++++++++++++++++
>
> Just a minor concern here. The SOC is a ARMv5, but files go into the
> armv7 directory. Maybe the bigger issue can be with the increasing
> number of work-around (CONFIG_ERRATA) that flow into start.S for armv7,
> that are specific only for armv7. I know that for ARMv5 we split
> differently instead of ARM architecture (ARM926,...).
>
> Albert, what do you think about ? Should these files be moved away from
> armv7 ?
If the SoC is ARMv5, then yes, its arch/arm/cpu files should not go in
armv7 -- and then, we may have to discuss whether, and how, to factorize
ISA-level code. Maybe we need an arch/arm/isa/armv{4,5,6,7...} beside
arch/cpu, and move wherever is isa-specific there.
Regarding errata, I don't understand your point: if they are specific
to armv7, then arch/arm/cpu/armv7/start.S seems to be the place to put
them (assuming they affect execution before board_init_f() of course).
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support
2013-05-15 12:09 ` Albert ARIBAUD
@ 2013-05-15 12:24 ` Stefano Babic
2013-05-15 12:39 ` Albert ARIBAUD
0 siblings, 1 reply; 25+ messages in thread
From: Stefano Babic @ 2013-05-15 12:24 UTC (permalink / raw)
To: u-boot
On 15/05/2013 14:09, Albert ARIBAUD wrote:
>>
>> Albert, what do you think about ? Should these files be moved away from
>> armv7 ?
>
> If the SoC is ARMv5, then yes, its arch/arm/cpu files should not go in
> armv7 -- and then, we may have to discuss whether, and how, to factorize
> ISA-level code. Maybe we need an arch/arm/isa/armv{4,5,6,7...} beside
> arch/cpu, and move wherever is isa-specific there.
Agree. I think adding armv{4,5,6,7...} is the most clean solution.
>
> Regarding errata, I don't understand your point: if they are specific
> to armv7, then arch/arm/cpu/armv7/start.S seems to be the place to put
> them (assuming they affect execution before board_init_f() of course).
I was not able to express my point, sorry. Of course, the right place
for them is arch/arm/cpu/armv7/start.S. My concern was related to this
SOC, as it seems it steals armv7 code but it is not armv7. Then changes
in start.S, that fixes real problems for armv7, can break this Vybrid.
But the reason is that Vybrid initialization should not be taken from
arch/arm/cpu/armv7/start.S.
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support
2013-05-15 12:24 ` Stefano Babic
@ 2013-05-15 12:39 ` Albert ARIBAUD
2013-05-15 13:20 ` Stefano Babic
0 siblings, 1 reply; 25+ messages in thread
From: Albert ARIBAUD @ 2013-05-15 12:39 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Wed, 15 May 2013 14:24:33 +0200, Stefano Babic <sbabic@denx.de>
wrote:
> On 15/05/2013 14:09, Albert ARIBAUD wrote:
> >>
> >> Albert, what do you think about ? Should these files be moved away from
> >> armv7 ?
> >
> > If the SoC is ARMv5, then yes, its arch/arm/cpu files should not go in
> > armv7 -- and then, we may have to discuss whether, and how, to factorize
> > ISA-level code. Maybe we need an arch/arm/isa/armv{4,5,6,7...} beside
> > arch/cpu, and move wherever is isa-specific there.
>
> Agree. I think adding armv{4,5,6,7...} is the most clean solution.
This is a clean solution, but do we have the problem? IOW, do we have a
substantial quantity of code that is common to a given ISA but neither
generic to ARM (if it were, it would go to arch/arm or arch/arm/lib) nor
specific to a CPU (if it were, then it should stay under arch/arm/cpu/)?
If we do then moving this code under an isa tree makes sense; if we
don't, then arch/arm/cpu/<cpu>/<soc> is enough, and mvf600 just jas to
move under arch/arm/cpu/ and copy the few ARMv5 snippets it needs from
another ARMv5-based cpu.
IMO, the proof is in the pudding: if I see a patch that creates e.g.
arch/arm/isa/armv5 and factorizes isa code there from cpu subdirs, and
if this results in a smaller codebase (apart from doc) and no binary
size increase, then I'll ack it and apply it [albeit on next as the
merge window is now closed].
> > Regarding errata, I don't understand your point: if they are specific
> > to armv7, then arch/arm/cpu/armv7/start.S seems to be the place to put
> > them (assuming they affect execution before board_init_f() of course).
>
> I was not able to express my point, sorry. Of course, the right place
> for them is arch/arm/cpu/armv7/start.S. My concern was related to this
> SOC, as it seems it steals armv7 code but it is not armv7. Then changes
> in start.S, that fixes real problems for armv7, can break this Vybrid.
> But the reason is that Vybrid initialization should not be taken from
> arch/arm/cpu/armv7/start.S.
I understand now, and this is a valid point -- all the more a reason to
move mvf600 under arch/cpu/, with or without factorizing armv5 code.
> Best regards,
> Stefano
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support
2013-05-15 12:39 ` Albert ARIBAUD
@ 2013-05-15 13:20 ` Stefano Babic
[not found] ` <81BA6E5E0BC2344391CABCEE22D1B6D8322144@039-SN1MPN1-002.039d.mgd.msft.net>
0 siblings, 1 reply; 25+ messages in thread
From: Stefano Babic @ 2013-05-15 13:20 UTC (permalink / raw)
To: u-boot
On 15/05/2013 14:39, Albert ARIBAUD wrote:
> Hi Stefano,
>
Hi Albert, hi Alison,
>> Agree. I think adding armv{4,5,6,7...} is the most clean solution.
>
> This is a clean solution, but do we have the problem? IOW, do we have a
> substantial quantity of code that is common to a given ISA but neither
> generic to ARM (if it were, it would go to arch/arm or arch/arm/lib) nor
> specific to a CPU (if it were, then it should stay under arch/arm/cpu/)?
> If we do then moving this code under an isa tree makes sense; if we
> don't, then arch/arm/cpu/<cpu>/<soc> is enough, and mvf600 just jas to
> move under arch/arm/cpu/ and copy the few ARMv5 snippets it needs from
> another ARMv5-based cpu.
Roght - this is also a clean solution, because we have already arm926
and so on. Alison, please check how you can move your initialization
code as Alber suggested.
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 2/6] arm: mvf600: Add IOMUX support for Vybrid MVF600
2013-05-15 8:16 ` Stefano Babic
@ 2013-05-15 13:53 ` Benoît Thébaudeau
0 siblings, 0 replies; 25+ messages in thread
From: Benoît Thébaudeau @ 2013-05-15 13:53 UTC (permalink / raw)
To: u-boot
Hi Stefano, Alison,
On Wednesday, May 15, 2013 10:16:40 AM, Stefano Babic wrote:
> On 14/05/2013 11:51, Alison Wang wrote:
> > This patch adds the IOMUX support for Vybrid MVF600 platform.
> >
> > There is a little difference for IOMUXC module between MVF600 and i.MX
> > platform, the muxmode and pad configuration share one 32bit register on
> > MVF600, but they are two independent registers on I.MX platform. A
> > CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
> >
> > Signed-off-by: Alison Wang <b18965@freescale.com>
> > ---
> > Changes in v2:
> > - Use common iomux-v3 code
> >
> > arch/arm/imx-common/Makefile | 2 +-
> > arch/arm/imx-common/iomux-v3.c | 6 ++++++
> > arch/arm/include/asm/imx-common/iomux-v3.h | 18 ++++++++++++++++++
> > 3 files changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
> > index 8bba8a5..3378931 100644
> > --- a/arch/arm/imx-common/Makefile
> > +++ b/arch/arm/imx-common/Makefile
> > @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
> >
> > LIB = $(obj)libimx-common.o
> >
> > -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6))
> > +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mvf600))
> > COBJS-y = iomux-v3.o
> > endif
> > ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
> > diff --git a/arch/arm/imx-common/iomux-v3.c
> > b/arch/arm/imx-common/iomux-v3.c
> > index 7fe5ce7..35880c7 100644
> > --- a/arch/arm/imx-common/iomux-v3.c
> > +++ b/arch/arm/imx-common/iomux-v3.c
> > @@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
> > if (sel_input_ofs)
> > __raw_writel(sel_input, base + sel_input_ofs);
> >
> > +#ifdef CONFIG_IOMUX_SHARE_CONF_REG
> > + if (!(pad_ctrl & NO_PAD_CTRL))
> > + __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
> > + base + pad_ctrl_ofs);
> > +#else
> > if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
> > __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
> > +#endif
> > }
> >
> > void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
> > diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h
> > b/arch/arm/include/asm/imx-common/iomux-v3.h
> > index 0b4e763..7005fde 100644
> > --- a/arch/arm/include/asm/imx-common/iomux-v3.h
> > +++ b/arch/arm/include/asm/imx-common/iomux-v3.h
> > @@ -121,6 +121,24 @@ typedef u64 iomux_v3_cfg_t;
> > #define PAD_CTL_DSE_40ohm (6 << 3)
> > #define PAD_CTL_DSE_34ohm (7 << 3)
> >
> > +#elif defined(CONFIG_MVF600)
> > +
> > +#define PAD_MUX_MODE_SHIFT 20
> > +
> > +#define PAD_CTL_PUS_47K_UP (1 << 4)
> > +#define PAD_CTL_PUS_100K_UP (2 << 4)
> > +#define PAD_CTL_PUE (1 << 2)
> > +#define PAD_CTL_PKE (1 << 3)
> > +
> > +#define PAD_CTL_SPEED_HIGH (3 << 12)
> > +#define PAD_CTL_SPEED_MED (1 << 12)
> > +
> > +#define PAD_CTL_DSE_20ohm (7 << 6)
> > +#define PAD_CTL_DSE_25ohm (6 << 6)
> > +#define PAD_CTL_DSE_50ohm (3 << 6)
> > +
> > +#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
> > +
> > #else
> >
> > #define PAD_CTL_DVS (1 << 13)
> >
>
> Acked-by: Stefano Babic <sbabic@denx.de>
Could you please just fix the spaces/tabs mess in the #define-s?
Thanks.
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 3/6] arm: mvf600: Add FEC support for Vybrid MVF600
2013-05-15 8:15 ` Stefano Babic
@ 2013-05-15 14:19 ` Benoît Thébaudeau
0 siblings, 0 replies; 25+ messages in thread
From: Benoît Thébaudeau @ 2013-05-15 14:19 UTC (permalink / raw)
To: u-boot
Hi Stefano, Alison,
On Wednesday, May 15, 2013 10:15:35 AM, Stefano Babic wrote:
> On 14/05/2013 11:51, Alison Wang wrote:
> > This patch adds FEC support for Vybrid MVF600 platform.
> > Add code to use RMII for MVF600.
> >
> > Signed-off-by: Alison Wang <b18965@freescale.com>
> > ---
> > Changes in v2:
> > - Use common FEC driver fec_mxc.c
> >
> > drivers/net/fec_mxc.c | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> > index 4dbcdca..21e58f4 100644
> > --- a/drivers/net/fec_mxc.c
> > +++ b/drivers/net/fec_mxc.c
> > @@ -518,7 +518,11 @@ static int fec_open(struct eth_device *edev)
> > u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
> > u32 rcr = (readl(&fec->eth->r_cntrl) &
> > ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
> > - FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
> > + FEC_RCNTRL_MII_MODE;
> > + if (fec->xcv_type == RGMII)
> > + rcr |= FEC_RCNTRL_RGMII;
> > + else if (fec->xcv_type == RMII)
> > + rcr |= FEC_RCNTRL_RMII;
> > if (speed == _1000BASET)
> > ecr |= FEC_ECNTRL_SPEED;
> > else if (speed != _100BASET)
> >
>
> This can generally be applied, it is not only related to the new SOC.
>
> Acked-by: Stefano Babic <sbabic@denx.de>
This is already done in fec_reg_setup(), so the piece of code above could
perhaps just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits, i.e.:
---
#ifdef FEC_QUIRK_ENET_MAC
{
u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
- u32 rcr = (readl(&fec->eth->r_cntrl) &
- ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
- FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
+ u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
if (speed == _1000BASET)
ecr |= FEC_ECNTRL_SPEED;
else if (speed != _100BASET)
---
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] 答复: [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support
[not found] ` <81BA6E5E0BC2344391CABCEE22D1B6D8322144@039-SN1MPN1-002.039d.mgd.msft.net>
@ 2013-05-15 14:23 ` Stefano Babic
0 siblings, 0 replies; 25+ messages in thread
From: Stefano Babic @ 2013-05-15 14:23 UTC (permalink / raw)
To: u-boot
On 15/05/2013 15:55, Wang Huan-B18965 wrote:
>
> Hi, Stefano,
>
> Vybrid MVF600 is a dual-core eMPU combining the ARM Cortex A5 and Cortex M4 cores.
> Cortex A5 is a processor core designed by implementing the ARM v7 instruction set architecture.
> So I put the codes in the armv7 directory.
Ok, got it. Then it is fine to have in armv7 directory.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support
2013-05-15 8:13 ` Stefano Babic
2013-05-15 12:09 ` Albert ARIBAUD
@ 2013-05-16 4:00 ` Wang Huan-B18965
1 sibling, 0 replies; 25+ messages in thread
From: Wang Huan-B18965 @ 2013-05-16 4:00 UTC (permalink / raw)
To: u-boot
Hi, Stefano,
>
> On 14/05/2013 11:51, Alison Wang wrote:
> > This patch adds generic codes to support Freescale's Vybrid MVF600 CPU.
> >
> > It aligns Vybrid MVF600 platform with i.MX platform. As there are some
> > differences between MVF600 and i.MX platforms, the specific codes are
> > in the arch/arm/cpu/armv7/mvf600 directory.
> >
> > Signed-off-by: Alison Wang <b18965@freescale.com>
> > ---
>
> Hi Alison,
>
> > Changes in v2:
> > - Remove vybrid-common directory
> > - Rename directory name 'vybrid' to 'mvf600'
> > - Add generic.c file
> > - Rewrite get_reset_cause() to make it readable
> > - Remove reset_cpu(), and use the function in imx_watchdog.c
> > - Rewrite timer.c file
> > - Use vybrid_get_clock(VYBRID_UART_CLK) instead of
> > vybrid_get_uartclk()
> > - Remove lowlevel_init.S, and add clock_init() in board_early_init_f()
> > - Remove useless CONFIG_SYS_ defines
> > - Move CONFIG_MACH_TYPE to board configuration file
> > - Define C structures and access C structures to set/read registers
> > - Remove useless errata
> > - Remove useless macros
> > - Rename directory 'arch-vybrid' to 'arch-mvf600'
> >
> > Makefile | 2 +-
> > arch/arm/cpu/armv7/mvf600/Makefile | 42 ++++
> > arch/arm/cpu/armv7/mvf600/generic.c | 309
> ++++++++++++++++++++++++++++
>
> Just a minor concern here. The SOC is a ARMv5, but files go into the
> armv7 directory. Maybe the bigger issue can be with the increasing number
> of work-around (CONFIG_ERRATA) that flow into start.S for armv7, that are
> specific only for armv7. I know that for ARMv5 we split differently
> instead of ARM architecture (ARM926,...).
>
> Albert, what do you think about ? Should these files be moved away from
> armv7 ?
>
> > +unsigned int mvf_get_clock(enum mvf_clock clk) {
> > + switch (clk) {
> > + case MVF_ARM_CLK:
> > + return get_mcu_main_clk();
> > + case MVF_BUS_CLK:
> > + return get_bus_clk();
> > + case MVF_IPG_CLK:
> > + return get_ipg_clk();
> > + case MVF_UART_CLK:
> > + return get_uart_clk();
> > + case MVF_ESDHC_CLK:
> > + return get_sdhc_clk();
> > + case MVF_FEC_CLK:
> > + return get_fec_clk();
> > + default:
> > + break;
> > + }
> > + return -1;
> > +}
>
> Ok - we have the same structure as for i.MX. I agree with you that the
> name of the function mxc_get_clock() is not anymore correct, after some
> other Freescale's SOC families were introduced. However, it is still
> important to have a common API to expone a SOC to a board maintainer.
>
> If you see, the mxs family (MX23 / MX28) has a mxc_get_clock(), even if
> most internal functions are marked as mxs_. I think we can later change
> the name for this function (maybe this is not the only one) to make the
> name clearer and not specific to i.MX, but then it is will be easier if
> all SOCs use the same names. For this reason, it is better to rename this
> function to mxc_get_clock() and please take the same enums that are
> already set for the other Freescale's SOCs.
[Alison Wang] Agree. I will rename this function to mxc_get_clock() and take the
same enums. Thanks.
>
> > +
> > +#ifdef CONFIG_FEC_MXC
> > +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) {
> > + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
> > + struct fuse_bank *bank = &ocotp->bank[4];
> > + struct fuse_bank4_regs *fuse =
> > + (struct fuse_bank4_regs *)bank->fuse_regs;
> > +
> > + u32 value = readl(&fuse->mac_addr0);
> > + mac[0] = (value >> 8);
> > + mac[1] = value;
>
> To my knowledge : is the whole MAC stored in the ocotp ? No need to add
> the first bytes (vendor-id) as we had for MX28 ?
[Alison Wang] Yes, the whole MAC is stored in the ocotp for Vybrid.
>
> > diff --git a/arch/arm/cpu/armv7/mvf600/timer.c
> > b/arch/arm/cpu/armv7/mvf600/timer.c
> > new file mode 100644
> > index 0000000..99ca57d
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/mvf600/timer.c
> > @@ -0,0 +1,144 @@
> > +/*
> > + * Copyright 2013 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <div64.h>
> > +#include <asm/arch/imx-regs.h>
> > +#include <asm/arch/clock.h>
> > +
> > +/* Periodic interrupt timer registers */ struct pit_reg {
> > + u32 mcr;
> > + u32 recv0[55];
> > + u32 ltmr64h;
> > + u32 ltmr64l;
> > + u32 recv1[6];
> > + u32 ldval0;
> > + u32 cval0;
> > + u32 tctrl0;
> > + u32 tflg0;
> > + u32 ldval1;
> > + u32 cval1;
> > + u32 tctrl1;
> > + u32 tflg1;
> > + u32 ldval2;
> > + u32 cval2;
> > + u32 tctrl2;
> > + u32 tflg2;
> > + u32 ldval3;
> > + u32 cval3;
> > + u32 tctrl3;
> > + u32 tflg3;
> > + u32 ldval4;
> > + u32 cval4;
> > + u32 tctrl4;
> > + u32 tflg4;
> > + u32 ldval5;
> > + u32 cval5;
> > + u32 tctrl5;
> > + u32 tflg5;
> > + u32 ldval6;
> > + u32 cval6;
> > + u32 tctrl6;
> > + u32 tflg6;
> > + u32 ldval7;
> > + u32 cval7;
> > + u32 tctrl7;
> > + u32 tflg7;
> > +};
> > +
>
> I had put these structure in imx-regs.h - no block from my side, but
> there is also no big reason to let it here.
[Alison Wang] Agree. I will put these structures to imx-regs.h. Thanks.
>
>
> > diff --git a/arch/arm/include/asm/arch-mvf600/clock.h
> > b/arch/arm/include/asm/arch-mvf600/clock.h
> > new file mode 100644
> > index 0000000..889d4d9
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-mvf600/clock.h
> > @@ -0,0 +1,38 @@
> > +/*
> > + * Copyright 2013 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#ifndef __ASM_ARCH_CLOCK_H
> > +#define __ASM_ARCH_CLOCK_H
> > +
> > +#include <common.h>
> > +
> > +enum mvf_clock {
> > + MVF_ARM_CLK = 0,
> > + MVF_BUS_CLK,
> > + MVF_IPG_CLK,
> > + MVF_UART_CLK,
> > + MVF_ESDHC_CLK,
> > + MVF_FEC_CLK,
> > +};
> > +
> > +unsigned int mvf_get_clock(enum mvf_clock clk);
> > +
> > +#define imx_get_fecclk() mvf_get_clock(MVF_FEC_CLK)
>
> See my previous comment. Agree the names are not anymore correct, but we
> can fix them later with a separate patch for all Freescale's SOCs.
[Alison Wang] Agree. I will change the names. Thanks.
>
>
> > +/* On-Chip One Time Programmable Controller (OCOTP) */ struct
> > +ocotp_regs {
> > + u32 ctrl;
> > + u32 ctrl_set;
> > + u32 ctrl_clr;
> > + u32 ctrl_tog;
> > + u32 timing;
> > + u32 rsvd0[3];
> > + u32 data;
> > + u32 rsvd1[3];
> > + u32 read_ctr;
> > + u32 rsvd2[3];
> > + u32 read_fuse_data;
> > + u32 rsvd3[7];
> > + u32 scs;
> > + u32 scs_set;
> > + u32 scs_clr;
> > + u32 scs_tog;
> > + u32 crc_addr;
> > + u32 rsvd4[3];
> > + u32 crc_value;
> > + u32 rsvd5[3];
> > + u32 version;
> > + u32 rsvd6[0xdb];
> > +
> > + struct fuse_bank {
> > + u32 fuse_regs[0x20];
> > + } bank[16];
> > +};
> > +
> > +/* OTP Bank 4 */
> > +struct fuse_bank4_regs {
> > + u32 sjc_resp0;
> > + u32 rsvd0[3];
> > + u32 sjc_resp1;
> > + u32 rsvd1[3];
> > + u32 mac_addr0;
> > + u32 rsvd2[3];
> > + u32 mac_addr1;
> > + u32 rsvd3[3];
> > + u32 mac_addr2;
> > + u32 rsvd4[3];
> > + u32 mac_addr3;
> > + u32 rsvd5[3];
> > + u32 gp1;
> > + u32 rsvd6[3];
> > + u32 gp2;
> > + u32 rsvd7[3];
> > +};
> > +
>
> Have you seen that a driver for fuse / ocotp was recently added to
> mainline ? Have you tested on your platform ?
[Alison Wang] Yes, I saw the driver and tested it on my platform just now. It worked fine.
I could enable ocotp support in the next version patch.
Thanks!
Best Regards,
Alison Wang
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board
2013-05-15 9:01 ` Stefano Babic
@ 2013-05-17 15:20 ` Wang Huan-B18965
2013-05-17 16:07 ` Stefano Babic
0 siblings, 1 reply; 25+ messages in thread
From: Wang Huan-B18965 @ 2013-05-17 15:20 UTC (permalink / raw)
To: u-boot
Hi, Stefano,
>
> On 14/05/2013 11:51, Alison Wang wrote:
> > MVF600TWR is a board based on Vybrid MVF600 SoC.
> >
> > This patch adds basic support for Vybrid MVF600TWR board.
> >
> > Signed-off-by: Alison Wang <b18965@freescale.com>
> > Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> > Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> > ---
>
> Hi Alison,
>
> > diff --git a/board/freescale/mvf600twr/imximage.cfg
> > b/board/freescale/mvf600twr/imximage.cfg
> > new file mode 100644
> > index 0000000..33ead0f
> > --- /dev/null
> > +++ b/board/freescale/mvf600twr/imximage.cfg
> > @@ -0,0 +1,35 @@
> > +/*
> > + * Copyright 2013 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not write to the Free Software
> > + * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> > + * MA 02110-1301 USA
> > + *
> > + * Refer docs/README.imxmage for more details about how-to configure
> > + * and create imximage boot image
> > + *
> > + * The syntax is taken as close as possible with the kwbimage */
> > +
> > +/* image version */
> > +IMAGE_VERSION 2
> > +
> > +/*
> > + * Boot Device : one of
> > + * spi, sd (the board has no nand neither onenand) */
> > +BOOT_FROM sd
>
> Ok, verstanden (I hope). This SOC has plenty of internal IRAM. It still
> uses the imximage mechanism, but you decided to start from internal RAM
> instead of DDR and to set up the RAM controller in the board
> initialization function.
>
> We recently discussed about the wrongness of BOOT_FROM command. It makes
> no sense, and it was replaced by BOOT_OFFSET. If the SOC uses the main
> common offset (0x400), you can put
>
> BOOT_OFFSET FLASH_OFFSET_STANDARD
>
[Alison Wang] I will use BOOT_OFFSET. Thanks.
>
> > +#include <netdev.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |
> \
> > + PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
> > +
> > +#define ESDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |
> PAD_CTL_PUS_100K_UP | \
> > + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | \
> > + PAD_CTL_OBE_IBE_ENABLE)
>
> Please see commit 7e2173cf82d0bc235b695460c56d46927febdf36 and adjust
> this SOC consequently. PUE requires that PKE is enabled, that means that
> setting PKE alone does nothing. Then it is better to define PAD_CTL_PUE
> so that PKE is enabled, so in your 2/6 (that I have too fast acked):
>
> PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
>
> and drop PAD_CTL_PKE here. This must fixed globally.
[Alison Wang] Agree, I will change as above. Thanks.
>
> > +#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH |
> \
> > + PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
> > +
> > +#define DDR_PAD_CTRL PAD_CTL_DSE_25ohm
> > +
> > +#define PHY_DQ_TIMING 0x00002613
> > +#define PHY_DQS_TIMING 0x00002615
> > +#define PHY_CTRL 0x01210080
> > +#define PHY_MASTER_CTRL 0x0001012a
> > +#define PHY_SLAVE_CTRL 0x00012020
> > +
> > +iomux_v3_cfg_t const ddr_pads[] = {
> > + MVF600_PAD_DDR_A15__DDR_A_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A14__DDR_A_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A13__DDR_A_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A12__DDR_A_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A11__DDR_A_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A10__DDR_A_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A9__DDR_A_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A8__DDR_A_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A7__DDR_A_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A6__DDR_A_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A5__DDR_A_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A4__DDR_A_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A3__DDR_A_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A2__DDR_A_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_A1__DDR_A_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_BA2__DDR_BA_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_BA1__DDR_BA_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_BA0__DDR_BA_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_CAS__DDR_CAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_CKE__DDR_CKE_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_CLK__DDR_CLK_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_CS__DDR_CS_B_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D15__DDR_D_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D14__DDR_D_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D13__DDR_D_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D12__DDR_D_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D11__DDR_D_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D10__DDR_D_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D9__DDR_D_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D8__DDR_D_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D7__DDR_D_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D6__DDR_D_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D5__DDR_D_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D4__DDR_D_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D3__DDR_D_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D2__DDR_D_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D1__DDR_D_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_D0__DDR_D_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_DQM1__DDR_DQM_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_DQM0__DDR_DQM_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_DQS1__DDR_DQS_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_DQS0__DDR_DQS_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_RAS__DDR_RAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_WE__DDR_WE_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_ODT1__DDR_ODT_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > + MVF600_PAD_DDR_ODT0__DDR_ODT_1 | MUX_PAD_CTRL(DDR_PAD_CTRL), };
> > +
>
> As this is the first board with this SOC, it can be ok. But is this setup
> valid only for this board ? Maybe the pads for RAM should be the same.
> Then this part should be factorize elsewhere.
>
> > +void setup_iomux_ddr(void)
> > +{
> > + imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); }
> > +
> > +void ddr_phy_init(void)
> > +{
> > + struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
> > +
> > + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[0]);
> > + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[16]);
> > + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[32]);
> > + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[48]);
> > +
> > + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[1]);
> > + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[17]);
> > + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[33]);
> > + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[49]);
> > +
> > + __raw_writel(PHY_CTRL, &ddrmr->phy[2]);
> > + __raw_writel(PHY_CTRL, &ddrmr->phy[18]);
> > + __raw_writel(PHY_CTRL, &ddrmr->phy[34]);
> > + __raw_writel(PHY_CTRL, &ddrmr->phy[50]);
> > +
> > + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[3]);
> > + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[19]);
> > + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[35]);
> > + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[51]);
> > +
> > + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[4]);
> > + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[20]);
> > + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[36]);
> > + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[52]);
> > +
>
> Without reference manual, it is difficult to judge. But it is surely
> difficult to read. What does hide under the magic index of the ddrmr
> stucture ?
[Alison Wang] In the reference manual, the registers are named as phy00, phy01, phy02.... cr00, cr01, cr02....
I think there may be some confusion if I rename the registers.
>
>
> > + __raw_writel(0x00001105, &ddrmr->phy[50]); }
>
> And can you add useful define instead of raw number ?
[Alison Wang] Yes, I will add useful define.
>
> > +
> > +void ddr_ctrl_init(void)
> > +{
> > + struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
> > +
> > + __raw_writel(0x00000600, &ddrmr->cr[0]); /* LPDDR2 or DDR3 */
> > + __raw_writel(0x00000020, &ddrmr->cr[2]); /* TINIT */
> > + __raw_writel(0x0000007c, &ddrmr->cr[10]);
> > +
> > + __raw_writel(0x00013880, &ddrmr->cr[11]);
> > + __raw_writel(0x0000050c, &ddrmr->cr[12]);
> > + __raw_writel(0x15040404, &ddrmr->cr[13]);
> > + __raw_writel(0x1406040F, &ddrmr->cr[14]);
> > + __raw_writel(0x04040000, &ddrmr->cr[16]);
> > + __raw_writel(0x006DB00C, &ddrmr->cr[17]);
> > + __raw_writel(0x00000403, &ddrmr->cr[18]);
> > +
> > + __raw_writel(0x01000000, &ddrmr->cr[20]);
> > + __raw_writel(0x06060101, &ddrmr->cr[21]);
> > +
> > + __raw_writel(0x000B0000, &ddrmr->cr[22]);
> > + __raw_writel(0x03000200, &ddrmr->cr[23]);
> > + __raw_writel(0x00000006, &ddrmr->cr[24]);
> > +
> > + __raw_writel(0x00010000, &ddrmr->cr[25]);
> > + __raw_writel(0x0C28002C, &ddrmr->cr[26]);
> > + __raw_writel(0x00000005, &ddrmr->cr[28]);
> > + __raw_writel(0x00000003, &ddrmr->cr[29]);
> > +
> > + __raw_writel(0x0000000A, &ddrmr->cr[30]);
> > + __raw_writel(0x00440200, &ddrmr->cr[31]);
> > + __raw_writel(0x00010000, &ddrmr->cr[33]);
> > + __raw_writel(0x00050500, &ddrmr->cr[34]);
> > +
> > + /* Frequency change */
> > + __raw_writel(0x00000100, &ddrmr->cr[38]);
> > + __raw_writel(0x04001002, &ddrmr->cr[39]);
> > +
> > + __raw_writel(0x00000001, &ddrmr->cr[41]);
> > + __raw_writel(0x00000000, &ddrmr->cr[45]);
> > + __raw_writel(0x00000000, &ddrmr->cr[46]);
> > + __raw_writel(0x00000000, &ddrmr->cr[47]);
> > +
> > + /* DRAM device Mode registers */
> > + __raw_writel(0x00460420, &ddrmr->cr[48]);
> > + __raw_writel(0x00000000, &ddrmr->cr[49]);
> > + __raw_writel(0x00000000, &ddrmr->cr[51]);
> > + __raw_writel(0x00000000, &ddrmr->cr[57]);
> > +
> > + /* ZQ stuff */
> > + __raw_writel(0x01000200, &ddrmr->cr[66]);
> > + __raw_writel(0x02000040, &ddrmr->cr[67]);
> > + __raw_writel(0x00000200, &ddrmr->cr[69]);
> > +
> > + __raw_writel(0x00000040, &ddrmr->cr[70]);
> > + __raw_writel(0x00000000, &ddrmr->cr[71]);
> > + __raw_writel(0x01000000, &ddrmr->cr[72]);
> > +
> > + /* DRAM controller misc */
> > + __raw_writel(0x0a010300, &ddrmr->cr[73]);
> > + __raw_writel(0x0101ffff, &ddrmr->cr[74]);
> > + __raw_writel(0x01010101, &ddrmr->cr[75]);
> > + __raw_writel(0x03030101, &ddrmr->cr[76]);
> > + __raw_writel(0x01000101, &ddrmr->cr[77]);
> > + __raw_writel(0x0000000C, &ddrmr->cr[78]);
> > + __raw_writel(0x01000000, &ddrmr->cr[79]);
> > +
> > + /* Disable interrupts */
> > + __raw_writel(0x1FFFFFFF, &ddrmr->cr[82]);
> > +
> > + /* ODT */
> > + __raw_writel(0x01010000, &ddrmr->cr[87]);
> > + __raw_writel(0x00040000, &ddrmr->cr[88]);
> > + __raw_writel(0x00000002, &ddrmr->cr[89]);
> > +
> > + __raw_writel(0x00020000, &ddrmr->cr[91]);
> > + __raw_writel(0x00000000, &ddrmr->cr[92]);
> > +
> > + __raw_writel(0x00002819, &ddrmr->cr[96]);
> > +
> > + /* AXI ports */
> > + __raw_writel(0x00202000, &ddrmr->cr[105]);
> > + __raw_writel(0x20200000, &ddrmr->cr[106]);
> > + __raw_writel(0x00002020, &ddrmr->cr[110]);
> > + __raw_writel(0x00202000, &ddrmr->cr[114]);
> > + __raw_writel(0x20200000, &ddrmr->cr[115]);
> > +
> > + __raw_writel(0x00000101, &ddrmr->cr[117]);
> > + __raw_writel(0x01010000, &ddrmr->cr[118]);
> > + __raw_writel(0x00000000, &ddrmr->cr[119]);
> > +
> > + __raw_writel(0x02020000, &ddrmr->cr[120]);
> > + __raw_writel(0x00000202, &ddrmr->cr[121]);
> > + __raw_writel(0x01010064, &ddrmr->cr[122]);
> > + __raw_writel(0x00000101, &ddrmr->cr[123]);
> > + __raw_writel(0x00000064, &ddrmr->cr[124]);
> > +
> > + /* TDFI */
> > + __raw_writel(0x00000000, &ddrmr->cr[125]);
> > + __raw_writel(0x00000B00, &ddrmr->cr[126]);
> > + __raw_writel(0x00000000, &ddrmr->cr[127]);
> > +
> > + __raw_writel(0x00000000, &ddrmr->cr[131]);
> > + __raw_writel(0x00000506, &ddrmr->cr[132]);
> > + __raw_writel(0x02000000, &ddrmr->cr[137]);
> > + __raw_writel(0x04070303, &ddrmr->cr[139]);
> > +
> > + __raw_writel(0x00000000, &ddrmr->cr[136]);
> > +
> > + __raw_writel(0x68200000, &ddrmr->cr[154]);
> > + __raw_writel(0x00000202, &ddrmr->cr[155]);
> > + __raw_writel(0x00000006, &ddrmr->cr[158]);
> > + __raw_writel(0x00000006, &ddrmr->cr[159]);
> > +
> > + ddr_phy_init();
> > +
> > + __raw_writel(0x00000601, &ddrmr->cr[0]);
> > +
> > + udelay(200);
> > +}
>
>
> Ditto. There are a lot of magical numbers here associated to magic
> indexes.
>
> > +
> > +static void clock_init(void)
> > +{
> > + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
> > + struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
> > +
> > + __raw_writel(0x00000078, &ccm->clpcr);
> > + __raw_writel(0x000fc000, &ccm->ccgr0);
> > + __raw_writel(0xf00fc0c0, &ccm->ccgr1);
> > + __raw_writel(0x0fff0303, &ccm->ccgr2);
> > + __raw_writel(0x00000033, &ccm->ccgr3);
> > + __raw_writel(0x33f0f003, &ccm->ccgr4);
> > + __raw_writel(0x3003cc00, &ccm->ccgr6);
> > + __raw_writel(0x0000033c, &ccm->ccgr7);
> > + __raw_writel(0x0000000f, &ccm->ccgr9);
> > +
> > + __raw_writel(0x00002001, &anadig->pll2_ctrl);
> > + __raw_writel(0x00011001, &anadig->pll5_ctrl);
> > + __raw_writel(0x00002001, &anadig->pll1_ctrl);
> > +
> > + __raw_writel(0x00010005, &ccm->ccr);
> > + __raw_writel(0x0003ff64, &ccm->ccsr);
> > + __raw_writel(0x00000810, &ccm->cacrr);
> > + __raw_writel(0x03cf0000, &ccm->cscmr1);
> > + __raw_writel(0x01000000, &ccm->cscdr1);
> > + __raw_writel(0x30004240, &ccm->cscdr2);
> > + __raw_writel(0x00003f1f, &ccm->cscdr3);
> > + __raw_writel(0, &ccm->cscmr2);
> > + __raw_writel(0, &ccm->cscdr4);
> > +}
>
> The same here. Note that in most boards we use clrsetbits_le32() to set
> the single bits and all bits are defined in the crm_regs.h.
[Alison Wang] Agree, I will change them. Thanks.
>
> > +int board_eth_init(bd_t *bis)
> > +{
> > + int ret;
> > +
> > + setup_iomux_enet();
> > +
> > + ret = cpu_eth_init(bis);
> > + if (ret)
> > + printf("FEC MXC: %s:failed\n", __func__);
> > +
> > + return 0;
> > +}
>
> Maybe not useful ? I mean, if you move setup_iomux_enet() into
> board_early_init_f(), you can drop this function, because it simply calls
> cpu_eth_init()
[Alison Wang] Agree, I will drop this funtion, and move setup_iomux_enet() into board_early_init_f(). Thanks.
>
> > diff --git a/include/configs/mvf600twr.h b/include/configs/mvf600twr.h
> > new file mode 100644 index 0000000..bb1f3ef
> > --- /dev/null
> > +++ b/include/configs/mvf600twr.h
> > @@ -0,0 +1,147 @@
> > +/*
> > + * Copyright 2013 Freescale Semiconductor, Inc.
> > + *
> > + * Configuration settings for the Freescale Vybrid mvf600twr board.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#ifndef __CONFIG_H
> > +#define __CONFIG_H
> > +
> > +#include <asm/arch/imx-regs.h>
> > +#include <config_cmd_default.h>
> > +
> > +#define CONFIG_MVF600
> > +
> > +#define CONFIG_DISPLAY_CPUINFO
> > +#define CONFIG_DISPLAY_BOARDINFO
> > +
> > +#define MACH_TYPE_VYBRID_VF6XX 4146
> > +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX
>
> Your choice, but maybe you could drop MACH_TYPE_VYBRID_VF6XX, because it
> is not used in any file.
[Alison Wang] Agree. I will drop it.
>
> > +
> > +#define CONFIG_SKIP_LOWLEVEL_INIT
> > +
> > +#define CONFIG_SYS_ICACHE_OFF
> > +#define CONFIG_SYS_CACHELINE_SIZE 64
>
> On the website, cache is marked "optional" in the figure. Does it mean
> that some SOC have instruction cache and other ones not ?
[Alison Wang] There is instruction cache on MVF600.
>
> Is this setup related to the fact that you use start.S inside armv7 and
> something is not compatible ?
[Alison Wang] No, I will drop it.
>
> > +
> > +/* Enable passing of ATAGs */
> > +#define CONFIG_CMDLINE_TAG
> > +
> > +/* Size of malloc() pool */
> > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 *
> 1024)
> > +
> > +#define CONFIG_BOARD_EARLY_INIT_F
> > +
> > +#define CONFIG_FSL_LPUART
> > +
> > +/* Allow to overwrite serial and ethaddr */ #define
> > +CONFIG_ENV_OVERWRITE
> > +#define CONFIG_SYS_UART_PORT (1)
> > +#define CONFIG_BAUDRATE 115200
> > +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600,
> 115200}
> > +
> > +#define CONFIG_CMD_BDI /* bdinfo */
> > +#define CONFIG_CMD_BOOTD
> > +#define CONFIG_CMD_CONSOLE /* coninfo */
> > +#define CONFIG_CMD_ELF
> > +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest
> */
> > +#define CONFIG_CMD_MISC
> > +#undef CONFIG_CMD_IMLS
>
> You do not include cmd_default.h. Is it wanted ?
[Alison Wang] As I include config_cmd_default.h at the start of this file, I will drop these redundant options.
>
> > +
> > +/* MUX mode and PAD ctrl are in one register */ #define
> > +CONFIG_IOMUX_SHARE_CONF_REG
>
> NAK. This is not a board configuration, it is related to the SOC. This
> setup should flow into the related imx-regs.h for this SOC. When you set
> CONFIG_MVF600, this value should be set automatically.
[Alison Wang] Agree, I will move it to imx-regs.h. Thanks.
BTW, what's your suggestions about the other two patches, [PATCH v2 4/6] and [PATCH v2 5/6]?
Thanks.
Best regards,
Alison Wang
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board
2013-05-17 16:07 ` Stefano Babic
@ 2013-05-17 16:06 ` Benoît Thébaudeau
2013-05-17 16:57 ` Stefano Babic
0 siblings, 1 reply; 25+ messages in thread
From: Benoît Thébaudeau @ 2013-05-17 16:06 UTC (permalink / raw)
To: u-boot
Hi Stefano, Alison,
On Friday, May 17, 2013 6:07:43 PM, Stefano Babic wrote:
> On 17/05/2013 17:20, Wang Huan-B18965 wrote:
> > Hi, Stefano,
> >
>
> Hi Alison,
>
> >>> +void setup_iomux_ddr(void)
> >>> +{
> >>> + imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); }
> >>> +
> >>> +void ddr_phy_init(void)
> >>> +{
> >>> + struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
> >>> +
> >>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[0]);
> >>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[16]);
> >>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[32]);
> >>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[48]);
> >>> +
> >>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[1]);
> >>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[17]);
> >>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[33]);
> >>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[49]);
> >>> +
> >>> + __raw_writel(PHY_CTRL, &ddrmr->phy[2]);
> >>> + __raw_writel(PHY_CTRL, &ddrmr->phy[18]);
> >>> + __raw_writel(PHY_CTRL, &ddrmr->phy[34]);
> >>> + __raw_writel(PHY_CTRL, &ddrmr->phy[50]);
> >>> +
> >>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[3]);
> >>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[19]);
> >>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[35]);
> >>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[51]);
> >>> +
> >>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[4]);
> >>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[20]);
> >>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[36]);
> >>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[52]);
> >>> +
> >>
> >> Without reference manual, it is difficult to judge. But it is surely
> >> difficult to read. What does hide under the magic index of the ddrmr
> >> stucture ?
> > [Alison Wang] In the reference manual, the registers are named as phy00,
> > phy01, phy02.... cr00, cr01, cr02....
> > I think there may be some confusion if I rename the registers.
>
> Then the names of the registers are ok - I wanted only to be sure that
> what we read here is what we can find in the RM.
>
>
> >
> >
> > BTW, what's your suggestions about the other two patches, [PATCH v2 4/6]
> > and [PATCH v2 5/6]?
> > Thanks.
>
> Patches 4/6 and 5/6 are ok for me.
And what about my comments regarding 2/6 and 3/6? There has been no reply for
that so far.
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board
2013-05-17 15:20 ` Wang Huan-B18965
@ 2013-05-17 16:07 ` Stefano Babic
2013-05-17 16:06 ` Benoît Thébaudeau
0 siblings, 1 reply; 25+ messages in thread
From: Stefano Babic @ 2013-05-17 16:07 UTC (permalink / raw)
To: u-boot
On 17/05/2013 17:20, Wang Huan-B18965 wrote:
> Hi, Stefano,
>
Hi Alison,
>>> +void setup_iomux_ddr(void)
>>> +{
>>> + imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); }
>>> +
>>> +void ddr_phy_init(void)
>>> +{
>>> + struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
>>> +
>>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[0]);
>>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[16]);
>>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[32]);
>>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[48]);
>>> +
>>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[1]);
>>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[17]);
>>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[33]);
>>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[49]);
>>> +
>>> + __raw_writel(PHY_CTRL, &ddrmr->phy[2]);
>>> + __raw_writel(PHY_CTRL, &ddrmr->phy[18]);
>>> + __raw_writel(PHY_CTRL, &ddrmr->phy[34]);
>>> + __raw_writel(PHY_CTRL, &ddrmr->phy[50]);
>>> +
>>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[3]);
>>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[19]);
>>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[35]);
>>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[51]);
>>> +
>>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[4]);
>>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[20]);
>>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[36]);
>>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[52]);
>>> +
>>
>> Without reference manual, it is difficult to judge. But it is surely
>> difficult to read. What does hide under the magic index of the ddrmr
>> stucture ?
> [Alison Wang] In the reference manual, the registers are named as phy00, phy01, phy02.... cr00, cr01, cr02....
> I think there may be some confusion if I rename the registers.
Then the names of the registers are ok - I wanted only to be sure that
what we read here is what we can find in the RM.
>
>
> BTW, what's your suggestions about the other two patches, [PATCH v2 4/6] and [PATCH v2 5/6]?
> Thanks.
Patches 4/6 and 5/6 are ok for me.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board
2013-05-17 16:06 ` Benoît Thébaudeau
@ 2013-05-17 16:57 ` Stefano Babic
0 siblings, 0 replies; 25+ messages in thread
From: Stefano Babic @ 2013-05-17 16:57 UTC (permalink / raw)
To: u-boot
On 17/05/2013 18:06, Beno?t Th?baudeau wrote:
> Hi Stefano, Alison,
Hi Benoit,
>>> BTW, what's your suggestions about the other two patches, [PATCH v2 4/6]
>>> and [PATCH v2 5/6]?
>>> Thanks.
>>
>> Patches 4/6 and 5/6 are ok for me.
>
> And what about my comments regarding 2/6 and 3/6? There has been no reply for
> that so far.
Of course, the issues you mentioned must be fixed as well !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2013-05-17 16:57 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-05-14 9:51 [U-Boot] [PATCH v2 0/6] arm: mvf600: Add Freescale Vybrid MVF600 CPU and MVF600TWR board support Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support Alison Wang
2013-05-15 8:13 ` Stefano Babic
2013-05-15 12:09 ` Albert ARIBAUD
2013-05-15 12:24 ` Stefano Babic
2013-05-15 12:39 ` Albert ARIBAUD
2013-05-15 13:20 ` Stefano Babic
[not found] ` <81BA6E5E0BC2344391CABCEE22D1B6D8322144@039-SN1MPN1-002.039d.mgd.msft.net>
2013-05-15 14:23 ` [U-Boot] 答复: " Stefano Babic
2013-05-16 4:00 ` [U-Boot] " Wang Huan-B18965
2013-05-14 9:51 ` [U-Boot] [PATCH v2 2/6] arm: mvf600: Add IOMUX support for Vybrid MVF600 Alison Wang
2013-05-15 8:16 ` Stefano Babic
2013-05-15 13:53 ` Benoît Thébaudeau
2013-05-14 9:51 ` [U-Boot] [PATCH v2 3/6] arm: mvf600: Add FEC " Alison Wang
2013-05-15 8:15 ` Stefano Babic
2013-05-15 14:19 ` Benoît Thébaudeau
2013-05-14 9:51 ` [U-Boot] [PATCH v2 4/6] arm: mvf600: Add watchdog " Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 5/6] arm: mvf600: Add uart " Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board Alison Wang
2013-05-15 4:14 ` Shawn Guo
2013-05-15 8:11 ` Wang Huan-B18965
2013-05-15 9:01 ` Stefano Babic
2013-05-17 15:20 ` Wang Huan-B18965
2013-05-17 16:07 ` Stefano Babic
2013-05-17 16:06 ` Benoît Thébaudeau
2013-05-17 16:57 ` Stefano Babic
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