[U-Boot] [PATCH] OMAP5: Enable access to auxclk registers

Lubomir Popov
2013-05-15T14:41:01Z

auxclk0 and auxclk1 are utilized on some OMAP5 boards.
Define the infrastructure needed for accessing them
without using magic numbers.

Also remove unrelated TPS62361 defines from clocks.h

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
---
arch/arm/cpu/armv7/omap5/prcm-regs.c | 8 ++++++++
arch/arm/include/asm/arch-omap5/clocks.h | 32 ++++++++++++++----------------
arch/arm/include/asm/omap_common.h | 4 ++++
3 files changed, 27 insertions(+), 17 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index e9f6a32..5ba9bc4 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -307,6 +307,10 @@ struct prcm_regs const omap5_es1_prcm = {
.prm_sldo_mpu_ctrl = 0x4ae07bd0,
.prm_sldo_mm_setup = 0x4ae07bd4,
.prm_sldo_mm_ctrl = 0x4ae07bd8,
+
+ /* SCRM stuff, used by some boards */
+ .scrm_auxclk0 = 0x4ae0a310,
+ .scrm_auxclk1 = 0x4ae0a314,
};

struct omap_sys_ctrl_regs const omap5_ctrl = {
@@ -740,6 +744,10 @@ struct prcm_regs const omap5_es2_prcm = {
.prm_sldo_mpu_ctrl = 0x4ae07cd0,
.prm_sldo_mm_setup = 0x4ae07cd4,
.prm_sldo_mm_ctrl = 0x4ae07cd8,
+
+ /* SCRM stuff, used by some boards */
+ .scrm_auxclk0 = 0x4ae0a310,
+ .scrm_auxclk1 = 0x4ae0a314,
};

struct prcm_regs const dra7xx_prcm = {
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index 68afa76..6e23b1e 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -195,9 +195,9 @@
#define RSTTIME1_MASK (0x3ff << 0)

/* Clock frequencies */
-#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
+#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 /* Not used; remove? */
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
-#define OMAP_32K_CLK_FREQ 32768
+#define OMAP_32K_CLK_FREQ 32768 /* Not used; remove? */

/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
@@ -232,21 +232,6 @@
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000

-/* TPS */
-#define TPS62361_I2C_SLAVE_ADDR 0x60
-#define TPS62361_REG_ADDR_SET0 0x0
-#define TPS62361_REG_ADDR_SET1 0x1
-#define TPS62361_REG_ADDR_SET2 0x2
-#define TPS62361_REG_ADDR_SET3 0x3
-#define TPS62361_REG_ADDR_CTRL 0x4
-#define TPS62361_REG_ADDR_TEMP 0x5
-#define TPS62361_REG_ADDR_RMP_CTRL 0x6
-#define TPS62361_REG_ADDR_CHIP_ID 0x8
-#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
-
-#define TPS62361_BASE_VOLT_MV 500
-#define TPS62361_VSEL0_GPIO 7
-
/* Defines for DPLL setup */
#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
@@ -261,4 +246,17 @@
* into microsec and passing the value.
*/
#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
+
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK (1 << 8)
+#define AUXCLK_SRCSELECT_SHIFT 1
+#define AUXCLK_SRCSELECT_MASK (3 << 1)
+#define AUXCLK_CLKDIV_SHIFT 16
+#define AUXCLK_CLKDIV_MASK (0xF << 16)
+
+#define AUXCLK_SRCSELECT_SYS_CLK 0
+#define AUXCLK_SRCSELECT_CORE_DPLL 1
+#define AUXCLK_SRCSELECT_PER_DPLL 2
+#define AUXCLK_SRCSELECT_ALTERNATE 3
+
#endif /* _CLOCKS_OMAP5_H_ */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index ee7b188..76f65ed 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -346,6 +346,10 @@ struct prcm_regs {
u32 cm_l3init_usbphy_clkctrl;
u32 cm_l4per_mcbsp4_clkctrl;
u32 prm_vc_cfg_channel;
+
+ /* SCRM stuff, used by some boards */
+ u32 scrm_auxclk0;
+ u32 scrm_auxclk1;
};

struct omap_sys_ctrl_regs {
--
1.7.9.5